JPH0618250B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0618250B2 JPH0618250B2 JP23021984A JP23021984A JPH0618250B2 JP H0618250 B2 JPH0618250 B2 JP H0618250B2 JP 23021984 A JP23021984 A JP 23021984A JP 23021984 A JP23021984 A JP 23021984A JP H0618250 B2 JPH0618250 B2 JP H0618250B2
- Authority
- JP
- Japan
- Prior art keywords
- contact portion
- semiconductor device
- wiring
- circuit
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000012535 impurity Substances 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 claims description 10
- 238000009434 installation Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 20
- 238000009792 diffusion process Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の利用分野〕 本発明は、外部回路との接続部と、本体回路との間に、
基板と反対導電形の高濃度不純物層からなる保護抵抗を
有する保護回路を備えた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Use of the Invention] The present invention relates to a connection between an external circuit and a main circuit,
The present invention relates to a semiconductor device provided with a protection circuit having a protection resistance formed of a high-concentration impurity layer having a conductivity type opposite to that of a substrate.
一般に半導体装置は、人体に帯電した静電荷による静電
破壊や電源投入時のサージから本体回路を保護するため
に、外部回路との接続部と、本体回路との間に、基板と
反対導電形の高濃度不純物層からなる保護抵抗を備えた
保護回路が設けられる。Generally, a semiconductor device has a conductive type opposite to that of the substrate between a connection part with an external circuit and the main circuit in order to protect the main circuit from electrostatic discharge damage caused by electrostatic charge on the human body and surge at power-on. A protection circuit having a protection resistor formed of the high-concentration impurity layer is provided.
第１図に、従来用いられているこの種の保護回路部のレ
イアウトパターンの一例を示す。同図において、１は外
部回路との接続部としてのボンデイングパツドでＡｌか
ら構成されるが、このボンデイングパツド１からのサー
ジは、Ａｌ配線２を伝わり、コンタクト部３を介してｐ
形シリコン基板４内に形成されたｎ+拡散層５からなる
抵抗部へ導かれた後、コンタクト部６を介してＡｌ配線
７へ伝わる。その際、保護抵抗部でその波高値は減殺さ
れ、さらに、図中省略したがＡｌ配線７に接続された保
護MOSトランジスタでブレイクダウンして一定電位にク
ランプされる。なお、Ａｌ配線２とＡｌ配線７との間隙
部は、遮光用のＡｌ配線８で覆つてあるが、このＡｌ配
線８は、Ａｌ配線９を介して接地用Ａｌ配線１０に接続
され接地される。また、この保護抵抗部の周囲には、ｎ
+拡散層５部分の電位を一定に保つために同じくｎ+拡散
層１１からなるガードラインを配置してある。なお、Ａ
ｌ配線８は図中上方のＡｌ配線９と下方のＡｌ配線９と
を接続しているが、これは、ガードライン内のｐ形シリ
コン基板４の電位を一定に保つ役割もしている。FIG. 1 shows an example of a layout pattern of a protection circuit unit of this type which has been conventionally used. In the figure, reference numeral 1 denotes a bonding pad as a connecting portion to an external circuit, which is made of Al. The surge from the bonding pad 1 is transmitted through the Al wiring 2 and p through the contact portion 3.
After being guided to the resistance portion formed of the n + diffusion layer 5 formed in the silicon substrate 4, it is transmitted to the Al wiring 7 through the contact portion 6. At that time, the peak value is reduced by the protective resistance portion, and further, although omitted in the figure, the protective MOS transistor connected to the Al wiring 7 breaks down and clamps to a constant potential. Although a gap between the Al wiring 2 and the Al wiring 7 is covered with a light-shielding Al wiring 8, the Al wiring 8 is connected to the grounding Al wiring 10 via the Al wiring 9 and grounded. . In addition, n is provided around the protective resistance portion.
In order to keep the potential of + diffusion layer 5 constant, a guard line also made of n + diffusion layer 11 is arranged. In addition, A
The l-wiring 8 connects the upper Al wiring 9 and the lower Al wiring 9 in the figure, but this also serves to keep the potential of the p-type silicon substrate 4 in the guard line constant.
ここで、ガードラインを構成するｎ+拡散層11は、コン
タクト部１２によりその上に配置された上記Ａｌ配線９
に接続された接地用Ａｌ配線１０により接地されるが、
図示のような従来のパターンでは、抵抗を構成する拡散
層５とＡｌ配線２とのコンタクト部３が、接地電位とな
るコンタクト部１２に対し、図中矢印で示したようにき
わめて近接して配置されているために、この部分で破壊
しやすく、十分なサージ耐圧が得られなかつた。Here, the n + diffusion layer 11 forming the guard line is formed by the contact portion 12 on which the Al wiring 9 is formed.
It is grounded by the grounding Al wiring 10 connected to
In the conventional pattern as shown in the drawing, the contact portion 3 between the diffusion layer 5 and the Al wiring 2 which constitutes the resistor is arranged very close to the contact portion 12 which is at the ground potential as shown by the arrow in the figure. Therefore, it was easy to break in this part, and sufficient surge withstand voltage could not be obtained.
なお、このような従来の保護回路部の構造については、
例えば近代科学社刊「MOS集積回路」監訳、武石喜幸・
金山宏、昭和４９年１月１５日出販等に開示されてい
る。Regarding the structure of such a conventional protection circuit unit,
For example, Yoshiyuki Takeishi, translated by "Modern Science" published by "MOS Integrated Circuit"
It is disclosed in Hiroshi Kanayama, January 15, 1974 sales.
本発明はこのような事情に鑑みてなされたもので、その
目的は、保護回路のサージ耐圧を向上させた半導体装置
を提供することにある。The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device in which a surge withstand voltage of a protection circuit is improved.
このような目的を達成するために、本発明は、外部回路
との接続部と、本体回路と、上記接続部と本体回路との
間に設けられた保護抵抗と、該保護抵抗の周囲に設けら
れた不純物領域とを有し、上記不純物領域は第１の電位
が印加された配線に第１のコンタクト部で電気的に接続
され、上記外部回路との接続部から伸びる配線は上記保
護抵抗に第２のコンタクト部で電気的に接続され、上記
本体回路から伸びる配線は上記保護抵抗に第３のコンタ
クト部で電気的に接続され、かつ、上記第１のコンタク
ト部と第２のコンタクト部の間隔のうち最も短い距離
が、上記第２のコンタクト部と第３のコンタクト部の間
隔のうち最も短い距離より長くなるように設けられた半
導体装置とし、更に、上記外部回路との接続部から伸び
る配線の幅は、上記本体回路から伸びる配線の幅より広
く設けられた半導体装置とし、更に、上記保護抵抗は上
記不純物領域と同じ導電型の不純物領域である半導体装
置とし、更に、上記外部回路との接続部はボンデイング
パッドである半導体装置とし、更に上記保護抵抗の周囲
に設けられた不純物領域は、平面的に見て、上記保護抵
抗を完全に囲む如く設けられる半導体装置とし、更に、
上記第１の電位は設置電位である半導体装置とし、更に
上記第１のコンタクト部は複数のコンタクト孔を有する
半導体装置とし、更に上記第２のコンタクト部は複数の
コンタクト孔を有する半導体装置とし、更に、上記第３
のコンタクト部は複数のコンタクト孔を有する半導体装
置とした。In order to achieve such an object, the present invention provides a connection portion with an external circuit, a main body circuit, a protection resistor provided between the connection portion and the main body circuit, and a protection resistor provided around the protection resistor. The impurity region is electrically connected to the wiring to which the first potential is applied at the first contact portion, and the wiring extending from the connection portion with the external circuit serves as the protective resistance. The wiring electrically connected at the second contact portion and extending from the main body circuit is electrically connected to the protective resistance at the third contact portion, and the wiring of the first contact portion and the second contact portion is connected. The semiconductor device is provided such that the shortest distance among the distances is longer than the shortest distance among the distances between the second contact portion and the third contact portion, and further extends from the connection portion with the external circuit. The width of the wiring is above The semiconductor device is provided wider than the width of the wiring extending from the body circuit, the protection resistor is a semiconductor device having an impurity region of the same conductivity type as the impurity region, and the connecting portion to the external circuit is a bonding pad. And a semiconductor device in which the impurity region provided around the protection resistor is provided so as to completely surround the protection resistor in plan view.
The first potential is a semiconductor device having a ground potential, the first contact portion is a semiconductor device having a plurality of contact holes, and the second contact portion is a semiconductor device having a plurality of contact holes. Furthermore, the third
The contact portion was a semiconductor device having a plurality of contact holes.
次に、第２図を用いて本発明の実施例を説明する。第２
図(a)は第１図と同様の平面パターン図、第２図(b)はｂ
−ｂ断面図で、第１図と同一もしくは相当部分は同一記
号を用いて表わしている。なお、１３は層間絶縁膜であ
る。Next, an embodiment of the present invention will be described with reference to FIG. Second
Figure (a) is the same plane pattern as Figure 1, and Figure 2 (b) is b.
In the -b sectional view, the same or corresponding portions as in FIG. 1 are represented by the same symbols. Reference numeral 13 is an interlayer insulating film.
第２図と第１図とを比較して明らかな通り、本実施例で
はガードラインを構成するｎ+拡散層11上のＡｌ配線の
パターンを、第１図の９から9Aのように変更し、外部回
路に接続するＡｌ配線2Aに近接した部分のコンタクト部
12A，12Bおよび12E，12Fを除去してある。この結果、コ
ンタクト部３に最も近い接地電位のコンタクト部１２
は、12Cおよび12Gとなり、その間の距離は第１図のコン
タクト部12Bないし12Fに比較して格段に大きくなるため
に、耐圧が向上する。なお、この場合、ｎ+拡散層１１
それ自体、あるいはＡｌ配線１０は、本実施例において
も第１図と同様に構成されコンタクト部３に近接した部
分にも延在しているが、コンタクト部１２がない部分で
は余り問題にならない。すなわち、耐圧に最も直接関係
するのは、外部回路に接続するＡｌ配線2Aと保護抵抗を
構成するｎ+拡散層５とを接続するコンタクト部３、こ
れと、接地用Ａｌ配線１０に接続するＡｌ配線9Aとのコ
ンタクト部１２がある部分のｎ+拡散層１１、この両者
の間の距離である。As is clear from comparison between FIG. 2 and FIG. 1, in this embodiment, the pattern of the Al wiring on the n + diffusion layer 11 forming the guard line is changed from 9 to 9A in FIG. , The contact part near the Al wiring 2A connected to the external circuit
12A, 12B and 12E, 12F have been removed. As a result, the contact portion 12 of the ground potential closest to the contact portion 3
Is 12C and 12G, and the distance between them is much larger than that of the contact portions 12B to 12F in FIG. 1, so that the breakdown voltage is improved. In this case, the n + diffusion layer 11
In itself, or in the present embodiment, the Al wiring 10 is also constructed in the same manner as in FIG. 1 and extends to the portion close to the contact portion 3, but in the portion without the contact portion 12, it does not become a problem. That is, the withstand voltage is most directly related to the contact portion 3 for connecting the Al wiring 2A connected to the external circuit and the n + diffusion layer 5 forming the protective resistance, and the Al connecting to the Al wiring 10 for grounding. This is the distance between the n + diffusion layer 11 in the portion where the contact portion 12 with the wiring 9A is present and between both.
本実施例では、外部回路との接続部であるボンデイング
パツド１とｎ+拡散層５とを接続するＡｌ配線２Ａの幅W
2を50μｍとし、第１図における同様のＡｌ配線２の幅
Ｗ１≒40μｍに比較して広くとつてある。これは、電流
密度を小さくして電流の集中を避けるためで、これによ
りさらに耐圧を上げる効果があり、本実施例では従来第
１図のパターンにおけるサージ耐圧より数十Ｖに向上さ
せることができた。なお、ここでサージ耐圧とは、200p
Fにチャージした電荷をスイツチを切換えてデバイスに
印加し、デバイスが破壊されたときのコンデンサにチヤ
ージした電圧とする（負荷抵抗０Ω）。In this embodiment, the width W of the Al wiring 2A connecting the bonding pad 1 and the n + diffusion layer 5, which is the connection portion with the external circuit, is W.
2 is 50 μm, which is wider than the width W1 of the similar Al wiring 2 in FIG. 1 ≈40 μm. This is because the current density is reduced to avoid current concentration, and this has the effect of further increasing the breakdown voltage. In this embodiment, it is possible to improve the surge breakdown voltage to several tens of volts compared to the conventional surge breakdown voltage shown in FIG. It was The surge withstand voltage here is 200p.
The charge charged in F is applied to the device by switching the switch, and the voltage is charged to the capacitor when the device is destroyed (load resistance 0Ω).
〔発明の効果〕 以上説明したように、本発明によれば、外部回路との接
続用配線層に近接した部分には、ガードラインを構成す
る接地電位の高濃度不純物層とその上の配線層とのコン
タクト部を設けないようにして、上記コンタクト部があ
る部分の高濃度不純物層と、上記接続用配線層と保護抵
抗とのコンタクト部との間の距離を大きくとるようにし
たことにより、保護回路のサージ耐圧を向上させ、半導
体装置の信頼性を向上させることができる。As described above, according to the present invention, the high-concentration impurity layer of the ground potential forming the guard line and the wiring layer thereabove are formed in the portion close to the wiring layer for connection with the external circuit. By not providing a contact portion with the high concentration impurity layer in the portion where the contact portion is present, and by increasing the distance between the contact portion of the connection wiring layer and the protective resistance, The surge withstand voltage of the protection circuit can be improved, and the reliability of the semiconductor device can be improved.
第１図は従来の半導体装置の保護回路部の構成例を示す
平面パターン図、第２図(a)は本発明の一実施例を示す
平面パターン図、同図(b)はｂ−ｂ断面図である。 １……外部回路に接続するボンデイングパツド、２，2
A,7,8,9,9A,10……Ａｌ配線層、３……第２のコンタク
ト部、４……ｐ形シリコン基板、５……保護抵抗を構成
するｎ+拡散層、６……コンタクト部、11……ガードラ
インを構成するｎ+拡散層、12……第１のコンタクト
部。FIG. 1 is a plan pattern diagram showing a configuration example of a protection circuit portion of a conventional semiconductor device, FIG. 2 (a) is a plan pattern diagram showing one embodiment of the present invention, and FIG. 1 (b) is a bb cross section. It is a figure. 1 ... Bonding pad to connect to external circuit, 2, 2
A, 7,8,9,9A, 10 ... Al wiring layer, 3 ... second contact part, 4 ... p-type silicon substrate, 5 ... n + diffusion layer constituting protective resistance, 6 ... Contact part, 11 ... n + diffusion layer forming the guard line, 12 ... first contact part.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 上原 正男 千葉県茂原市早野3300番地 株式会社日立 製作所茂原工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masao Uehara 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Mobara factory
Claims (9)
接続部と本体回路との間に設けられた保護抵抗と、該保
護抵抗の周囲に設けられた不純物領域とを有し、 上記不純物領域は第１の電位が印加された配線に第１の
コンタクト部で電気的に接続され、 上記外部回路との接続部から伸びる配線は上記保護抵抗
に第２のコンタクト部で電気的に接続され、 上記本体回路から伸びる配線は上記保護抵抗に第３のコ
ンタクト部で電気的に接続され、かつ、 上記第１のコンタクト部と第２のコンタクト部の間隔の
うち最も短い距離が、上記第２のコンタクト部と第３の
コンタクト部の間隔のうち最も短い距離より長くなるよ
うに設けられたことを特徴とする半導体装置。1. A connection part to an external circuit, a main body circuit, a protective resistor provided between the connection part and the main body circuit, and an impurity region provided around the protective resistor, The impurity region is electrically connected to the wiring to which the first potential is applied at the first contact portion, and the wiring extending from the connection portion with the external circuit is electrically connected to the protection resistor at the second contact portion. The wiring that is connected and extends from the main circuit is electrically connected to the protection resistor at the third contact portion, and the shortest distance between the first contact portion and the second contact portion is the above. A semiconductor device provided so as to be longer than a shortest distance among the distances between the second contact portion and the third contact portion.
幅は、上記本体回路から伸びる配線の幅より広く設けら
れたことを特徴とする特許請求の範囲第１項記載の半導
体装置。2. The semiconductor device according to claim 1, wherein the width of the wiring extending from the connection portion with the external circuit is set wider than the width of the wiring extending from the main circuit.
型の不純物領域であることを特徴とする特許請求の範囲
第１項又は第２項記載の半導体装置。3. The semiconductor device according to claim 1, wherein the protection resistor is an impurity region of the same conductivity type as the impurity region.
ッドであることを特徴とする特許請求の範囲第１項乃至
第３項の何れかに記載の半導体装置。4. The semiconductor device according to claim 1, wherein the connection portion with the external circuit is a bonding pad.
域は、平面的に見て、上記保護抵抗を完全に囲む如く設
けられることを特徴とする特許請求の範囲第１項乃至第
４項の何れかに記載の半導体装置。5. The impurity region provided around the protection resistor is provided so as to completely surround the protection resistor in plan view. The semiconductor device according to any one of 1.
徴とする特許請求の範囲第１項乃至第５項の何れかに記
載の半導体装置。6. The semiconductor device according to any one of claims 1 to 5, wherein the first potential is an installation potential.
ト孔を有することを特徴とする特許請求の範囲第１項乃
至第６項の何れかに記載の半導体装置。7. The semiconductor device according to claim 1, wherein the first contact portion has a plurality of contact holes.
ト孔を有することを特徴とする特許請求の範囲第１項乃
至第７項の何れかに記載の半導体装置。8. The semiconductor device according to claim 1, wherein the second contact portion has a plurality of contact holes.
ト孔を有することを特徴とする特許請求の範囲第１項乃
至第８項の何れかに記載の半導体装置。9. The semiconductor device according to claim 1, wherein the third contact portion has a plurality of contact holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23021984A JPH0618250B2 (en) | 1984-11-02 | 1984-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23021984A JPH0618250B2 (en) | 1984-11-02 | 1984-11-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61110455A JPS61110455A (en) | 1986-05-28 |
| JPH0618250B2 true JPH0618250B2 (en) | 1994-03-09 |
Family
ID=16904421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23021984A Expired - Lifetime JPH0618250B2 (en) | 1984-11-02 | 1984-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618250B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2982491B2 (en) * | 1992-06-15 | 1999-11-22 | 日本電気株式会社 | Semiconductor protection element |
| JPH0629154U (en) * | 1992-09-10 | 1994-04-15 | 横河電機株式会社 | Semiconductor integrated circuit |
-
1984
- 1984-11-02 JP JP23021984A patent/JPH0618250B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61110455A (en) | 1986-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5682047A (en) | Input-output (I/O) structure with capacitively triggered thyristor for electrostatic discharge (ESD) protection | |
| US4994874A (en) | Input protection circuit for semiconductor integrated circuit device | |
| US4509067A (en) | Semiconductor integrated circuit devices with protective means against overvoltages | |
| US5477407A (en) | Protection circuit for protecting a semiconductor device from a voltage surge | |
| US4739438A (en) | Integrated circuit with an improved input protective device | |
| US5706156A (en) | Semiconductor device having an ESD protective circuitry | |
| US5365103A (en) | Punchthru ESD device along centerline of power pad | |
| JP2965264B2 (en) | Snapback device triggered by low voltage | |
| KR960030397A (en) | Protection circuit of semiconductor integrated circuit | |
| JP2906749B2 (en) | Gate protection device for semiconductor device | |
| US4922316A (en) | Infant protection device | |
| JPH0618250B2 (en) | Semiconductor device | |
| JPH08181219A (en) | Semiconductor integrated circuit device | |
| US5113230A (en) | Semiconductor device having a conductive layer for preventing insulation layer destruction | |
| JPS6221018Y2 (en) | ||
| US6538291B1 (en) | Input protection circuit | |
| JP2676899B2 (en) | Input circuit protection device for MOS integrated circuit device | |
| JP3185723B2 (en) | Semiconductor device | |
| JPH07147384A (en) | Semiconductor device | |
| US5432369A (en) | Input/output protection circuit | |
| JP2585633B2 (en) | Semiconductor device | |
| JPS63291470A (en) | Protective circuit for semiconductor integrated circuit device | |
| JPH0454978B2 (en) | ||
| JPH05160341A (en) | Capacitor for removing noise from integrated circuit device | |
| JPS60115253A (en) | Semiconductor integrated circuit device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |