JPH06180945A - Optical recorder/player - Google Patents

Abstract

PURPOSE:To solve a problem that recording or reproduction of a signal is interrupted due to time lag caused by switching of a timing clock at the time of zone switching when recording or reproduction is carried out onto/from a recording medium by means of a focused optical beam. CONSTITUTION:Light reflected on a recording medium 101 is converted through an optical detector ill into current which is further converted through an I/V converter 114 into a voltage waveform which is then binarized through a binarization circuit 118. A CK mark detecting circuit 117 detects sync signal and a timing clock generator 119 generates timing clocks for tracking servo and address reading based on the sync signal. A control circuit 121 detects current track through an address reaching circuit 120 and controls second and third oscillation circuits to oscillate at timing clocks suitable, respectively, to that zone and a zone to be accessed next thus switching the timing clocks upon gaining access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical reproducing apparatus for recording information on a recording medium with a focused light beam or reproducing the recorded information. Regarding sample format format.

[0002]

2. Description of the Related Art In recent years, an optical recording / reproducing apparatus holds a large amount of data in a recording medium and can reproduce it, so that it occupies an important position in recording and reproducing audio information data, video information data, and various information equipment data. ing.

FIG. 15 shows a recording state on a recording medium of a sample format type in a conventional optical recording / reproducing apparatus. In FIG. 15, reference numeral 1501 denotes a recording medium substrate,
For example, it is formed of a resin such as polycarbonate having a thickness of 1.2 mm, and a clock mark (also called a clock pit) 1505 and tracking marks (also called a wobble mark) 1506, 1507 which are also called wobble marks are injected on one surface. And the like. A servo area 1503 including the clock mark 1505 and the tracking marks 1506 and 1507 is formed radially from the center of the recording medium substrate 1501, and the clock mark 1505 for clock reading is centered on each track indicated by a chain line 1504.
Are arranged, and are then slightly deviated (for example, by 1/4 track pitch) on both sides of the track center line, and tracking marks 150 for tracking servo are formed.
6, 1507 are provided. And each servo area 1
Between 503, information areas 1508 are also formed radially. And Te (tellurium) is on the surface.
Recording thin film 15 made of a phase change recording material containing
02 is formed by a method such as sputtering.

Assuming that the recording medium of the sample format described above is rotated at a constant angular velocity as a premise, in order to effectively use the radial information area 1508, information recording of the information area 1508 portion between the servo areas 1503 is performed. The density should be closer to the outer circumference. For example, the surface of the recording thin film 1502 is concentrically divided into four zones (zones 0 to 3). For example, one information area in zone 0 has 10 bytes, and zone 1 has 14 bytes.
The amount of information is increased toward the outer periphery, such as 18 bytes for zone 2 and 22 bytes for zone 3.

[0005]

However, in order to make the information density of the recording medium closer to the outer circumference, the timing clock frequency for reading or writing the information is different for each zone, and the higher the outer circumference is, the higher the timing clock frequency is. If the timing clock for reading the address recorded on the recording medium or the timing clock for detecting the peak value of the wobble mark and the timing clock for reading or writing the information are combined, the frequency becomes It will be extremely high.

For example, the frequency of the timing clock for zone 0, zone 1, zone 2, and zone 3 is set to 10M.
Hz, 14 MHz, 18 MHz, 22 MHz, 10 MHz is used as a timing clock for detecting the position of the wobble mark, and a timing clock for detecting the peak value of the wobble mark and a timing clock for reading or writing information are used. Combined use, 10 MHz in zone 0 and 10 M in zone 1
70 MHz, which is the least common multiple of Hz and 14 MHz, and 9 which is the least common multiple of 10 MHz and 18 MHz in Zone 2.
At 0 MHz, in zone 3, the least common multiple of 10 MHz and 22 MHz is 110 MHz, and it is necessary to obtain a timing clock of a predetermined frequency by dividing the timing clock of these frequencies. Further, if it is intended to realize high density recording by providing versatility in zone division, for example, the timing clock for zone 0 is 9.85 MHz and that for zone 1 is 1
A frequency such as 4.8 MHz is required, and a clock with a higher frequency is required. Also, when the timing clock for reading the address and the timing clock for reading or writing the information are both used, the frequency becomes extremely high as well.

As described above, the conventional optical recording / reproducing apparatus has a problem that the circuit is complicated and expensive because it is necessary to handle a high frequency clock. Also,
In order to solve this, the zone division method is limited due to the limitation of the clock frequency, and high-density recording cannot be performed.

Further, in the conventional optical recording / reproducing apparatus, in order to make the information density of the recording medium closer to the outer circumference, the timing clock frequency for reading or writing information is different for each zone, and the timing clock frequency is closer to the outer circumference. Since it is necessary to increase the frequency, a PLL circuit normally used as a timing clock generation circuit requires a pull-in time of 3 to 5 mS when switching the timing clock frequency. There is a problem that signal recording or reproduction cannot be performed.

The present invention solves the above-mentioned conventional problems, enables high-density recording and reproduction with a low-frequency timing clock, and instantaneously records or reproduces a signal when a desired track is searched. It is an object of the present invention to provide a simple and inexpensive optical recording / reproducing device capable of starting reproduction.

[0010]

In order to achieve this object, an optical recording / reproducing apparatus of the present invention is, as a first invention,
A plurality of clock marks for synchronization are provided per spiral on a spiral or concentric track, which is rotated at a constant angular velocity, and the clock marks are radial with respect to the locus connecting them with those of adjacent tracks. The information area, which is arranged in such a manner that it is divided into at least two zones in the radial direction, can store information such that the amount of information per circle is larger in the outer zone than in the inner zone. A device for irradiating a light beam on a recording medium to record information or reproducing recorded information, the converting device converting the information recorded on a recording medium into an electric signal, and the signal of the converting device. Sync signal detecting means for detecting a sync signal corresponding to the clock mark, and the same for recording information on the recording medium or reading the recorded information. Two timing clock generating means capable of respectively generating timing clocks of one or a plurality of frequencies synchronized with a signal, and a track in which a current light beam is located in one of the two timing clock generating means A timing clock having a frequency matching the zone of the track, and instructing another one of the two timing clock generating means to generate a timing clock having a frequency matching the zone of the track to be transferred next. It is configured to have a control means for controlling.

In addition to the first invention, a second invention is provided with at least one address per circle for identifying a position, and the address is synchronized with the clock mark in all tracks, An apparatus using a recording medium recorded so that it can be reproduced at the same timing clock, the converting means converting the information recorded on the recording medium into an electric signal, and the clock mark from the signal of the converting means. And a first timing clock generation means for generating a timing clock having a first frequency based on the synchronization signal detected by the synchronization signal detection means;
An address reading circuit for reading the address recorded on the recording medium by judging the signal of the converting means based on the timing clock from the timing clock generating means, and recording or recording the information on the recording medium. 1 synchronized with the sync signal to read the existing information
Second and third timing clock generating means capable of respectively generating timing clocks of one kind or a plurality of kinds of frequencies, and a zone in which the light beam on the recording medium is located based on the address read by the address reading circuit, or The zone to be searched and transitioned is determined, and a timing clock having a frequency suitable for the zone of the track where the current light beam is located is generated in one of the second or third timing clock generating means, and The other of the second or third timing clock generating means is provided with a control means for instructing to generate a timing clock having a frequency suitable for the zone of the track to be transferred next.

In a third invention, the first timing clock generating means in the second invention records information in a specific zone on the recording medium based on the synchronization signal detected by the synchronization signal detecting means, or The control means generates a timing clock of a first frequency for reading the recorded information, and the control means is a zone or transition where the light beam on the recording medium is located based on the address read by the address reading circuit. , The zone to be searched is determined, and if it is the specific zone, the output of the first timing clock generating means is selected, and if it is another zone, one of the second or third timing clock generating means is selected. Instructs to generate a timing clock with a frequency that matches the zone of the desired track and let it be selected. It is configured so that.

[0013]

In the first aspect of the present invention, the information recorded on the recording medium is converted into an electric signal by the converting means, and the synchronizing signal is detected from the clock mark of the recording medium by the synchronizing signal detecting means. The control means generates one of the two timing clock generating means based on the synchronizing signal, and generates a timing clock having a frequency suitable for the zone of the track where the current light beam is located. A timing clock having a frequency suitable for the zone of the track to be moved next is generated on the other side of the timing clock generating means of the above, and the timing clock is selected along with the movement of the light beam to select the information on the recording medium. Acts to record or read recorded information.

In the second invention, the timing clock of the first frequency is generated by the first timing clock generating means in synchronization with the synchronization signal detected from the clock mark of the recording medium, and the recording medium is based on this. The address recorded on the address is read by the address reading circuit, the control means determines the zone where the light beam is located on the recording medium based on the read address,
Alternatively, when searching for a desired track based on the address read by the address reading circuit, either the second or third timing clock generating means is used to generate a timing clock having a frequency suitable for the zone of the track. It controls to select one of the timing clocks of the second or third timing clock generating means according to the zone to record information on the recording medium or read the recorded information.

Further, in the third invention, the control means determines the zone where the light beam is located on the recording medium or the zone to be searched based on the address read by the address reading circuit, and the specific zone is determined. If there is, the output of the first timing clock generating means is selected, and if there is another zone, one of the second or third timing clock generating means is used to generate a timing clock having a frequency suitable for the zone of the desired track. It will act to select that output.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An optical recording / reproducing apparatus according to embodiments of the present invention will be described below with reference to the drawings. First of the present invention
1 of the block diagram showing the embodiment, the phase change type recording medium 101 is attached to the rotating shaft 102a of the motor 102 and rotated at a predetermined angular velocity. Transfer stand 10
4, a light source 105 such as a semiconductor laser, a coupling lens 106, a polarization beam splitter 107,
Quarter wave plate 108, total reflection mirror 109, photodetector 111
A fixed portion (not shown) of the actuator 112 is attached, and the transfer table 104 is configured to move in the radial direction of the recording medium 101 by the transfer motor 103 such as a linear motor.

An optical beam generated by a light source 105 such as a semiconductor laser arranged in the transfer table 104 is collimated by a coupling lens 106 and then polarized by a polarization beam splitter 107, 1/4. After passing through the wave plate 108, the total reflection mirror 1
09, the recording medium 10 is reflected by the focusing lens 110.
The first recording surface is focused and irradiated. The reflected light reflected by the recording surface of the recording medium 101 passes through the focusing lens 110, is reflected by the total reflection mirror 109, and is reflected by the quarter wavelength plate 10.
After passing through 8, the light is reflected by the polarization beam splitter 107 and irradiated onto the photodetector 111. Focusing lens 110
Is attached to the movable part of the actuator 112. The actuator 112 is composed of a tracking coil 113 provided in the movable part and a permanent magnet (not shown) attached to the fixed part. Therefore, when an electric current is passed through the tracking coil 113, the focusing lens 110 is moved in the radial direction of the recording medium 101, that is, across the track on the recording medium 101 (in the figure, by the electromagnetic force received by the coil from the permanent magnet). Move left and right). Further, a focus coil (not shown) is also attached to the movable portion of the actuator 112, and when a current is passed through this coil, the focusing lens 1 is generated by an electromagnetic force received by the coil from a permanent magnet (not shown).
10 is configured to be movable in a direction perpendicular to the surface of the recording medium 101. The focusing lens 110 is focus-controlled so that the light beam irradiated on the recording medium 101 is always in a predetermined focusing state.

The output of the photodetector 111 is input to an I / V converter 114 that converts a current into a voltage, and the photodetector 111 is output.
Output current is converted to voltage and output. I / V converter 1
One of the output signals of 14 is the tracking error detector 11
5 and the tracking error detector 115 shown in FIG.
A tracking error is detected from the position of the focused light with respect to the first and second tracking marks shown in FIG. That is, the tracking error detector 115 is the I / V converter 1
The peak values of the first and second tracking marks are detected from the output signal of 14 and the difference between the two peak values is obtained. And
This tracking error signal is applied to the actuator 112 via the control circuit 116, and tracking control is performed so that the light beam on the recording medium 101 is located between the first and second tracking marks, that is, on the center line of the track. .

Further, the transfer motor 10 is transferred from the control circuit 116.
In addition to 3, the transfer table 104 is transferred and controlled so that the focusing lens 110 moves in the radial direction of the recording medium around the natural state.

The output signal of the I / V converter 114 is a clock (CK) mark detection circuit 117 and a binarization circuit 11.
It is entered in 8. The binarization circuit 118 binarizes the output signal of the I / V converter 114 and sends the binarized signal to the CK mark detection circuit 117. CK mark detection circuit 117
Detects the clock mark position and differentiates the clock mark signal to output a synchronization signal corresponding to the clock mark. The timing clock generation circuit 119 is C
Timing for generating various signals in synchronization with the synchronization signal of the K mark detection circuit 117, generating a period signal indicating each position of the tracking mark and sending it to the tracking error detector 115, and timing for address reading. Address read circuit 12 for generating a clock
Send to 0. The timing clock generation circuit 119 also generates a timing clock for reading data and sends it to the data reading circuit 123. The address reading circuit 120 is inputted with the binarized signal of the binarizing circuit 118 and the timing clock for address reading from the timing clock generating circuit 119. The address reading circuit 120 determines whether the binarized signal is 1 or 0 based on the timing clock, reads the address on the recording medium, and reads the read address from the control circuit 121.
Send to. A circuit for generating a timing clock for reading data in the timing clock generation circuit 119 is configured to generate a timing clock suitable for each zone of the recording medium according to an instruction from the control circuit 121. The control circuit 121 controls the timing clock generation circuit 119 based on the address read by the address reading circuit 120 to generate a timing clock for data reading corresponding to the zone corresponding to the address position, and the timing clock generation circuit 119 This timing clock for reading data is sent to the data reading circuit 123. The binarization signal from the binarization circuit 118 is also input to the data reading circuit 123, and the data reading circuit 123 determines the binarization signal based on the data reading clock signal from the timing clock generation circuit 119. Recording medium 10
Read the information recorded on 1.

Before entering the detailed description of the circuit operation, how the data on the recording medium 101 is arranged will be described. FIG. 3 conceptually shows the format on the recording medium. As shown in FIG. 3A, servo areas and information areas are alternately arranged on the tracks on the recording medium. And the information area form one block. Then, as shown in FIG. 3B, one sector is composed of (n + 1) blocks, and the information area of the first block of the sector is an address area in which an address for identifying the position of the sector is recorded. And the data is recorded in the information area of the n blocks following it. This address does not necessarily have to be provided at one location for each sector as shown in the figure, and access is possible if there is at least one location for one track. Next, Fig. 3
As shown in (c), one track in a certain zone is composed of m sectors, and when one track cannot be divided by one sector length, a surplus area is provided at the end of the track.

FIG. 4 conceptually shows the time intervals of the address pits recorded in the address area provided at the head of each sector and the data pits recorded in the data area. Similar to the servo area, the address pits in the address area are also recorded in a radial pattern on the recording medium regardless of the zone. That is, when the recording medium is rotated at a constant angular acceleration, the clock frequency for address reading is recorded so as to be constant regardless of the zone. This is to enable the address to be read immediately when searching for a desired track and to realize high-speed searching. For example, if the address is recorded so that the timing clock for reading the address of the entire area and the timing clock for detecting the respective positions of the tracking marks can also be used, the timing clock generation circuit can also be used, and the circuit can be simplified. You can Further, the addresses of all areas are recorded so that they can be read by the timing clock for reading the data recorded in the innermost zone 0, and the timing clock for reading the address and the data for reading the data recorded in the zone 0 are also used. You may record as you do.

The amount of data recorded in the data area is the same in the same zone, but as shown in the figure, the amount of data is increased in the outer peripheral zone. Generally, the data mark interval that can be read by the light beam spot on the recording medium is determined by the size of the light beam spot. Since the servo areas are radially formed, the distance between the servo areas becomes wider toward the outer circumference of the recording medium, and therefore the amount of data that can be recorded in one data area can be increased. For this reason, in this embodiment, the capacity is increased by dividing the recording medium into zones in the radial direction and increasing the amount of data recorded in one data area in the outermost zones. For example, 10 bytes are recorded in one data area of zone 0, 14 bytes are recorded in zone 1, 18 bytes are recorded in zone 2, and 22 bytes are recorded in zone 3. That is, the data is recorded so that the spatial frequency of the data pits in the data area in the innermost track of each zone is substantially constant. Then, the clock frequency for data reproduction in the data area inevitably becomes higher in the outer zone.

The data amount per sector is 102, for example.
It is constant at 4 bytes. However, since the amount of data per rotation of the recording medium differs depending on the zone, the number of sectors per rotation also differs depending on the zone. Therefore,
The number of addresses also inevitably differs depending on the zone. Figure 5
As shown in FIG. 5, if the addresses of a sector of a certain number, for example, sector 1 are provided so as to be radially arranged in the radial direction of the recording medium over all zones, the addresses of other sectors are arranged radially in the same zone. , The addresses of other zones are not necessarily arranged radially. However, since an address mark that can identify the address position is also recorded at each address, it is possible to instantaneously read based on this address mark.

The timing clock generation circuit 119 of FIG.
Will be described with reference to FIG. 2, which is a block diagram thereof.
The timing clock generation circuit 119 includes three timing generation means, that is, a PLL (phase locked loop) 21.
0, 220, 230 are provided. The PLL 210, which is the first timing clock generation means, generates a timing clock for reading an address and detecting the position of the tracking mark, and the phase comparator 2
11, a VCO (voltage controlled oscillator) 212 and a frequency divider 213. The PLL 220, which is the second timing clock generation means, includes the phase comparator 2
21, a VCO 222, and a frequency divider 223, and is a PLL 230 which is a third timing clock generating means.
Is a phase comparator 231, a VCO 232 and a frequency divider 23.
It is composed of three. The PLLs 220 and 230 generate timing clocks for reading the data recorded in the data area on the recording medium.

First, the operation of the PLL 210 will be described. The VCO 212 generates a signal having a frequency corresponding to the input signal, and the frequency divider 213 frequency-divides the frequency of the output signal of the VCO 212 into an integer and sends the frequency-divided signal to the phase comparator 211. . The phase comparator 211 is CK
The phase of the synchronization signal corresponding to the clock mark detected by the mark detection circuit 117 and the phase of the frequency-divided signal by the frequency divider 213 are compared, and the phase difference signal corresponding to the phase difference between the two signals is VCO.
Send to 212. Therefore, the VCO 212 is controlled so that the synchronization signal from the CK mark detection circuit 117 and the signal divided by the frequency divider 213 are synchronized, for example, the phases of both signals match. For example, if the frequency division ratio of the frequency divider 213 is 1/200, the oscillation frequency of the VCO 212 is 200 times the clock mark frequency of the clock mark detector 117. The counting circuit 214 is VCO2
Twelve output signals are counted and reset by the output signal of the frequency divider 213. Since the signal of the clock mark detector 117 and the signal of the frequency divider 220 are synchronized, the count value of the counting circuit 230 corresponds to the time from the clock mark detected by the clock mark detector 117, that is, the recording medium. Represents the rotation angle of. The decoder 215 includes two bit comparators, one bit comparator detects that the count value of the counting circuit 214 exceeds a predetermined value, and the other bit comparators detect that the count value of the counting circuit 214 is less than or equal to the predetermined value. Detect that there is. Then, it is detected from the logical product of both bit comparators that the count value of the counting circuit 214 is in a predetermined range, that is, a period corresponding to the information area, and a high level signal is sent to the AND circuit 216 during this period. Therefore, AND
The clock signal sent from the circuit 216 to the address reading circuit 120 serves as a clock signal for reading addresses in the entire area of the recording medium. The decoders 217 and 218 are configured similarly to the decoder 215, detect the first and second tracking mark detection positions, and send the period signal of each tracking mark to the tracking error detector 115.

The PLLs 220 and 230 have the same configuration as the PLL 210, but the frequency dividers 223 and 233 are configured so that the frequency division ratio can be changed by the control circuit 121. Therefore, the VCOs 222 and 232 are controlled so that the synchronization signal from the CK mark detection circuit 117 and the signals from the frequency dividers 223 and 233 are synchronized.
The frequency of the output signals of 2 and 232 is the control circuit 12
It corresponds to the division ratio set at 1. The counting circuits 224 and 234 count the output signals of the VCOs 222 and 232, and are reset by the output signals of the frequency dividers 223 and 233, respectively. Decoders 225 and 235 are decoders 215
However, the comparison values of the two bit comparators in each decoder are the same as those in the control circuit 1.
It is configured to be changed at 21. That is, the decoders 225 and 235 are configured to output a predetermined period signal for data reading according to the comparison value of the bit comparator set by the control circuit 121.

An operation of continuously reading data over a plurality of zones in the above structure will be described.
The control circuit 121 uses the address reading circuit 12
The zone of the track where the light beam is located is determined based on the address read by 0, and the frequency division ratio of the frequency divider 223 is set so that the VCO 222 generates a timing clock having a frequency matching the zone. , The decoder 225 sets the comparison value of the bit comparator in the decoder 225 so as to output the gate period of the data recorded in the zone. Then, the control circuit 121 sends a high level signal to the AND circuit 241 to start reading data. AND circuit 22
The data read clock output from the data read circuit 6 is sent to the data read circuit 1 via the AND circuit 241 and the OR circuit 243.
23, the data reading circuit 123 reads the data only while the control circuit 121 sends a HIGH level signal to the AND circuit 241.

When data is continuously read, the zone is crossed during the reading. When reading data from the first zone to the second zone, the control circuit 121 detects that the zone boundary is approaching based on the address read by the address reading circuit 120, and the VCO 232 causes the second zone to approach. The frequency division ratio of the frequency divider 233 is set so as to generate a timing clock having a frequency suitable for the decoder 2 and the decoder 235 outputs the gate period of the data recorded in the second zone.
The comparison value of the bit comparator in 35 is set. Then, the control circuit 121 detects that the light beam on the recording medium has entered the second zone based on the address read by the address reading circuit 120, and starts reading the data of the second zone. , AND
The LOW level signal is sent to the circuit 241 and the AND circuit 2
A high level signal is sent to 42. AND circuit 236
The clock signal for reading the data of the second zone output from the second zone is sent to the data reading circuit 123 via the AND circuit 242 and the OR circuit 243. In the data reading circuit 123, the control circuit 121 sends the AND circuit 242 to HIGH. Data is read only while the level signal is being sent.

Further, when the data is read over the second zone to the third zone again, the control circuit 121 detects that the zone boundary is approaching based on the read address, similarly to the above. And then the VCO
The divider 222 sets the frequency division ratio of the frequency divider 223 so as to generate a timing clock having a frequency suitable for the third zone, and the decoder 225 outputs the gate period of the data recorded in the third zone. The comparison value of the bit comparator in the decoder 225 is set to. Then, the control circuit 121 detects that the light beam on the recording medium has entered the third zone based on the address read by the address reading circuit 120, and starts reading the data of the third zone. AND circuit 24
A HIGH level signal is sent to 1, and a LOW level signal is sent to the AND circuit 242. The clock signal for reading the data of the third zone, which is output from the AND circuit 226, is sent to the data reading circuit 123 via the AND circuit 241 and the OR circuit 243, and the control circuit 121 of the data reading circuit 123 is the AND circuit. Data is read only during the period when a HIGH level signal is being sent to 241. As a matter of course, the signals sent from the control circuit 121 to the AND circuits 241 and 242 do not simultaneously become HIGH level, and both are LOW.
When the level signal is sent, the data is not read.

Next, the basic operation of the timing clock generation circuit 119 will be described with reference to FIG. Figure 6
(A) is a diagram schematically showing an arrangement of marks (pits) on a recording medium, in which the first and second tracking marks are vertically displaced from the center line (dashed line). It forms a wobble mark. Figure 6 (b) shows I / V
FIG. 6C shows an output waveform of the converter 114, and a pulse output waveform of the binarized circuit 118 which is binarized. The time interval t between the clock mark and the first tracking mark is called a so-called unique distance, and the mark interval is arranged so that this interval t cannot appear in other portions. FIG. 6D shows a synchronization signal waveform of the CK mark detection circuit 117 corresponding to the clock mark. In the CK mark detection circuit 117, the clock mark position is detected by paying attention to the time t in FIG. The synchronizing signal is detected by differentiating the waveform of the mark part. Wave 6
6E is a pulse output waveform of the frequency divider 213, FIG. 6F is an output waveform of the VCO 212, waveform (g) is a period signal waveform of the decoder 217 corresponding to the position of the first tracking mark, and waveform (h). Is a period signal waveform of the decoder 218 corresponding to the position of the second tracking mark, and waveform (i) is an address reading period signal waveform of the decoder 215 for reading an address. The counting circuit 214 is reset by the pulse signal of the waveform (e) and counts the pulse signal of the waveform (f). Therefore, the count value of the counting circuit 214 becomes the value of the number described in the waveform (f). The decoders 217, 218, and 215 determine how many counts the count value of the counting circuit 214 opens the gate, and output the waveform (g), the waveform (h), and the waveform (i). Waveform (j) is an address read clock signal waveform output from the AND circuit 216. actually,
For example, 10 bytes of information can be recorded in the information area in zone 0, and the address information is also recorded with a mark of the same spatial frequency as this information, but in FIG.
It is illustrated that individual marks are recorded.
That is, the waveform (i) in FIG. 6 becomes high level at the trailing edge of the fifth pulse of the timing pulse in FIG. 6 (f) after the decoder 215 outputs the clock mark, and becomes low level at the trailing edge of the fifteenth clock. The AND circuit 216 outputs 10 pulses for the information area as shown in the waveform (j) by opening the gate at.

In this embodiment, the frequency of the timing clock for reading data is changed depending on the zone of the recording medium, and the frequency of the timing clock is set higher in the outer zones. FIG. 7 shows a timing clock for reading the data recorded in zone 0 and zone 3. As described above, the control circuit 121 selects either the PLL 220 or the PLL 230 as the data read timing clock, but as shown in FIG. 7, the data read timing clock frequency (VCO output) in the zone 3 is changed. Is higher than that in zone 0.

The structure of the tracking error detector 115 will be described with reference to FIG. The tracking error detector 115 detects the peak value of the first tracking mark shown in FIG. 6A and holds it.
10, a second peak detection circuit 820 that detects and holds the peak value of the second tracking mark, and a differential amplifier 817 that outputs a signal according to the difference between the outputs of both peak detection circuits 810 and 820. There is. The output signal of the I / V converter 114 is the first and second peak detection circuits 8
It is input to the switches 811 and 821 in 10, 820. Further, the gate signal for the first tracking mark sent from the timing clock generation circuit 119 is input to the first peak detection circuit 810, and the gate signal for the second tracking mark is the second peak detection circuit 820. Has been entered in.

The operation of the first peak detection circuit 810 will be briefly described. 811, 813 and 815 are switches, 814 is an inverting circuit for inverting the polarity of the input signal,
812 and 816 are amplifiers with high input impedance. When the gate period signal (HIGH level signal) for the first tracking mark is input from the timing clock generation circuit 119 to the gate signal input terminals of the switches 811, 815 and the inversion circuit 814, the switch 81
1, 815 are in a short circuit state, and the switch 813 is in an open state. The signal from the I / V converter 114 is stored in the capacitor C11 via the switch 811 and the diode D11.
The diode D11 has a higher I than the potential of the capacitor C11.
Since the output signal of the / V converter 114 is passed and the signal of low potential is not passed, the potential of the capacitor C11 is the highest in the gate period for the first tracking mark sent from the timing clock generation circuit 119. It becomes an electric potential. Then, the peak potential is held in the capacitor C12 via the amplifier 812, the switch 815, and the resistor R11. When the timing clock generation circuit 119 completes the first tracking mark gate period signal, that is, when it becomes a LOW level signal, the switches 811 and 8 are provided.
15 is open, and switch 813 is short-circuited. The charge accumulated in the capacitor C11 is transferred to the switch 81.
However, the potential of the capacitor C11 becomes zero, but since the switch 815 is opened, the peak potential accumulated in the capacitor C12 is held. Then, when the gate period signal for the first tracking mark is input again from the timing clock generation circuit 119, the peak signal of this period is accumulated in the capacitor C11, and the capacitor C11 via the amplifier 812, the switch 815, and the resistor R11. A new peak potential is held at C12. Since the first peak detection circuit 810 and the second peak detection circuit 820 have exactly the same configuration, the operation of the second peak detection circuit 820 is omitted. In this way, the peak potential is held in the capacitors C11 and C21, and the held peak signal is sent to the differential amplifier 817 via the amplifiers 816 and 826. The differential amplifier 817 outputs a tracking error signal according to the difference between the two peak signals, and sends this signal to the control circuit 116.

Next, a search for a desired track will be briefly described. When the address of a desired track is input to the control circuit 121, the control circuit 12
1 reads the address of the track where the light beam is located on the recording medium 101 from the address sent from the address reading circuit 120, and calculates the distance to the desired track. If the calculated distance exceeds the predetermined range, the tracking control is disabled as the sparse search operation, the transfer motor 103 is driven, and the transfer table 104 is moved in the radial direction of the recording medium 101 to obtain a desired track. When it reaches the vicinity of, the tracking control is operated again, and the address of the track where the light beam on the recording medium 101 is currently located is read from the address sent from the address reading circuit 120 and desired. Calculate the distance to the truck. When the calculated distance exceeds the predetermined range, the sparse search described above is performed again. When it is within the predetermined range, the actuator 112 is driven to perform the fine search by jumping track by track. After that, the address is read again, and if the read address matches the address of the desired track, the search is ended, and if it does not match, the above-described search operation is repeated to search for the desired track.

When searching for the desired track, the control circuit 121 reads the data corresponding to the zone corresponding to the desired address position immediately after the desired track is input or during the search operation. The timing clock generation circuit 119 is controlled so as to generate the timing clock for the clock. For example, assuming that the data is read by the timing clock of the PLL 220 before the search is started, the PLL 23
The frequency division ratio of the frequency divider 233 is set so that the timing clock for data reading corresponding to the zone corresponding to the desired address position of 0 is generated, and the comparison value of the bit comparator in the decoder 235 is set. . When the search is completed, a read gate signal is sent from the control circuit 121 to the timing clock generation circuit 119, and the data reading circuit 123 reads the data. Under the control of the control circuit 121, the timing clock generation circuit 119 outputs a timing clock having a frequency corresponding to a zone corresponding to a desired track position, but the pull-in time of the PLL 230 after the control circuit 121 instructs is at most 3 to. Since the access time is about 5 ms and the access time is usually 5 to 50 ms until the access is completed, the pull-in of the PLL 230 is completed and the timing clock frequency is stable until the access is completed. Can be read.

As described above, in this embodiment, the timing clock generating circuit for detecting the period of the servo area and reading the address is separated from the timing clock generating circuit for reading the data of zones 0 to 3. Has become. Therefore, the detection of the tracking error signal and the address reading, which are extremely basic and important for operating the device, can always be performed stably, so that the reliability of the device is improved and the zone can be always easily discriminated. The data can be continuously read even if the data is recorded in a plurality of zones.

Generally, the number of servo areas per rotation of the recording medium is about 1500 to 2000. For example, when the recording medium is rotated at 1800 rpm, CK
The sync signal from the mark detector 117 is at most several tens of kHz. Therefore, the PLL requires a pull-in time of about 3 to 5 ms to generate an accurate timing clock of a predetermined frequency. However, in this embodiment, two timing clock generation circuits for reading data are provided, and one of the timing clock generation circuits reads the data of the track where the light beam is currently located, and the zone is switched to the next zone before the zone is switched. Controls the other timing clock generation circuit to generate a timing clock with a suitable frequency, detects the zone switching, and switches to the timing clock of the other timing clock generation circuit to read the data. The continuous reading of data across the area can be done very smoothly.

In the above description of the embodiment, it is detected that the zone boundary is approaching based on the read address, the frequency division ratio of the frequency divider 223 or 233 is set, and the bit comparator in the decoder 225 or 235 is set. -Although the comparison value of the data is set, the timing of these settings is PL
It suffices to consider the pull-in time of L, and it should not be limited. For example, when the VCO 232 generates a timing clock having a frequency suitable for the second zone when entering the second zone from the first zone, the frequency divider 2
The frequency division ratio of 33 is set, and the comparison value of the bit comparator in the decoder 235 is set so that the decoder 235 outputs the gate period of the data recorded in the second zone. At this time, immediately, the VCO 222 sets the frequency division ratio of the frequency divider 223 so as to generate a timing clock having a frequency suitable for the third zone, and the decoder 225 sets the gate period of the data recorded in the third zone. The comparison value of the bit comparator in the decoder 225 may be set so as to output the signal and the apparatus may be on standby. Also,
It is also possible to set such that when the clock frequency of one timing clock generation circuit is set and the reading of data is started, the other timing clock generation circuit simultaneously generates a timing clock suitable for the next zone.

Although the case of the reproducing apparatus has been described in the first embodiment, the present invention can be applied to the recording apparatus. FIG. 9 shows a block diagram of the optical recording apparatus of the second embodiment. 9, constituent elements having the same functions as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

When recording a signal, which will be described in detail later,
The control circuit 901 searches for a desired track to be recorded, and controls the timing clock generation circuit 905 to generate a timing clock suitable for the zone where the desired track is located. Then, the control circuit 901 puts the random access memory (RAM) in the recording pulse generation circuit 902 into a storage state, and thereafter, the recording data from the outside is input to the modulation circuit 903. The modulation circuit 903 modulates the recording data, and sends the modulation data to the recording pulse generation circuit 902 together with the data storage clock in the RAM. The recording pulse generation circuit 902 stores the modulation data in the RAM, and when the storage of the predetermined data is completed, a storage completion signal is sent to the control circuit 90.
Send to 1. Then, the control circuit 901 puts the RAM of the recording pulse generation circuit 902 into the read mode and outputs the recording gate signal for recording the signal in the predetermined storage area on the recording medium to the timing clock generation circuit 90.
Send to 5. The timing clock generation circuit 905 sends to the recording pulse generation circuit 902 a clock signal suitable for the zone for recording data. The recording pulse generation circuit 902 sends a predetermined recording pulse according to the modulation data stored in the RAM to the drive circuit 904. The drive circuit 904 strongly modulates the light source 105 according to the recording pulse, and the recording medium 1
The signal is recorded in a predetermined recording area on 01.

The timing clock generation circuit 905 will be described with reference to FIG. 10, constituent elements having the same functions as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. The timing clock generation circuit 905 includes three timing clock generation means, that is, the PLLs 210 and 22.
0 and 230 are provided. The PLL 210 generates a timing clock for reading an address and detecting the position of a tracking mark.
20 and 230 generate timing clocks for recording data.

The operation of continuously recording data in the above configuration will be described. Control circuit 901
Searches the desired track for recording data, and sets the frequency division ratio of the frequency divider 223 so that the VCO 222 generates a timing clock having a frequency that matches the zone of the desired track, and the decoder 225 sets the zone. The comparison value of the bit comparator in the decoder 225 is set so that the gate period of the data to be recorded in is output.
Then, the control circuit 901 sends a high-level recording gate signal to the AND circuit 1001 in order to start recording data. The clock signal for data recording output from the AND circuit 226 is the AND circuit 1001, OR
Data is recorded by being sent to the recording pulse generation circuit 902 via the circuit 1003.

When data is continuously recorded, the zone is crossed. When data is recorded from the first zone to the second zone, the control circuit 901 detects that the zone boundary is approaching based on the address read by the address reading circuit 120, and the VCO 232.
Sets the frequency division ratio of the frequency divider 233 so as to generate a timing clock having a frequency suitable for the second zone, and the decoder 235 outputs the gate period of the data to be recorded in the second zone. Set the comparison value of the bit comparator. And the control circuit 9
01 detects that the light beam on the recording medium has entered the second zone based on the address read by the address reading circuit 120, and starts the recording of data in the second zone. To the AND circuit 1002, and a HIGH level signal to the AND circuit 1002. The clock signal for recording data in the second zone output from the AND circuit 236 is AND
Data is transmitted to the recording pulse generation circuit 902 via the circuit 1002 and the OR circuit 1003 to record data. Further, when recording data over the second zone to the third zone again, the control circuit 901 detects that the zone boundary is approaching based on the read address, as described above. The frequency division ratio of the frequency divider 223 is set so that the VCO 222 generates a timing clock having a frequency that matches the third zone, and the decoder 225
Set the comparison value of the bit comparator. And
Based on the address read by the address reading circuit 120, it is detected that the light beam on the recording medium has entered the third zone, and the AND circuit 1001 is set to the high level in order to start reading the data of the third zone. And a LOW level signal is sent to the AND circuit 1002. A clock signal for recording data in the third zone, which is output from the AND circuit 226, is sent to the recording pulse generation circuit 902 via the AND circuit 1001 and the OR circuit 1003 to record data.

Recording pulse generation circuit 902 is shown in FIG.
Will be explained. FIG. 11 shows a recording pulse generation circuit 902.
It is a block diagram of. Explaining the relationship between FIG. 9 and FIG. 11, the modulation signal from the modulation circuit 903 is on the line (a),
The data storage clock signal is input to the line (a). Also, sent from the control circuit 901,
The R / W signal for switching the RAM 1101 of the recording pulse generation circuit 902 between the storage mode and the reproduction mode has a line (d) with a clock for storing data in the RAM 1101 and a timing clock for reading data from the RAM 1101. A clock switching signal for switching is input to the line (f). Recording pulse generation circuit 9
From 02, the storage completion signal indicating that the predetermined modulation data is stored in the RAM 1101 is transmitted from the line (e). The recording gate signal sent from the control circuit 901 to the timing clock generation circuit 905 is also input to the line (K). In addition, the timing clock generation circuit 9
The clock signal for data recording from 05 is line (K)
The recording pulse signal input to the drive circuit 904 for driving the light source is transmitted from the line (c).

When recording the signal on the recording medium 101, the control circuit 901 sets the RAM 1101 to the storage mode by the line (d), and the CK switching circuit 1
102 is switched by a line (f) so that the data storage clock signal from the modulation circuit 903 is input to the counting circuit 1103. After that, the modulation data and the data storage clock signal are sent from the modulation circuit 903 to the recording pulse generation circuit 902. The counting circuit 1103 counts the clock signal for data storage every moment, and the count value is stored in the RAM.
1101 and the comparison circuit 1104 are sequentially sent. RAM1
Reference numeral 101 designates the modulation circuit 9 using the count value of the counting circuit as an address.
The modulation data sent from the device 03 is stored. The comparator circuit 1104 detects that the count value of the counter circuit 1103 has reached a predetermined value, and transmits a storage completion signal indicating that predetermined modulation data is stored in the RAM 1101 from the line (e) to the control circuit 901. . When the storage completion signal is input from the comparison circuit 1104, the control circuit 901 sets the RAM 1101 to the read mode by the line (D), and at the same time the clock signal of the gate circuit 1106 is transmitted to the counting circuit 1103. ), The CK switching circuit 1102 is switched.
Then, the control circuit 901 searches a predetermined recording area on the recording medium 101 where the data stored in the RAM 1101 should be stored, and outputs a recording gate signal for starting recording to the timing clock generation circuit 90 in FIG.
5 and the line (K) to the gate circuit 1105. Timing clock generation circuit 905 is line
A clock signal having a frequency suitable for the zone in which the data is recorded is sent by the clock signal.
It is inverted in 6 and sent to the gate circuit 1105. At the same time as the recording gate signal, an inverted clock signal is output from the gate circuit 1105, and this clock signal is sent to the recording pulse generation circuit 1107 and also input to the counting circuit 1103 via the CK switching circuit 1102. The counting circuit 1103 counts the gated and inverted clock signal from the gate circuit 1105 and stores the counted value in the RAM.
1101 and the comparison circuit 1104. The recording pulse generation circuit 1107 generates a recording clock signal having a predetermined pulse width from the inverted clock signal from the gate circuit 1105, and sends this signal to the gate circuit 1108.
On the other hand, the RAM 1101 sequentially outputs the data stored in the address corresponding to the count value of the counting circuit to the gate circuit 110.
Send to 8. The gate circuit 1108 creates a recording data pulse signal corresponding to the logical product of the data signal sent from the RAM 1101 and the recording clock pulse signal, and sends the recording data pulse signal to the drive circuit 904 by line (c). Drive circuit 90
Reference numeral 4 strongly modulates the light source according to the recording data pulse signal from the gate circuit 1108 to record the data on the recording medium. The comparator circuit 1104 detects that the count value of the counter circuit 1103 has reached a predetermined value, and transmits a recording completion signal indicating that the recording of the data stored in the RAM 1101 is completed from the line (e) to the control circuit 901. To do. When the recording completion signal is input from the comparison circuit 1104, the control circuit 901 sets the recording gate signal input to the timing clock generation circuit 905 and the line (X) to LOW level to end the recording. Then, in the case of continuously recording data, the above-mentioned operation is alternately repeated.

The operation of recording data on the recording medium 101 will be described with reference to the timing chart of FIG. FIG. 12 shows the waveform of each part in a desired data area for recording data. FIG. 12 (a) shows a schematic diagram of pits on a recording medium, and FIG. 12 (b) shows CK.
The sync signal waveform output from the mark detection circuit 117 is shown. FIG. 12C shows the VCO output waveform, which is the output waveform of either the VCO 222 or VCO 232 in the PLL 220 or PLL 230 selected by the control circuit 901. FIG. 12D shows the output waveform of the decoder, which is the output waveform of either the decoder 225 or the decoder 235 selected by the control circuit 901. FIG. 12E shows the output waveform of the OR circuit 1003, and the waveform (f) is from the control circuit 901 to the timing generation circuit 905 and the gate circuit 1105.
12 (g) shows the waveform of the recording gate signal input to FIG.
Shows the output waveform of the gate circuit 1105. The control circuit 901 outputs the recording gate signal as shown in FIG.
A signal for the same period as the decoder output shown in (d) is continuously generated for each data area in which data is recorded. 12
(H) shows the gate circuit 1 from the recording pulse generating circuit 1107.
The waveform of the recording clock signal input to 108 is shown, and as shown in the figure, it is a pulse having a predetermined time width delayed by Δt from the rising edge of the output pulse of the gate circuit 1105. FIG. 12I shows the gate circuit 1 from the RAM 1101.
FIG. 12 shows a recording data waveform input to 108.
(J) shows a data recording pulse waveform sent from the gate circuit 1108 to the drive circuit 904.

In FIG. 1 which is the first embodiment, a timing clock generation circuit 119 is used for reading an address and a PLL 210 for detecting a position of a tracking mark and for reading data recorded in a data area on a recording medium. It has two PLLs 220 and 230,
The PLL 210 can also be used for reading data. Regarding the third embodiment configured in this way,
This will be described with reference to FIGS. 13 and 1
4, components having the same functions as those in FIGS. 1 and 2 are designated by the same reference numerals, and the description thereof will be omitted. The timing clock generation circuit 1302 is recorded in the PLL 210 for reading an address, detecting the position of the tracking mark, and reading the data recorded in the data area of the zone 0, and the data area on the recording medium of the zones 1 to 3. PLLs 220 and 230 for reading data are provided.

When the data is recorded in the zone 0 and the data is read, the control circuit 1301 outputs HIGH to the AND circuit 1401 only during the data read period.
Send a level signal. As a matter of course, at this time, the control circuit 1301 has the AND circuits 1402 and 1
It sends a LOW level signal to 403. Therefore, the data read clock signal for the zone 0 of the AND circuit 216 is the AND circuit 1401 and the OR circuit 140.
4 to the data reading circuit 123. Further continuous reading of data crosses the zone. When reading data from zone 0 to zone 1, the control circuit 1301 detects that the zone boundaries are approaching based on the address read by the address reading circuit 120, and the VCO 222 causes the zone 1 to read.
The frequency division ratio of the frequency divider 223 is set so as to generate a timing clock having a frequency that conforms to, and the bit comparator in the decoder 225 outputs the gate period of the data recorded in the zone 1. Set the comparison value of the data. Then, the control circuit 1301 detects that the light beam on the recording medium has entered the zone 1 on the basis of the address read by the address reading circuit 120, and in order to start reading the data of the zone 1, the AND circuit 1401. A low level signal is sent to 1403, and a HIGH level signal is sent to the AND circuit 1402. The clock signal for reading the zone 1 data output from the AND circuit 226 is the AND circuit 14
02, the data reading circuit 1 through the OR circuit 1404
Sent to 23.

When the data is read again from the zone 1 to the zone 2, the control circuit 1301 detects that the zone boundary is approaching based on the read address, and the VCO 232 detects that the zone boundary is approaching. The frequency division ratio of the frequency divider 233 is set so as to generate a timing clock having a frequency suitable for the zone 2.
The comparison value of the bit comparator in the decoder 235 is set so that 35 outputs the gate period of the data recorded in the zone 2. Then, the control circuit 130
1 detects that the light beam on the recording medium has entered the zone 2 on the basis of the address read by the address reading circuit 120, and the AND circuit 1403 is set to the HIGH level in order to start the reading of the data of the zone 2. A signal is sent, and a LOW level signal is sent to the AND circuits 1401 and 1402. The clock signal for reading the zone 2 data output from the AND circuit 236 is AND
It is sent to the data reading circuit 123 through the circuit 1403 and the OR circuit 1404.

Further, when reading data from zone 2 to zone 3, control circuit 1301
Detects that the zone boundary is approaching based on the address read by the address reading circuit 120,
The frequency division ratio of the frequency divider 223 is set so that the O222 generates a timing clock having a frequency suitable for zone 3.
The comparison value of the bit comparator in the decoder 225 is set so that the decoder 225 outputs the gate period of the data recorded in the zone 3. Then, the control circuit 1301 detects that the light beam on the recording medium has entered the zone 3 based on the address read by the address reading circuit 120, and starts the reading of the data of the zone 3 in order to start reading the data of the zone 3. 1403
LOW level signal to the AND circuit 1402
Send an IGH level signal. The clock signal for reading the data of zone 3 output from the AND circuit 226 is sent to the data reading circuit 123 via the AND circuit 1402 and the OR circuit 1404. As a matter of course, the control circuit 1301 has the AND circuit 140
The data reading circuit 123 reads the data recorded in the data area on the recording medium only during the period in which the HIGH level signal is sent to 1, 1402 or 1403.

The search for the desired track will be briefly described. When the address of the desired track is input to the control circuit 1301, the control circuit 1301 is input.
1 determines the zone to which the desired track belongs from the address sent from the address reading circuit 120, and if the zone is 0, the AND circuit 14 after the access is completed.
A high level signal is sent to 01. When the desired track belongs to zones 1 to 3, the control circuit 1301 corresponds to the zone corresponding to the desired address position immediately after the desired track is input or while the search operation is being performed. The timing clock generation circuit 1302 is controlled so as to generate a timing clock for reading data. For example, assuming that the data is read by the timing clock of the PLL 220 before the search is started, the frequency division is performed so that the PLL 230 generates the timing clock for data reading corresponding to the zone corresponding to the desired address position. The frequency division ratio of the converter 233 is set, and the comparison value of the bit comparator in the decoder 235 is set. When the search is completed, a read gate signal is sent from the control circuit 1301 to the timing clock generation circuit 1302, and the data reading circuit 123 reads the data.

As described above, in the third embodiment, the timing clock generation circuit generates a timing clock for detecting the servo area and reading the address, and a timing clock for reading the data recorded in the zone 0. Is generated by the PLL 210,
The frequency range of the timing clocks of the PLL 220 and the PLL 230 can be narrowed, and a more accurate timing clock can be generated.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to the embodiments. For example, in the present invention, the track is not limited to the spiral shape, but may be the concentric shape. Although the number of zones has been described as 4, the number may be increased or decreased as necessary.
Further, the positional relationship between the clock mark and the tracking mark need not be limited to the embodiment. Further, it is not always necessary to provide one address area in one sector, and if there is at least one address area in one track, the necessary sectors can be reached by counting the number of data areas.

Further, generally, the interval between the clock mark and the first tracking mark or the interval between the first and second tracking marks is set to an integral multiple of the shortest address mark interval and arranged so that the timing clock can also be used. Has been done. However, the interval between the clock mark and the first tracking mark is set so that the reproduced signal of the clock mark does not cause intersymbol interference, and the interval between the first and second tracking marks is also an interval at which the track deviation can be accurately detected. The density can be increased by setting the minimum interval satisfying this condition, and it is not necessarily required to be an integral multiple of the shortest address mark interval. In this case, if the timing clock for address reading is also used, the frequency becomes high, and the circuit becomes complicated and expensive. Therefore, the timing clock for position detection of the tracking mark and the timing clock for address reading may be separately provided.

[0056]

As described above, the optical recording / reproducing apparatus of the present invention reproduces the synchronizing signal from the clock mark of the recording medium, and based on the synchronizing signal, one or more kinds of frequencies suitable for the recording zone. Two timing clock generating means for generating the timing clock are provided, and one timing is used to generate a timing clock for recording data on the track where the light beam is currently located or for reading the recorded data. Since the clock generating means is controlled and the other timing clock generating means is controlled so as to generate a timing clock having a frequency suitable for the zone of the next track to be moved, the recording medium is divided into a plurality of zones. Can continuously record or reproduce data.

Further, the optical recording / reproducing apparatus of the present invention reproduces the synchronizing signal from the clock mark of the recording medium, and based on this synchronizing signal, at least the servo area is detected, the address is read, and if necessary, a specific recording zone A first timing clock generating means for generating a timing clock of a first frequency to meet the above requirement, and one or more kinds of timing clocks that match the desired recording zone of the recording medium according to the instruction of the control means based on the synchronization signal. By having the second and third timing clock generating means for generating the timing clock of the frequency, the timing clock adapted to the desired zone can be adjusted to the second or third timing until the desired track of the desired zone is accessed. It is generated and stabilized by the clock generation means, and when accessed, it immediately Since it is possible to switch to a timing clock suitable for the zone, there is no problem that signal reproduction or recording cannot be performed during this period due to the pull-in time due to timing clock switching, and signal reproduction or recording can be performed immediately. Since the frequency can be lowered, an effective effect that the circuit can be made simple and inexpensive can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of an optical reproducing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of the same timing clock generation circuit.

FIG. 3 is a schematic diagram of an arrangement state of recording data on the recording medium.

FIG. 4 is an explanatory diagram of a data recording status when each recording zone is reproduced.

FIG. 5 is an explanatory diagram of an address area in the recording area on the recording medium.

FIG. 6 is a schematic diagram of data on the recording medium and an operation waveform diagram of each part of the circuit.

FIG. 7 is a schematic diagram of data on a recording medium in a plurality of zones and an operation waveform diagram of each part of the circuit.

FIG. 8 is a block diagram of a tracking error detector.

FIG. 9 is a block diagram of an optical recording device according to a second embodiment of the present invention.

FIG. 10 is a block diagram of the timing clock generation circuit of the same.

FIG. 11 is a block diagram of the recording pulse generation circuit of the same.

FIG. 12 is a schematic diagram of data on the recording medium and an operation waveform diagram of each part of the circuit.

FIG. 13 is a block diagram of an optical reproducing device according to a third embodiment of the present invention.

FIG. 14 is a block diagram of the timing clock generation circuit of the same.

FIG. 15 is a recording area layout diagram of a recording medium common to a conventional example and an example of the present invention.

[Explanation of symbols]

 101 recording medium 111 photodetector 114 I / V converter 115 tracking error detector 117 CK mark detection circuit 118 binarization circuit 119 timing clock generation circuit 120 address reading circuit 121 control circuit 123 data reading circuit 210, 220, 230 PLL 211, 221, 231 Phase comparator 212, 222, 232 VCO 213, 223, 233 Frequency divider 214, 224, 234 Counting circuit 215, 217, 218, 225, 235 Decoder 216, 226, 236, 241, 242 AND circuit 243 OR circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Yamada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (6)

[Claims] 1. A plurality of synchronizing clock marks are provided per spiral on a spiral or concentric track rotated at a constant angular velocity, and the clock mark is centered on a locus connecting it with that of an adjacent track. The information area radially arranged with respect to each other and divided into at least two zones in the radial direction stores information such that the amount of information per circle is larger in the outer zone than in the inner zone. A device for irradiating a light beam on a storable recording medium to record information or reproducing the recorded information, and a conversion means for converting the information recorded on the recording medium into an electric signal, Sync signal detecting means for detecting a sync signal corresponding to the clock mark from the signal of the converting means, and recording information on a recording medium or reading recorded information To this end, two timing clock generating means capable of respectively generating timing clocks having one or more kinds of frequencies synchronized with the synchronizing signal, and the current light beam is positioned at one of the two timing clock generating means. A timing clock having a frequency suitable for the zone of the track being moved, and a timing clock having a frequency suitable for the zone of the next track to be transferred to another one of the two timing clock generating means. An optical recording / reproducing apparatus comprising a control means for instructing to perform. 2. A clock mark for synchronization and at least one address per circle for identifying a position are provided on a spiral or concentric circular track rotated at a constant angular velocity, and the clock marks are adjacent to each other. The track connecting to the clock mark of the track is arranged so as to be radial with respect to the center, and the address is recorded in all tracks so as to be reproduced in synchronization with the clock mark and at the same timing clock. The information area divided into at least two zones in the direction is irradiated with a light beam on a recording medium capable of accumulating information such that the amount of information per circle is larger in the outer zone than in the inner zone. A device for recording information or reproducing recorded information by converting the information recorded on a recording medium into an electrical signal. Converting means for converting; a synchronizing signal detecting means for detecting a synchronizing signal corresponding to the clock mark from the signal of the converting means; and a timing clock having a first frequency based on the synchronizing signal detected by the synchronizing signal detecting means. And an address reading circuit for reading the address recorded on the recording medium by determining the signal of the converting means based on the timing clock from the first timing clock generating means. And second and third timing clocks capable of generating timing clocks of one or a plurality of frequencies synchronized with the synchronizing signal for recording information on a recording medium or reading recorded information Generating means and a recording medium based on the address read by the address reading circuit. The zone in which the upper light beam is located is determined, and a timing clock having a frequency matching the zone of the track in which the current light beam is located is generated in one of the second or third timing clock generating means. At the same time, an optical recording / reproducing device is provided with a control means for instructing the other of the second or third timing clock generating means to generate a timing clock having a frequency suitable for the zone of the track to be transferred next. apparatus. 3. The control means, when searching for a desired track based on the address read by the address reading circuit, determines which recording zone the desired track is and matches the zone of the desired track. 3. The optical recording / reproducing apparatus according to claim 2, wherein either the second or third timing clock generating means is instructed to generate a timing clock of a frequency. 4. A clock mark for synchronization and at least one address per circle for identifying a position are provided on a spiral or concentric track rotated at a constant angular velocity, and the clock marks are adjacent to each other. The track connecting to the clock mark of the track is arranged so as to be radial with respect to the center, and the address is recorded in all tracks so as to be reproduced in synchronization with the clock mark and at the same timing clock. The information area divided into at least two zones in the direction is irradiated with a light beam on a recording medium capable of accumulating information such that the amount of information per circle is larger in the outer zone than in the inner zone. A device for recording information or reproducing recorded information by converting the information recorded on a recording medium into an electrical signal. Converting means for converting, synchronizing signal detecting means for detecting a synchronizing signal corresponding to the clock mark from the signal of the converting means, and a specific zone on a recording medium based on the synchronizing signal detected by the synchronizing signal detecting means Based on the timing clock from the first timing clock generating means for generating a timing clock of a first frequency for recording information on or reading the recorded information; An address reading circuit for reading the address recorded on the recording medium by judging the signal of the converting means, and recording information on the recording medium, or synchronizing with the synchronizing signal for reading the recorded information Second and third timings capable of generating timing clocks of one or more frequencies, respectively The zone in which the light beam on the recording medium is located is determined based on the clock reading means and the address read by the address reading circuit. If the zone is the specific zone, the output of the first timing clock generating means is output. If it is another zone, one of the second or third timing clock generating means generates a timing clock having a frequency suitable for the zone of the track where the current light beam is located and selects it. An optical recording / reproducing apparatus comprising: 5. The control means, when searching for a desired track based on the address read by the address reading circuit, determines which recording zone the desired track belongs to, and controls the first timing clock generating means. 5. A decision as to whether to select an output or to instruct the second or third timing clock generating means to generate a timing clock of a frequency matching the zone of the desired track to determine it. Optical recording / reproducing device. 6. A recording medium is provided with a plurality of pairs of wobble marks corresponding to a clock mark for synchronization per one circumference, and a locus connecting the wobble marks of each adjacent track is radial with respect to the center. And the pair of wobble marks are arranged at equal distances from each other with respect to the center line of the track outward and inward, and are separated from each other in the track direction. A period signal generating means for generating a period signal corresponding to each position of the pair of wobble marks based on the timing clock of the timing clock generating means, and a pair of wobble marks for each of the pair of wobble marks based on the period signal of the period signal generating means. The peak detection means for detecting the peak value and the difference between the peak values of the pair of wobble marks by the peak detection means are described. Optical recording and reproducing apparatus according to any one of the light beam on the medium is claims 1 and a tracking control means for controlling so as to be positioned on the track center line 5.