JP3385101B2 - Reference clock generation device and disk device for sample servo type disk device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference clock signal generating apparatus for generating a reference clock signal for recording information on a disc of sample format type or reproducing the recorded information.

[0002]

2. Description of the Related Art A sample servo type optical disk will be described with reference to FIG. In FIG. 33, 1001
Is a substrate of an optical disc, which is formed of a resin such as polycarbonate having a thickness of 1.2 mm, and has a clock mark (also referred to as a clock pit) 100 on one surface.
5, wobble marks (also referred to as tracking marks or tracking pits), a first wobble mark 1006, and a second wobble mark 10
07 is formed by a method such as injection.
This clock mark 1005, wobble mark 1006
And 1007 are arranged at the intersections of the radial straight lines emanating from the center O of the recording medium substrate 1001 and the center lines of the spiral or concentric circular tracks indicated by the chain line 1004. A first wobble mark 1006 and a second wobble mark 1007 for tracking servo are provided at positions slightly deviated (for example, by 1/4 track pitch) on both sides of the track center line before and after the synchronization clock mark 1005. Has been. This clock mark 1
005 and wobble marks 1006 and 1007 form a servo area 1002. Then, each servo area 100
Between the two, information areas 1003 are also formed radially. The recording medium substrate 1001 is included in several information areas 1010 of the plurality of information areas 1003 on one track.
Radial straight lines 1013 and one-dot chain line 1 emanating from the center O of the
The mark 1011 is arranged at the intersection with the center line of the spiral or concentric track indicated by 004. Also,
A mark 1012 is formed at the intersection of a radial straight line 1014 emanating from the center O of the recording medium substrate 1001 and the center line of a spiral or concentric circular track indicated by a chain line 1004.
Are placed. The marks 1011 and 1012 are
Like the clock mark 1005, it is formed by a method such as injection. Further, a mark indicating a track address is formed in the information area 1010, and a mark indicating data is formed in the information area 1003 by a method such as injection. A reflecting film of aluminum or the like is formed on the surface thereof. Here, the angles of the straight line 1013 and the straight line 1014 are the same in all the information areas 1010. The angle is set to a value that is not the same as the angle formed by the radial straight lines formed by the marks in the address areas of the servo area 1002, the information area 1003, and the information area 1010. Therefore, when the disc is rotated at a constant rotation speed, there is no other time interval from the mark 1011 to the mark 1012. Generally, the time interval from the mark 1011 to the mark 1012 is called a unique distance. Hereinafter referred to as UD. Figure 3
4 schematically shows an arrangement of marks (pits) on the disc shown in FIG. 1006a to 10
06d indicates a first wobble mark, which is from 1005a to 1
005d indicates a clock mark, and 1007a to 10
07d indicates the second wobble mark. A mark indicating a track address is formed in the address area of the information area 1010, and a mark indicating data is formed in the information area 1003 (not shown). Further, all the marks are formed in synchronism with the positions where the intervals between the clock marks are equally divided by a predetermined value. Therefore, when the information is reproduced or recorded, the PLL is based on the clock mark signal obtained by detecting the clock mark.
A (phase locked loop) circuit generates a reference clock signal serving as a reference for reproducing or recording information. The reference clock signal is shown in waveform (b). Mark 1 as described above
The period of the UD region from 011 to the mark 1012 is a period that does not occur in other regions. Therefore, this U
The D area is detected, and the clock marks 1005 arranged at predetermined intervals are extracted from the mark 1012. At the same time, P
The reference clock signal described above is generated based on the clock mark 1005 detected using the LL circuit. PLL
Before the operation of the circuit becomes stable, the clock marks 1005 arranged at a predetermined cycle with respect to the UD area are detected. After the operation of the PLL circuit is stabilized, a gate signal for clock mark detection is generated based on the reference clock signal generated by the PLL circuit, and the clock mark 1005 is detected. Further, a gate signal for detecting the first wobble mark 1006 and the second wobble mark 1007 is generated based on this reference clock signal. The gate signal is used to detect the difference in the amount of light reflected from the disk by the first wobble mark and the second wobble mark, and the deviation from the track center of the light beam is detected to perform tracking control.

[0003]

As described above, in the conventional optical disk device, if the number of UD areas in one track is reduced to further improve the recording density,
The number of gates for clock mark detection generated based on the UDs increases. Generally, the position of the clock mark fluctuates due to the eccentricity of the disk and the fluctuation of the rotation of the motor. Therefore, the gate for clock mark detection shifts from the clock mark position as time elapses from the time when the UD area is detected. However, in order for the PLL circuit to be in a steady state, several tens of clock marks must be accurately detected, so the PLL circuit cannot be brought into a stable state.

Further, in the conventional optical disk device, a pulse signal corresponding to a mark in a period in which a gate signal for clock mark detection is open is input to a PLL circuit to generate a reference clock signal. In this method, if a pseudo pulse is generated due to noise or the like during the period when the gate signal for detecting the clock mark is open, the PLL circuit operates based on the pseudo pulse. As a result, the PLL circuit outputs a signal different from the reference clock signal. Since the gate signal for detecting the clock mark is generated based on the reference clock signal which is the output signal of the PLL circuit, the clock mark cannot be detected. As a result, the output signal of the PLL circuit further deviates from the reference clock signal.

Further, since the gate signal for detecting the wobble mark also shifts, the deviation of the light beam from the track center cannot be detected. Therefore, the tracking control also becomes unstable.

An object of the present invention is to support a high-density disk in which the number of UD areas of one track is reduced, and to shift to a state where a reference clock signal is stably generated in a short time. Method to provide a reference clock signal generator for a disk device.

[0007]

[0008]

In order to achieve this object, the reference clock signal generating device of the present invention is used for reproducing information.
Or a black mark obtained by detecting a clock mark during recording.
PLL (phase locked loo)
p) A standard that is used as a standard for reproducing or recording information by the circuit.
In a device for generating a clock signal, a first clock
A VCO that generates a signal and a first VCO that outputs the VCO.
Frequency dividing means for dividing by counting the clock signal, and
Detects the clock mark based on the count value of the frequency division means
Clock mark detecting means for generating a second clock signal.
Clock oscillating means to be formed and the clock mark detecting means
Disconnect the output signal of the stage and the output signal of the clock oscillator.
Switching means for switching and outputting, and the output of the switching means.
The phase of the force signal and the phase of the output signal of the frequency dividing means are compared to obtain the V
Phase comparison means for sending to the CO, and first output for the VCO
Detects unique distance based on the clock signal of
Unique distance detection means for
Predetermined mark based on the output signal of the distance detection circuit
And a reference mark detecting means for detecting
Means first outputs the signal of said clock oscillator means.
The VCO oscillation frequency as a reference
The frequency dividing means so that the frequency becomes equal to the frequency of the clock signal.
The frequency division ratio of the
Switch means when a unique distance is detected by
To output the signal of the clock mark detection means
The VCO oscillation frequency is the reference clock signal.
The frequency division ratio of the frequency dividing means is set to be equal to the frequency of
After the determination, the reference mark detection means sets the predetermined value.
Counting of the frequency dividing means at the timing when the mark is detected
Preset the value to the given value only once, like this,
Obtaining a desired reference clock from the VCO,
Reference clock signal of sample servo system disk device
No. generator .

[0009]

[0010]

In the reference clock generating device of the present invention, in the above-mentioned configuration, the frequency of the clock signal generated by the VCO is equal before and after detecting the unique distance, and is divided by a predetermined mark signal after detecting the unique distance. Since the count value of the container is preset, the PLL circuit stably and rapidly shifts to the state synchronized with the clock mark.

[0011]

That is, in the present invention, the unique distance is detected by using the output signal of the VCO in a state where the PLL circuit of the timing clock generating circuit is operated based on the output signal of the oscillator. When the unique distance is detected, the frequency division ratio of the frequency divider of the PLL circuit is switched, and the PLL is generated based on the clock mark signal (output of the AND gate).
Activate the circuit. The frequency division ratio is set so that the oscillation frequency of the VCO becomes constant before and after the switch switches from the output signal of the oscillator to the clock mark signal. Also,
The count value of the frequency divider is preset to zero by the first clock mark signal (output of the AND gate) after detecting the unique distance, and subsequent detection of the clock mark is performed based on the count value of the frequency divider.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 33 is a diagram showing an optical disc for explaining the outline of the present invention. Note that FIG. 33 is used in the description of the reference clock signal generation device of the conventional example.

The marks are formed in synchronization with the clock marks 1005 and the positions where the intervals between the clock marks 1005 are equally divided by a predetermined value. Therefore, when reproducing or recording information, a reference clock signal is generated by a PLL (phase locked loop) circuit using the clock mark signal obtained by detecting the clock mark as a reference, and the information is recorded based on the reference clock signal. Play or record. Hereinafter, a state in which the reference clock signal is generated will be referred to as an operation mode. Here, the basic configuration of the PLL circuit will be briefly described.

The PLL circuit is a V which generates a clock signal.
CO, a frequency divider that divides the clock signal and outputs a divided pulse, a phase comparator that compares the phases of the clock mark signal and the divided pulse, and a VCO based on the output of the phase comparator.
It is composed of a loop filter that generates the control signal of.
The frequency divider counts the clock signals output by the VCO,
When the predetermined number of clocks is counted, the count value is cleared and counting is started again. The frequency divider repeats this operation. The frequency divider outputs a frequency division pulse when the count value is zero and sends it to the phase comparator. Therefore, the VCO generates the reference clock signal by setting the frequency division ratio of the frequency divider to a predetermined value. The frequency divider is configured so that the count value becomes zero when it is cleared.

The operation of shifting to the operation mode will be described below.

The period of the UD region from the mark 1011 to the mark 1012 is a period which does not occur in other regions. Therefore, the mark 1012 is detected by detecting this UD area.
From this, clock marks 1005 arranged at a predetermined interval are detected. The detection of the UD area is performed based on this clock signal by generating a clock signal having the same frequency as the reference clock signal. Hereinafter, this clock signal is referred to as a UD detection clock signal. The clock signal for UD detection is P
It is generated by inputting a clock signal corresponding to the rotation speed of the disk in place of the clock mark signal to the phase comparator of the LL circuit, and setting the frequency division ratio of the frequency divider to a predetermined value 1 / N. Hereinafter, a state in which the UD detection clock signal is generated will be referred to as a standby mode.

When the UD area is detected in the standby mode, the division ratio is switched from 1 / N to 1 / M. still,
The division ratio 1 / M is a value at which the VCO generates the reference clock signal when the input of the phase ratio detector is the clock mark signal. Further, the input of the phase comparator is switched to the clock mark signal obtained by detecting the clock mark from the clock signal corresponding to the rotation speed of the disk. Then, the first clock mark after detecting the UD area is detected, and the count value of the frequency divider is cleared. Therefore, the divided pulse is output and the divided pulse is synchronized with the clock mark signal. Since the timing when the count value is zero is synchronized with the clock mark signal, the second and subsequent clock marks after detecting the UD area generate a gate signal for detection based on the count value of the frequency divider, and generate the gate signal. Can be detected using.
Therefore, it is possible to shift from the standby mode to the operation mode. Since the oscillation frequency of the VCO is almost constant even when the operation mode is changed from the standby mode,
Stable transition from standby mode to operating mode,
And it can be done at high speed.

An optical disk device using the reference clock generation device according to the first embodiment of the present invention will be described in detail below with reference to FIG. 1 which is a block diagram thereof. In FIG. 1, the disc 100 is attached to a rotary shaft 102 of a motor 101. Then, the motor 101 uses the oscillator 13
The motor control circuit 123 controls so that the motor rotates at a rotation speed according to the clock signal output by 0.

Inside the transfer table 104, for example, a light source 105 such as a semiconductor laser, a coupling lens 106, a polarization beam splitter 107, a quarter wave plate 108, a total reflection mirror 109, a photodetector 111 and an actuator. A fixed part 112 (not shown) is attached to the transfer table 10.
4 is configured to move in the radial direction of the disc 100 by a transfer motor 103 such as a linear motor.

An optical beam generated by a light source 105 such as a semiconductor laser arranged in the transfer table 104 is collimated by a coupling lens 106 and then polarized by a polarization beam splitter 107, 1/4. After passing through the wave plate 108, the total reflection mirror 1
09 by the focusing lens 110.
The recording surface of 0 is focused and irradiated. The reflected light reflected by the recording surface of the disc 100 passes through the focusing lens 110, is reflected by the total reflection mirror 109, and is reflected by the quarter-wave plate 10
After passing through 8, the light is reflected by the polarization beam splitter 107 and irradiated onto the photodetector 111. Focusing lens 110
Is attached to the movable part of the actuator 112. When a current is passed through the tracking coil 113, the focusing lens 110 is moved to the disk 10 by the electromagnetic force received from a permanent magnet (not shown) attached to the fixed portion.
It moves in the radial direction of 0, that is, across the tracks on the disk 100 (left and right in the figure). Further, a coil (not shown) for a focus is also attached to the movable portion of the actuator 112, and when a current is passed through this coil, a permanent magnet (not shown) attached to the fixed portion is used. The focusing lens 110 is configured to be movable in the direction perpendicular to the surface of the disc 100 by the electromagnetic force received by the coil. Then, the focusing lens 11
In 0, the focus is controlled so that the optical beam irradiated on the disc 100 is always in a predetermined focusing state. In the following description, it is assumed that the focus control is operating normally.

The light reflected from the disk 100 is received by the photodetector 111 and converted into an electric current. Since the amount of light reflected from the disc 100 changes depending on the presence / absence of a mark on the disc, the output value of the photodetector 111 changes depending on the presence / absence of a mark on the disc. Therefore, the output level of the I / V converter 114 that converts current into voltage indicates the presence or absence of a mark on the disc. The output of the I / V converter 114 is sent to the peak detection circuit 133 and the binarization circuit 134. The peak detection circuit 133 outputs a pulse indicating the center position of the mark on the disc. Further, the binarization circuit 134 converts the input signal into a high level or low level binarization at a predetermined level. The high level is configured to indicate a mark. Hereinafter, the output signal of the peak detection circuit 133 will be referred to as a peak detection signal. The pulse corresponding to the clock mark in the peak detection signal is the above-mentioned clock mark signal. Further, the output signal of the binarization circuit 134 is referred to as a binarized signal.

Here, the flow of the rough operation of the block diagram shown in FIG. 1 will be described. The control circuit 132 sends a command to the gate generation circuit 136 and the UD detection circuit 135 via the data line 150 so that the optical disk device enters the standby mode. The gate generation circuit 136 connects the terminal b and the terminal c of the switch 139 via the data line 151. Therefore, the output signal of the oscillator 130 is input to the terminal a of the timing clock generation circuit 119. The timing clock generation circuit 119 is the PL described above.
It has a built-in L (phase locked loop) circuit. The timing clock generation circuit 119 synchronizes with the clock input to the terminal a and generates a clock having a frequency N times or M times that frequency. 1 / N or 1 / M is PLL
This is the division ratio of the divider built into the circuit. The timing clock generation circuit 119 outputs the generated clock to the UD detection circuit 135 and the gate generation circuit 136 from the terminal d. The switching of the division ratio 1 / N or 1 / M is controlled by the level of the terminal c. In standby mode, select 1 / N. The frequency division ratio 1 / N is set in advance so that the frequency of the clock output from the terminal d becomes equal to the frequency of the reference clock signal.

In the standby mode, the control circuit 132 transmits the UD detection circuit 1 via the data line 150.
A command is sent to 35 and the gate generation circuit 136 so as to enter the operation mode.

When the UD detection circuit 135 receives a command to enter the operation mode, the timing clock generation circuit 119.
It is detected that the light beam spot has passed through the UD area based on the clock signal, the peak detection signal and the binarized signal output from the terminal d. UD detection circuit 135 is UD
When the area is detected, the gate generation circuit 136 switches the frequency division ratio of the timing clock generation circuit 119 from 1 / N to 1 / M. Here, the frequency division ratio 1 / M is preset to a value at which the PLL circuit generates a clock having a frequency equal to that of the reference clock signal when the clock mark signal is input to the terminal a. In addition, the gate generation circuit 136 generates a gate signal for detecting the first clock mark after detecting the UD area with reference to the timing when the UD detection circuit 135 detects the UD area. This gate signal is at terminal b
Is sent to the terminal a of the AND gate 140.

Since the peak detection signal is input to the terminal b of the AND gate 140, the output of the AND gate 140 becomes the first clock mark signal after detecting the UD area. This clock mark signal is sent to the terminal b of the timing clock generation circuit 119.

The timing clock generation circuit 119 clears the count value of the frequency divider of the PLL circuit when the first clock mark signal after detecting the UD area is sent to the terminal b. Therefore, the second and subsequent clock marks after detecting the UD area can be detected based on the count value of the frequency divider of the timing clock generation circuit 119. The gate signal for detecting the clock mark generated based on the count value is sent from the terminal e of the timing clock generation circuit 119 to the terminal a of the AND gate 138. AND
Since the peak detection signal is input to the terminal b of the gate 138, the output of the AND gate 138 becomes the clock mark signal.

The terminal c of the switch 139 is disconnected from the terminal b immediately before the first clock mark signal after detecting the UD area and is connected to the terminal a. Therefore, the clock mark signal after detecting the UD area is sent to the terminal a of the timing clock generation circuit 119. The frequency division ratio of the PLL circuit incorporated in the timing clock generation circuit 119 is 1
Since it is switched to / M, the reference clock signal is generated when the clock mark signal is input to the terminal a. Therefore, the transition to the operation mode is completed.

Next, the operation of the optical disk device shown in FIG. 1 will be described with reference to the waveform chart shown in FIG. The schematic diagram (a) is a diagram schematically showing the arrangement of marks on the disk shown in FIG. 33 of the conventional example. The waveform (b) is the I / V converter 114.
, The waveform (c) is the output signal of the peak detection circuit 133, the waveform (d) is the output signal of the binarization circuit 134, the waveform (e) is the output signal of the switch 139, and the waveform (f). Is the signal at the output terminal d of the timing clock generation circuit 119, the waveform (g) is the signal at the output terminal a of the control circuit 132, and the waveform (h) is the unique distance detection circuit 135 (hereinafter referred to as the UD detection circuit). , The waveform (i) is the signal at the output terminal b of the gate generation circuit 136, the waveform (j) is the signal at the output terminal a of the gate generation circuit 136, and the waveform (k) is the output signal of the AND gate 140. The waveform (l) is the timing clock generation circuit 1
19 shows the output signal of the terminal e, the waveform (m) shows the output signal of the terminal g of the timing clock generation circuit 119, and the waveform (n) shows the output signal of the terminal h of the timing clock generation circuit 119.

In the schematic diagram (a), the first and second wobble marks are arranged vertically displaced from the center line (dotted line). Here, it is assumed that a wobble mark, an address mark, and a mark for forming a UD area are formed at any of positions where the space between the clock mark and the black mark is equally divided into 22. Each position divided into 22 is changed from 0 bit to 21 bit, the clock mark is 0 bit,
It is assumed that the second wobble mark is 3 bits, the head mark of the UD area is 11 bits, the end mark of the UD area is 16 bits, and the first wobble mark is 19 bits. Further, it is assumed that 0 to 21 bits are one block and one track is composed of 1000 blocks. It should be noted that this clock synchronized with 0 to 21 bits becomes the reference clock signal when the disk is rotating at a predetermined rotation speed. It is assumed that data is recorded in the information area.

The interval of the UD area is a unique interval that does not occur in the data recorded in the information area, the address mark, the clock mark and the wobble mark which are formed in advance.

When the light beam spot moves on the disk of the schematic diagram (a), the output signal of the I / V converter 114 has a waveform (b). This output signal is sent to the binarization circuit 134 and the peak detection circuit 133. The binarization circuit 134 binarizes the input signal at a predetermined level and outputs the binarized signal shown in the waveform (d). Also, the peak detection circuit 1
33 outputs the peak detection signal shown in the waveform (c) in which the center position of the mark is detected. The signal at the output terminal a of the control circuit 132 is at the low level (shown by the waveform (g)) before the time t0. The standby mode is set before time t0. The gate generation circuit 136 outputs a low level signal to the terminal a when the signal at the output terminal a of the control circuit 132 is at low level.

The switch 139 is constructed so that the terminal a and the terminal c are connected when the control terminal d is at the high level, and the terminals b and c are connected when the control terminal d is at the low level. Therefore, in the standby mode, the terminal b and the terminal c are connected, and the output signal of the oscillator 130 is input to the terminal a of the timing clock generation circuit 119 (shown by the waveform (e)).

The PLL circuit built in the timing clock generation circuit 119 operates based on the output signal of the oscillator 130 corresponding to the rotation speed of the motor, and generates a clock signal having a frequency N times that of this output signal. As described above, the clock signal generated by the PLL circuit has the same frequency as the reference clock signal. That is, the UD detection clock is output from the terminal d of the timing clock generation circuit 119.

The output waveform of the terminal d of the timing clock generation circuit 119 is shown in waveform (f). U before time t1
This is a clock signal for D detection.

The UD detection circuit 135 is the control circuit 1
When the signal at the output terminal a of 32 becomes high level at time t0 (shown in waveform (g)), the operation of detecting the UD area is started based on the binarized signal and the peak detection signal.

The interval of the UD area is a unique interval which does not occur in the data recorded in the information area, the address mark, the clock mark and the wobble mark which are formed in advance. Therefore, the UD detection clock signal output from the terminal d of the timing clock generation circuit 119 measures the low level period of the binarized signal (shown in the waveform (d)) to detect the UD area. Since the measurement is performed using the UD detection clock having the same frequency as the reference clock signal, even when the frequency of the oscillator 130 is changed and the rotation speed of the motor 101 is changed, it is possible to cope with the change without changing the configuration.

The UD detection circuit 135 sets the UD area at time t1.
When it is detected, the output is switched to the high level (shown by the waveform (h)). When the waveform (h) becomes high level at time t1, the terminal c of the timing clock generation circuit 119 is set to high level, so that the frequency division ratio of the PLL circuit described above is switched to 1 / M.

The gate generation circuit 136 is the UD detection circuit 13
When the signal sent from 5 switches to the high level, the gate signal for detecting the first clock mark after the detected UD area is output to the terminal b (shown by the waveform (i)). The gate signal of waveform (i) is from time t1 to time s
It is a signal which becomes high level for a period of time s1 after 0 has elapsed. The gate signal is generated based on the UD detection clock signal.

A gate signal (shown by waveform (i)) for detecting the first clock mark after UD detection is input to the terminal a of the AND gate 140, and a peak detection signal is input to the terminal b. Therefore, the output of the AND gate 140 becomes the first clock mark signal immediately after detecting the UD area (shown by the waveform (k)). The count value of the frequency divider of the PLL circuit is cleared by the pulse shown in the waveform (k). Therefore, the divided pulse is almost synchronized with the clock mark signal. The operation of the frequency divider will be described later in detail.

The signal at the output terminal e of the timing clock generation circuit 119 is a gate signal for detecting a clock mark and is generated based on the count value of the frequency divider.

The count value of the frequency divider is cleared by the first clock mark signal (shown by the waveform (k)) immediately after detecting the UD area, and the frequency division pulse and the clock mark are synchronized. Therefore, it is possible to generate the gate signal for detecting the second and subsequent clock marks after detecting the UD area based on the count value of the frequency divider. Therefore, the output of the AND gate 138 becomes the clock mark signal (shown by the waveform (l)). Since the clock mark signal is input to the terminal a of the timing clock generation circuit 119, the timing clock generation circuit 119 stably generates the reference clock signal. The output of the terminal g of the timing clock generation circuit 119 is a gate signal for detecting the first wobble mark (shown by the waveform (m)). The output of the terminal h is a gate signal for detecting the second wobble mark (shown by the waveform (n)). The gate signals shown in the waveform (m) and the waveform (n) are generated based on the count value of the frequency divider, like the gate signal for detecting the clock mark. The tracking error detection circuit 115 detects the positional deviation between the light beam spot and the track based on the gate signal sent from the terminals g and h of the timing clock generation circuit 119 and the signal sent from the I / V converter 114. That is, the tracking error detector 115
Detects the peak value of the first and second wobble marks from the output signal of the I / V converter 114, and the signal indicating the positional deviation between the track on the disc 100 and the light beam spot, that is, the tracking, based on the difference between the peak values. Generate an error signal. Then, this tracking error signal is applied to the actuator 112 via the control circuit 116, and tracking control is performed so that the light beam spot on the disc 100 is located between the first and second wobble marks, that is, the center of the track. . Further, the tracking error signal is applied to the transfer motor 103 from the control circuit 116, and the transfer table 104 is transferred and controlled so that the focusing lens 110 moves in the radial direction of the disk around the natural state.

Each block will be described in detail below. First, the peak detection circuit 133 will be described. FIG. 3 shows a block diagram of the peak detection circuit 133.
Terminal 200 is connected to data line 146 of FIG. Further, the terminal 201 is connected to the data line 147 of FIG.

The capacitor 203 and the resistor 202 form a differentiating circuit 204. The signal input to the terminal 200 is differentiated by the differentiating circuit 204 and the comparator 205
Sent to the terminal. The comparator 205 outputs a high level signal when the signal level input to the terminal + is higher than the signal level input to the terminal −, and outputs a low level signal in the opposite case. The terminal + of the comparator 205 is set to zero level. The output of the comparator 205 is connected to the terminal 201. The operation will be described with reference to the waveforms shown in FIG. The vertical axis of each waveform represents the signal level, and the horizontal axis represents time. The operation when the signal of waveform (a) is input to the terminal 200 will be described. The peak of the waveform (a) indicates the center position of the mark. Waveform (b) shows the output of the differentiating circuit 204. The waveform has a zero cross at the peak position of the waveform (a). The waveform (b) is binarized by the comparator 205 and becomes the waveform (c). The rising edge of the waveform (c) indicates the peak position.

Next, the binarization circuit 134 will be described.
FIG. 5 shows a block diagram of the binarization circuit 134. Terminal 30
0 is connected to the data line 146 of FIG. Further, the terminal 301 is connected to the data line 153 of FIG.

The terminal 300 is the terminal of the comparator 302+
It is connected to the. The comparator 302 outputs a high level signal when the signal level input to the terminal + is higher than the signal level input to the terminal −, and outputs a low level signal in the opposite case. The power supply 303 sets the terminal-of the comparator to a predetermined level.

The operation will be described with reference to the waveforms shown in FIG. The vertical axis of each waveform represents the signal level, and the horizontal axis represents time. The operation when the signal of waveform (a) is input to the terminal 300 will be described. Waveform (b) shows the output waveform of the comparator 302. The level E of the waveform (a) indicates the level of the terminal − of the comparator 302 set by the power supply 303. The comparator 302 binarizes the signal (shown in the waveform (a)) input to the terminal + with reference to the level E,
The waveform is as shown in waveform (b). The high level period corresponds to the position of the mark on the disc.

Next, the UD detection circuit 135 will be described.
FIG. 7 shows a block diagram. The UD detection clock generated by the timing generation circuit 119 is input to the input terminal 400. The binarized signal output from the binarization circuit 134 is input to the input terminal 401, the peak detection signal output from the peak detection circuit 133 is input to the input terminal 402, and the signal output from the terminal a of the control circuit 132 is input to the terminal 416. Are input respectively. The terminal 405 is connected to the terminal c of the gate generation circuit 136 and the timing clock generation circuit 119 of FIG.

The UD detection clock is sent to the terminal CK of the counter 403. The counter 403 counts clocks input to the terminal CK while the terminal CLR is at low level. The comparator 404 compares the count value of the counter 403 with the value set in the data setting circuit 411, and outputs a high level signal when they are equal. Comparator 404
When the output of is high level, the output of the flip-flop 406 becomes high level. The output signal of the flip-flop 406 is connected to the terminal D of the flip-flop 407. The peak detection signal output from the peak detection circuit 133 is input to the terminal CK of the flip-flop 407. Therefore, the output of the flip-flop 407 is the terminal D
Becomes high level when a peak detection signal is input to the terminal CK in a high level state. Flip flop 40
The output of 7 is sent to terminal 405.

The operation will be described with reference to the waveforms in FIG.

The signal input to the terminal 416 has a waveform (g)
Since it has the waveform shown in, it becomes a high level at time t0.
Therefore, the output of the inverter 417 becomes low level and O
The output of the R gate becomes low level. Therefore, the counter 403 starts counting. U for the data setting circuit 411
A value slightly smaller than the count value when the period of the UD area is measured by the D detection clock signal (shown in waveform (f)) is set. Therefore, the output of the comparator 404 becomes high level before the mark indicating the end of the period of the UD area. Therefore, the output of the flip-flop 406 becomes high level. Immediately after that, the peak detection signal P0 shown in the waveform (c) corresponding to the mark at the end of the UD area is output to the terminal 40.
When input to 2, the flip-flop 407 outputs a high level (shown by the waveform (h)). Therefore, the UD area is detected.

Next, the operation of the gate generation circuit 136 will be described with reference to FIG. FIG. 8 shows a block diagram. U generated by the timing generation circuit 119 at the input terminal 500
A clock signal for D detection is input. Also, input terminal 5
01, the output signal of the UD detection circuit 135 is input terminal 50
The signal from the terminal a of the control circuit 132 is input to each of the eight. The terminal 504 is the gate generation circuit 136 of FIG.
The terminal b corresponds to the terminal b, and the terminal 505 corresponds to the terminal a.

The signal input to the terminal 501 is an inverter 502 which inverts and outputs the input signal, and an OR gate 51.
It is sent to the terminal CLR of the counter 503 via 0. The counter 503 counts the clocks input to the terminal CK while the terminal CLR is at the low level, and outputs the count value to the decoders 506 and 507. The decoder 506 outputs a high level when the count value is a predetermined value. The decoder 507 outputs a high level when the count value exceeds a predetermined value.

The operation will be described with reference to the waveforms in FIG. Since the signal input to the terminal 508 (shown in the waveform (g)) becomes high level at time t0, the output of the inverter 509 becomes low level after time t0. The signal input to the terminal 501 becomes high level at time t1 (shown by the waveform (h)). Therefore, the output of the inverter 502 becomes low level. Therefore, the output of the OR gate 510 becomes low level after the time t1. When the output of the OR gate 510 becomes low level at time t1, the counter 503 starts counting. The decoder 506 outputs a high level when the count value of the counter 509 reaches a value corresponding to the time s0 (shown in the waveform (i)), and outputs a low level after the time s1 has elapsed. The decoder 507 outputs a high level when the count value of the counter 503 reaches the value corresponding to the time s0 shown in the waveform (j).

Next, the operation of the timing clock generation circuit 119 will be described in detail. Here, it is assumed that the motor 101 is configured to rotate once when 100 clocks are input to the motor control circuit 123. Further, the oscillation frequency of the oscillator 130 is 4 kHz. Therefore, the motor 101 is 240
Rotate at 0 rpm. Further, the number of blocks per track of the disk 100 is 1000, and the number of clocks of the reference clock signal per block is 22. Therefore, the frequency of the reference clock signal is 880 kHz.
z.

FIG. 9 shows a timing clock generation circuit 119.
The block diagram of is shown. The terminal 600 corresponds to the terminal a of the timing clock generation circuit 119 shown in FIG.
01 is terminal b, terminal 602 is terminal e, terminal 603 is terminal g, terminal 604 is terminal h, and terminal 605 is terminal c.
In addition, the terminals 606 correspond to the terminals d, respectively.

The timing clock generation circuit 119 includes the PLL circuit 607 described above. PLL circuit 60
Reference numeral 7 generates a UD detection clock signal and a reference clock signal. Also, a gate signal for detecting the first and second wobble marks and a gate signal for detecting the clock marks are generated.

The PLL circuit 607 includes a phase comparator 608,
Loop filter 609, VCO (voltage controlled oc)
silator) 610 and frequency divider 611.

The frequency divider 611 counts the clock signals output from the VCO 610, and when counting the integer 1 / N or 1 / M clocks, the count value is cleared and the counting is started again. The frequency divider 611 repeats this operation. Frequency divider 611
Outputs a pulse when the count value is zero, and the data line 6
15 to the phase comparator 608. This pulse corresponds to the frequency division pulse described above. The switching between N and M is performed according to the level of the terminal 605. Further, the frequency divider 611 is configured such that when a pulse is input to the terminal 601, the internal state is cleared, that is, the count value becomes zero. The phase comparator 608 compares the phase of the divided pulse with the clock signal input to the terminal 600, and sends a phase difference signal corresponding to the phase difference between the two signals to the VCO 610 via the loop filter 609. Therefore, the VCO 610 is
Control is performed so that the phases of the clock signal input to the terminal 600 and the divided pulse signal match. Here, the frequency divider 6
The division ratio of 11 can be set to either 1/220 or 1/22. The frequency division ratio is 1/22 when the terminal 605 is at the high level, and the frequency division ratio is 1/220 when it is at the low level. The above-mentioned frequency division ratio N is 1/220 and the frequency division ratio M is 1/22.

First, the operation in which the timing clock generation circuit 119 generates the UD detection clock signal in the standby mode will be described.

In the standby mode, since a low level signal is input to the terminal d, the frequency division ratio is 1/220. Therefore, the oscillation frequency of the VCO 610 is 220 times that of the input signal. Here, the frequency of the clock signal input to the terminal 600 is 4 kHz which is the output of the oscillator 130 shown in FIG. Therefore, the oscillation frequency of the VCO 610 is 880 kHz, which is the same as the reference clock signal. V
The clock signal oscillated by the CO 610 is the UD detection clock signal.

The frequency of the oscillator 130 changes and the motor 10
Since the oscillation frequency of the VCO 610 also changes when the rotation speed of 1 changes, the oscillation frequency of the VCO 610 matches the frequency of the reference clock signal. Therefore, it is not necessary to change the configurations of the UD detection circuit 135 and the gate generation circuit 136 described above.

Next, the operation of the timing clock generation circuit 119 when shifting from the standby mode to the operation mode will be described with reference to the waveform diagram of FIG. Time t of waveform (h)
After 1 the terminal 605 is set to high level. Therefore, the frequency division ratio of the frequency divider 611 is M (M is 1/22). Therefore, the oscillation frequency of the VCO 610 is 22 times the frequency of the clock signal input to the terminal 600. After the time t2 shown in the waveform (j), the terminal 600
The signal input to is a clock mark signal. Since the frequency of the clock mark signal is 40 kHz, VCO6
The oscillation frequency of 10 is 880 kHz. Since it has the same frequency as the UD detection clock, the frequency divider 611 is generated at time t1.
Even if the frequency division ratio is switched, the oscillation frequency of the VCO 610 does not change.

When the first clock mark signal (pulse P1 of waveform (k)) after detecting the UD area is input to the terminal 601, the internal state of the frequency divider 611 is cleared,
The count value becomes zero. Since the count value becomes zero, the frequency divider 611
Outputs the divided pulse to the phase comparator 6 via the data line 615.
Send to 08. Further, the clock mark signal (pulse P1 of waveform (k)) is ORed to the terminal 600 at almost the same timing.
It is input via the gate 154 and the switch 139. Therefore, the oscillation frequency of the VCO 610 hardly changes.

Since the count value of the frequency divider 611 becomes zero at the first clock mark signal after detecting the UD area, the timing when the clock mark on the disk and the count value of the frequency divider 611 are zero are substantially synchronized. . Therefore, the count value corresponds to the time from the clock mark on the disk, that is, the rotation angle of the disk. The decoder 612 includes two bit comparators, and one bit comparator detects that the count value exceeds a predetermined value, and the other bit comparators detect that the count value is less than or equal to the predetermined value. Then, the decoder 612 generates a gate signal indicating a predetermined value range, that is, a clock mark area, from the logical product of both bit comparators. The clock mark is detected based on the generated gate signal indicating the area of the clock mark and input to the phase comparator 608. Therefore, the reference clock signal is constantly generated. Similarly, the decoder 61
Reference numerals 3 and 614 generate gate signals indicating the areas of the first and second wobble marks.

Next, the configuration of the frequency divider 611 will be described in detail.

FIG. 10 shows a block diagram of the frequency divider 611. The terminal 700 is the terminal a of the frequency divider 611 of FIG. 11, the terminal 701 is the terminal c, the terminal 705 is the terminal b, and the terminal 70.
7 corresponds to terminals d, respectively. The terminals 702a to 702h are connected to the data bus line 616 in FIG. The counter 703 is an 8-bit counter generally called a synchronous counter, in which the counting operation is performed in synchronization with the rising edge of the clock input to the terminal CK. Q0 to Q7 indicate count values. Q0 indicates the lower bit and Q7 indicates the upper bit. When the rising edge is input to the terminal CK when the terminal CLR2 is at the high level, the count value is cleared, and when the terminal CLR1 is set to the high level, the count value is cleared regardless of the input signal input to the terminal CK. It The clock input to the terminal 700 is input to the terminal CK of the counter 703. The count value of the counter 703 is the terminal 702, the comparator 704,
Input to 706 and 708. The comparator 706 outputs a high level when the input value is 21. The comparator 704 outputs a high level when the input value is 219. The comparator 708 outputs a high level when the input value is zero. The output of the comparator 708 is the divided pulse.
The switch 709 connects the terminal b and the terminal c when the terminal d is low level, and connects the terminal a and the terminal c when the terminal d is high level.

The operation of the frequency divider 611 will be described with reference to the waveform chart of FIG. First, the operation in the standby mode will be described. The signal shown in the waveform (h) is input to the terminal 707. Before the time t1 of the waveform (h), the level is low. The standby mode is before time t1. In the standby mode, the signal from the comparator 704 is input to the terminal CLR2 of the counter 703 via the switch 709. Therefore, the count values Q0 to Q7 of the counter 703 repeat 0 to 219 according to the clock input to the terminal CK. Since the comparator 708 is configured to output a high level when the input value is zero, the output of the comparator 708 is the clock input to the terminal 700 divided by 220. That is, the terminal 6 of FIG.
When a clock of 4 kHz which is the output signal of the oscillator 130 is input to 00, the oscillation frequency of the VCO 610 of the PLL circuit 607 is 880 kHz which is the frequency of the UD detection clock.
It becomes Hz.

Next, the operation when shifting from the standby mode to the operation mode will be described. When the UD area is detected, the level of the terminal 707 becomes high level (shown by the waveform (h)). Therefore, the signal of the comparator 706 is input to the terminal CLR2 of the counter 703 via the switch 709. Therefore, the count value Q0 to Q of the counter 703
7 is 0 to 2 depending on the clock input to the terminal CK.
Repeat 1. Therefore, the output of the comparator 708 is
The clock input to the terminal 700 is divided by 22. Immediately after the switch 709 is switched, the terminal 710 is
When the pulse P1 having the waveform (k) which is the clock mark signal is input to the counter, the count value of the counter 703 is forcibly cleared. Therefore, the divided pulse is synchronized with the clock mark position on the disk.

After time t2, the clock signal of 40 kHz (shown in waveform (e)), which is the clock mark signal, is input to the terminal 600 of the timing clock generation circuit 119 shown in FIG.
The oscillation frequency of 0 is the frequency of the reference clock signal 88.
It becomes 0 kHz. When the count value of the counter 703 is zero, it corresponds to the clock mark position, and the rising edge of the clock of the VCO 610 is synchronized with the mark position on the disk.

In this embodiment, the count value of the frequency divider 611 is set to zero at the first clock mark signal after detecting the UD area. However, it is previously set at a predetermined position between the end of the UD area and the clock mark. A mark is provided and the frequency divider 6
The count value of 11 may be preset to a predetermined value. In this case, the divided pulse and the clock mark signal are synchronized at the preset timing.

An optical disk device using the reference clock generation device of the second embodiment of the present invention will be described below with reference to the block diagram of FIG. The same blocks as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. The disk 100 is the rotating shaft 10 of the motor 101.
It is attached to 2. Then, the motor 101 is controlled by the motor control circuit 823 so as to rotate at a predetermined rotation speed.

The light picked up by the optical pickup 803 to the mark on the disc is read out as a current, and the I / V
It is sent to the converter 114. The output signal of the I / V converter 114 is sent to the tracking error detection circuit 115 and the peak detection circuit 133.

The output of the peak detection circuit 133 is sent to the terminal b of the AND gate 838 and the noise detection circuit 840.
The terminal a of the AND gate 838 is connected to the terminal b of the timing clock generation circuit 819. The timing clock generation circuit 819 outputs from the terminal b a gate signal for detecting a clock mark, which is at a high level during the period when the clock mark exists. Therefore, AND gate 838
The output signal of is a clock mark signal corresponding to the clock mark. The clock mark signal is a signal whose pulse is output at a timing corresponding to the clock mark.

The timing clock generation circuit 819 is PL
It has a built-in L circuit, is synchronized with the clock mark signal input to the terminal a, and has a frequency of 1/1 /
Generates M times the clock signal. The integer 1 / M is set to the number of marks between clock marks, and the PLL circuit generates a reference clock signal synchronized with the mark position on the disk. Further, the timing clock generation circuit 819
Generates a gate signal for detecting a clock mark and a gate signal for detecting the first wobble mark 1006 and the second wobble mark 1007 based on a reference clock signal generated by the PLL circuit. The tracking error detection circuit 115 outputs the tracking error signal as described in the first embodiment. This tracking error signal is sent to the optical pickup positioning mechanism 804 via the control circuit 816. Therefore, the light beam spot is tracking-controlled so as to be located at the center of the track.

The noise detection circuit 840 is the peak detection circuit 1
When there is a pulse corresponding to the clock mark and a pulse due to noise during the period when the gate signal for detecting the clock mark of the output signal 33 is at the high level, the terminal c of the timing clock generation circuit 819 and the control circuit 832 are provided.
A high level signal is sent to the signal via the OR gate 849.
The timing clock generation circuit 819 stops the operation of the phase comparator of the PLL circuit when the terminal c becomes high level.

As a result, the PLL circuit is not affected by the noise during the period when the gate signal for detecting the clock mark is at the high level, and the operation does not become unstable.

The clock mark missing detection circuit 830 ORs the high level signal when there is no pulse during the high level period of the clock mark detection gate signal sent from the terminal b of the timing clock generation circuit 819.
Timing clock generation circuit 81 via gate 849
9 to terminal c and control circuit 832. This prevents the PLL circuit from malfunctioning even when there is no clock mark due to a manufacturing error in the disk.

The memory circuit 839 synchronizes the control voltage of the VCO forming a part of the PLL circuit incorporated in the timing clock generation circuit 819 with the RAM (ran) in synchronization with the reference clock signal over the period in which the disk makes one rotation.
Write and store in the "done access memory". After storing, it is similarly read from the RAM in synchronization with the reference clock signal and added to the control voltage of the VCO.

The control circuit 832 uses the OR gate 8
When the output signal of 49 is always at a low level during one rotation of the disk, that is, when the clock mark is properly read, the memory circuit 839 is instructed to perform the write operation, and thereafter, the stored control voltage is read. Switch to dashi operation. Therefore, it is possible to prevent the unstable control voltage of the VCO from being written in the RAM when there is no clock mark or when there is noise.

V stored in the RAM of the memory circuit 839
The value of the control voltage of the CO becomes the control voltage value of the VCO when the output signal of the VCO follows the change in the cycle of the clock mark caused by the eccentricity of the disk.

Therefore, after switching to the reading operation,
Even if the operation of the phase comparator of the PLL circuit of the timing clock generation circuit 819 is stopped according to the output signal of the OR gate 849, the output signal of the VCO of the PLL circuit follows the change in the cycle of the clock mark caused by the eccentricity of the disk. Signal is obtained. That is, the output signal of the VCO of the PLL circuit is maintained in a state of substantially matching the reference clock signal, and the gate signal for detecting the clock mark can be surely opened at the next clock mark position.

Next, the operation of the optical disk device shown in FIG. 11 will be described based on the waveform chart shown in FIG. 12
FIG. 34A is a diagram schematically showing the arrangement of marks on the disk shown in FIG. 33 of the conventional example.

The waveform (b) is the output signal of the I / V converter 114, the waveform (c) is the output signal of the peak detection circuit 133, and the waveform (d) is the output signal of the terminal b of the timing clock generation circuit 819. A gate signal for detecting a certain clock mark, a waveform (e) indicates the output signal of the terminal d of the timing clock generation circuit 819 indicating the first wobble mark area, and a waveform (f) indicates the timing indicating the second wobble mark area. The output signal of the terminal e of the clock generation circuit is shown. Further, the waveform (g) is the waveform (h) of the output signal of the VCO of the PLL circuit incorporated in the timing clock generation circuit 819.
Is the output signal of the AND gate 838, waveform (i) is the output signal of the noise detection circuit 840, waveform (j) is the output signal of the clock mark drop detection circuit 830, and waveform (k) is the output signal of the OR gate 849. Indicates. Each waveform is a PLL
The waveform is shown when the circuit is operating stably. Also,
The disc 100 is the same as that used in the first embodiment. However, as shown in FIG.
There is noise near the th clock mark and the fourth clock mark from the left is not a manufacturing error.
Therefore, in FIG. 12A, the first and second wobble marks are displaced from each other by 1/4 track in the upper and lower parts of the figure with respect to the center line (dotted line). Further, a wobble mark and a data mark are formed at any of positions where the space between the clock mark and the black mark is equally divided into 22. Each position divided into 22 is named 0 bit to 21 bit, the clock mark is located in 0 bit, the second wobble mark is located in 3 bits, and the first wobble mark is located in 19 bit. One block consists of 0 to 21 bits, and one track consists of 1000 blocks.
Further, the clock marks are formed on a radial straight line emanating from the center of the disk, the angles of adjacent straight lines are all equal, and the clock marks are arranged periodically. As described above, the timing clock generation circuit 819 starts from 0 bit to 2 when the disk is rotating at a predetermined rotation speed.
A reference clock signal is generated in synchronization with 1 bit.

When the light beam spot passes over the disc as shown in FIG. 12A, the output waveform has a peak level at the mark portion as shown in the waveform (b). The peak detection circuit 133 detects the peak position and outputs the peak detection signal shown in the waveform (c). The output signal of the I / V converter 114 is also input to the tracking error detector 115 at the same time. Tracking control is performed according to the level difference between the signals of the first and second wobble marks.

The clock mark detection gate signal shown in the waveform (d), the gate signal showing the first wobble mark region shown in the waveform (e), and the gate signal showing the second wobble mark region shown in the waveform (f) are , PL shown in waveform (g)
It is generated based on the output signal of the VCO of the L circuit.

The output of the AND gate 838 is the pulse (shown in the waveform (c)) of the peak detection signal during the high level period (shown in the waveform (d)) of the gate signal for clock mark detection. It becomes the waveform shown in the waveform (h). The first peak of the waveform (d) is the pulse signal corresponding to the clock mark during the period in which the gate signal for detecting the clock mark is first at the high level, and therefore is indicated by the waveform (i) of the noise detection circuit 840. The output signal becomes low level.

During the period when the gate signal for detecting the clock mark becomes the second highest level, a total of 2 pulses of the pulse corresponding to the clock mark and the pulse k2 generated by noise are generated.
Since there are individual pulse signals, the output signal of the noise detection circuit 840 becomes high level. When the signal of the waveform (h) is input to the clock mark missing detection circuit 830, it corresponds to the clock mark in the first high level period from the left of the gate signal for clock mark detection (shown in the waveform (d)). The output signal of the clock mark dropout detection circuit 830 is at a high level (waveform (j)).
Shown in. ). Since there is no pulse corresponding to the clock mark in the fourth period in which the gate signal for detecting the clock mark of the waveform (d) becomes high level, the output signal of the clock mark missing detection circuit 830 becomes high level. The output of the OR gate 849 shown in the waveform (k) becomes high level when the output signal of the noise detection circuit 840 is high level or the output signal of the clock mark missing detection circuit 830 is high level. While the output of the OR gate 849 is at the high level, the operation of the phase comparator of the PLL circuit of the timing clock generation circuit 819 is stopped, so the PLL
The circuit does not become unstable even when a pulse is generated due to noise or when there is no clock mark.

Next, the operation of the timing clock generation circuit 819 will be described with reference to FIG. FIG. 13 shows a block diagram of the timing clock generation circuit 819. The timing clock generation circuit 119 shown in FIG. 9 of the first embodiment.
The same blocks are given the same numbers and their explanations are omitted. The terminal 900 corresponds to the terminal a of the timing clock generation circuit 819 shown in FIG. 11, and the terminal 902 is the terminal g.
, Terminal 901 to terminal c, terminal 907 to terminal f, terminal 903 to terminal h, terminal 904 to terminal b, terminal 90.
5 corresponds to the terminal d, and the terminal 906 corresponds to the terminal e.

The timing clock generation circuit 819 has a timing generation means, that is, a PLL circuit 910. PLL circuit 91 which is a timing clock generation means
0 produces the reference clock signal. Also, the first and second wobble mark detection gate signals and the clock mark detection gate signal are generated based on the reference clock signal. The PLL circuit 910 includes a phase comparator 911 and a VCO6.
10, a frequency divider 912, delay circuits 913 and 914, a loop filter 915, and an adder circuit 916.

The frequency divider 912 divides the frequency of the output signal of the VCO 610 by a factor of 22, and sends the divided frequency-divided pulse to the terminal a and the terminal 907 of the phase comparator 911 via the delay circuit 914. . The delay circuits 913 and 914 delay the input signal by a predetermined time and output it. The delay circuit 91
3 and the delay amount of the delay circuit 914 are equal. The phase comparator 911 compares the phase of the pulse input from the terminal 900 through the delay circuit 913 to the terminal b and the phase of the signal input to the terminal a, and outputs the phase difference signal corresponding to the phase difference between the two signals to the loop filter 915. Send to. The phase comparator 911 is configured to stop the phase comparison operation when the signal input from the terminal 901 to the terminal c is at high level. The loop filter 915 adjusts the transfer characteristic of the PLL circuit 910.

The output of the loop filter 915 is the terminal 902.
And to the adder circuit 916. The adder circuit 916 adds the signals input to the terminals a and b and sends them to the VCO 610. The level of the signal input to the terminal 903 is zero,
In addition, when the level of the signal input to the terminal 901 is low level, the delay amounts of the delay circuit 913 and the delay circuit 915 are set to be the same, so that the VCO 610 sets the terminal 900
Is controlled so that the pulse signal input to the signal and the signal divided by the frequency divider 912 are synchronized, that is, the phases of both signals match.

The operation of PLL circuit 910 when the level of the signal input to terminal 903 is zero will be described with reference to the waveforms in FIG.

The waveform (a) in FIG. 14 shows the waveform input to the terminal 900. The waveform is the same as the waveform (h) in FIG. The waveform (b) is the output signal of the delay circuit 913, the waveform (c) is the output signal of the VCO 610, the waveform (d) is the output signal of the frequency divider 912 sent to the delay circuit 914, and the waveform (e) is the delay circuit. The output signals of 914 are shown respectively. A waveform (f) shows a waveform input to the terminal 901. In addition,
The waveform is the same as the waveform (k) in FIG.

The pulses k1, k3, k4 of the waveform (a) indicate the pulses corresponding to the clock marks. The pulse k2 indicates a pulse generated by noise. A pulse k5 indicated by a dotted line indicates a case where the clock mark is not a manufacturing error. When the signal shown in the waveform (a) is input to the delay circuit 913, it is delayed by the time L and becomes the waveform (b). The output signal of the frequency divider 912 sent to the delay circuit 914 is VC
The output signal of O610 (shown in the waveform (c)) is divided into 1/22 and becomes the signal of the waveform (d). The output signal of the frequency divider 912 (shown in the waveform (d)) is delayed by the delay circuit 914 by the time L and becomes the signal shown in the waveform (e).

At the terminal a of the phase comparator 911, the waveform (e)
Signal is input. Further, the signal of the waveform (b) is input to the terminal b. The phase comparator 911 detects the phase difference between both signals. When the phase of the waveform (b) is ahead of that of the waveform (e), the terminal d becomes high level, and in the opposite case, the terminal e.
Becomes high level. However, the phase comparison operation is stopped while the level of the signal shown in the waveform (f) is high,
The terminals d and e are at low level. Therefore, the phase comparator 9
The output of 11 has waveforms (g) and (h). When the waveform (g) is at the high level, the oscillation frequency of the VCO 610 is so high that the phase of the output signal of the frequency divider 912 is advanced by the high level signal P2 of the waveform (g). Therefore, the VCO6 is
10 will follow. That is, the output signal of the VCO 610 follows the reference clock signal.

Next, the phase comparator 911 will be described with reference to FIG. FIG. 15 shows a block diagram of the phase comparator 911.

The terminal 940 is the phase comparator 9 shown in FIG.
The terminal b of 11 corresponds. The terminal 941 is a phase comparator 91.
1 corresponds to terminal a, terminal 942 corresponds to terminal c, terminal 943 corresponds to terminal d, and terminal 944 corresponds to terminal e. 94
Reference numerals 5 to 955 denote NAND gates, and 956 and 957.
Indicates an inverter.

The operation will be described with reference to the waveforms shown in FIG.

The waveform (a) shows the signal at the terminal 940, the waveform (b) shows the signal at the terminal 941, and the waveform (c) shows the terminal 942.
, The waveform (d) shows the signal at the terminal 943, and the waveform (e) shows the signal at the terminal 944.

Since the phase of the pulse m1 of the waveform (a) is ahead of the phase of the pulse n1 of the waveform (b), the terminal 943 becomes high level during the period shown in the waveform (d). Since the phase of the pulse m2 of the waveform (a) is delayed as compared with the pulse n2 of the waveform (b), the terminal 944 becomes high level during the period shown in the waveform (d). Pulse m3 of waveform (a) and waveform (b)
During the period of the pulse n3, the terminal 942 is at the high level, the AND gates 945 and 946 are at the low level, and the phase comparison operation is stopped.

Next, the operation of the loop filter 915 will be described with reference to FIG.
It will be described based on. FIG. 17 shows a block diagram of the loop filter 915.

The terminal 960 corresponds to the terminal a of the loop filter 915 shown in FIG. Similarly, the terminal b of the terminal 961 corresponds to the terminal 962 and the terminal c corresponds to the terminal 962. 96
Reference numeral 3 denotes a differential amplifier, which is 964, 965, 966, 96.
7 indicates a capacitor, and 968 to 971 indicate resistors.

FIG. 18 shows an example of transfer characteristics. In the characteristic diagram (a), the horizontal axis represents frequency and the vertical axis represents gain. In the characteristic diagram (b), the horizontal axis represents frequency and the vertical axis represents phase. Considering the sensitivity of VCO 610, resistors 968, 9
The value of 69 is adjusted so that the frequency f is adjusted to the gain intersection of the PLL circuit 910. Therefore, the PLL circuit 910
In the open loop characteristic of, a sufficient phase margin can be obtained and the characteristic becomes stable.

The output of the differential amplifier 963 becomes positive when the terminal 960 becomes high level and becomes negative when the terminal 961 becomes high level with the zero level as the center.
Further, the VCO 610 oscillates at a predetermined frequency when the control voltage is zero, the frequency increases when the control voltage increases, and the frequency decreases when the control voltage decreases.

Next, the operation of the frequency divider 912 will be described with reference to FIG. Terminal 980 is connected to the output terminal of VCO 610 in FIG. Similarly, the terminal 981 is connected to the delay circuit 914, and the terminals 982a to 982e are connected to the data bus line 917, respectively. The counter 983 is a 5-bit counter generally called a synchronous counter in which the counting operation and the clearing of the count value are performed in synchronization with the rising edge of the clock input to the terminal CK. Q0 to Q4 indicate count values. Q0 indicates the lower bit and Q4 indicates the upper bit.

If the rising edge is input to the terminal CK when the terminal CLR is at the high level, the count value is cleared. The clock input to the terminal 980 is input to the terminal CK of the counter 983. The count value of the counter 983 is input to the terminal 982 and the comparators 986 and 988. The comparator 986 outputs a high level when the input value is 21. The output signal of the comparator 986 is input to the terminal CLR of the counter 983. Therefore, the count values Q0 to Q4 of the counter 983 repeat 0 to 21 according to the clock input to the terminal CK. Since the comparator 988 is configured to output a high level when the input value is zero, the output of the comparator 988 is
The clock input to the terminal 980 is divided by 22.

When the PLL circuit 910 is operating normally, a pulse corresponding to a clock mark is input to the terminal 900 of FIG.
The oscillation frequency of 10 becomes equal to the frequency of the reference clock signal. Further, the time when the count value of the counter 983 becomes zero is synchronized with the center position of the clock mark. Also, V
The rising edge of the CO 610 clock is synchronized with the mark position on the disc. That is, the count values Q0 to Q4 of the counter 983 correspond to the time from the clock mark on the disk, that is, the rotation angle of the disk.

Next, the operation of the noise detection circuit 840 will be described with reference to FIG.
It will be described based on. FIG. 20 shows a block diagram of the noise detection circuit 840.

The terminal 850 of FIG. 20 is connected to the output terminal of the peak detection circuit 133 of FIG. Similarly terminal 8
51 is connected to the terminal b of the timing clock generation circuit 819. That is, the gate signal for detecting the clock mark is input to the terminal 851.

The counter 855 is a 2-bit binary counter that counts the rising edges of the signal input to the terminal CK. When the terminal CLR is at high level, counting is stopped and the count value is cleared. The count value of the counter 855 is input to the comparator 856. Comparator 856
Sets the output signal to a high level when the input value is 2. When the output of the comparator 856 becomes high level, the input of the AND gate 858 becomes low level via the inverter 854, so that the count value of the counter 855 remains 2. The flip-flop 857 latches and outputs the level of the terminal D whose rising edge is input to the terminal CK.

The noise detection circuit 8 is based on the waveform of FIG.
The operation of 40 will be described. The waveform (a) in FIG.
The peak detection signal input to 0 is shown. A waveform (b) shows a gate signal for detecting a clock mark input to the terminal 851.

The waveform (c) shows the output signal of the comparator 856, and the waveform (d) shows the waveform of the terminal Q which is the output of the flip-flop 857. The horizontal axis represents time.

At time t11, when the clock mark detection gate signal shown by the waveform (b) becomes high level, the counter 855 starts the counting operation. Since the count value of the counter 855 is zero at time t11, the level of the output signal of the comparator 856 is low level. Therefore, AND
The output of the gate 858 becomes the peak detection signal shown by the waveform (a) input to the terminal 850. Waveform (a) r
With 1 pulse, the count value of the counter 855 becomes 1 and the time t
It becomes 2 with 12 pulses r2. Therefore, at time t12, the output of the comparator 856 becomes high level, and the count value of the comparator 855 is held at 2. When the gate signal for detecting the clock mark shown in the waveform (b) becomes low level at time t14, the output signal of the comparator 856 is latched by the flip-flop 857. That is, terminal 8
The signal at 52 becomes high level at time t14 as shown in the waveform (d). Immediately after that, the counter 855 is cleared.

At time t15, the counter 855 starts the counting operation again. Since only the pulse r3 is present during the period when the clock mark detecting gate signal shown in the waveform (b) is at the high level, the terminal 852 is provided at the time t16 when the clock mark detecting gate signal shown in the waveform (b) becomes the low level.
Signal goes low. As described above, the noise detection circuit 840 can detect that two or more pulses are input during the period when the gate signal for clock mark detection is at the high level.

Next, the operation of the clock mark missing detection circuit 830 will be described. FIG. 22 shows a block diagram of the clock mark missing detection circuit 830.

The terminal 860 of FIG. 22 is connected to the output terminal of the peak detection circuit 133 of FIG. The terminal 861 of FIG. 22 is connected to the terminal b of the timing clock generation circuit 819 of FIG. That is, the gate signal for detecting the clock mark is input to the terminal 861. When the rising edge of the signal input to the terminal CK is input, the flip-flop 863 latches the high level signal of the terminal D and outputs it to the terminal Q. When the terminal CLR is at high level, the terminal Q is at low level. Flip-flop 86
Reference numeral 8 latches and outputs the level of the terminal D in which the rising edge is input to the terminal CK.

The operation of the clock mark detection circuit 830 will be described based on the waveform of FIG. The waveform (a) in FIG. 23 shows the peak detection signal input to the terminal 860. A waveform (b) shows a gate signal for detecting a clock mark, which is input to the terminal 861.

The waveform (c) shows the output signal of the flip-flop 863, and the waveform (d) shows the waveform of the terminal Q which is the output of the flip-flop 868. The horizontal axis represents time. When the clock mark detection gate signal (waveform (b)) becomes high level at time t21, r of the waveform (a) is generated.
With the 11th pulse, the output of the flip-flop 863 becomes high level. When the gate signal for detecting the clock mark shown by the waveform (b) becomes low level at time t23, the output signal of the flip-flop 863 is latched by the flip-flop 868. That is, as shown in the waveform (d), the signal at the terminal 862 becomes low level at time t23. Immediately after that, the flip-flop 863 is cleared. Since there are two pulses r12 and r13 during the period when the gate signal for detecting the clock mark is at the high level from time t24 to t26, the same operation as described above is performed.

Since there is no pulse during the period when the clock mark detection gate signal is at the high level from time 27 to time 28 shown in the waveform (b), the output of the flip-flop 863 remains at the low level. Therefore, at the time t28 when the clock mark detection gate signal shown in the waveform (b) becomes low level, the signal at the terminal 862 becomes high level. As described above, the clock mark detection circuit 830
It is possible to detect that there is no pulse during the period when the clock signal for detecting the clock lock mark shown in the waveform (b) is at the high level.

Next, based on FIG. 24, the memory circuit 839
The operation of will be described.

Tracks are formed on the disc in a spiral or concentric circle with the center of the disc as a reference.
Further, the clock marks are formed on a radial straight line emanating from the center of the disc, and the angles of adjacent straight lines are all equal. Therefore, when the center of the disk coincides with the center of rotation and has no eccentricity and rotates at a constant number of rotations, the time intervals of the clock marks are constant.

However, when the center of the disc deviates from the center of rotation due to displacement of the disc when the disc is attached, the time interval of the clock mark changes. Figure 2
4 (a) shows an example of changes in the time intervals of clock marks when the disc is rotated at a constant number of revolutions with eccentricity. The horizontal axis indicates the angle of rotation. 360 degrees indicates one rotation. Therefore, the timing clock generation circuit 819
The control voltage of the PLL circuit 910 VCO 610 follows the change in the time interval of the clock mark shown in the waveform (a) and becomes the signal shown in the waveform (b) when the PLL circuit 910 is operating normally.

Therefore, the signal shown in the waveform (b) is stored in the memory circuit 839, and thereafter, by applying the stored control voltage to the control voltage of the read VCO 610 in synchronization with the rotation of the disk, noise caused by noise is generated. Even if the operation of the phase comparator 911 of the PLL circuit 910 is stopped when a pulse is generated or when there is no clock mark, the control voltage corresponding to the eccentricity is input, and the change in the time interval of the clock mark due to the eccentricity is VC.
It is possible to make the output signal of O610 follow. Further, by always applying the eccentricity error, the eccentricity error is applied to the control voltage in advance, so that feedforward control is performed and the control accuracy is improved.

Next, the operation of the memory circuit 839 will be described with reference to FIG. FIG. 25 shows a block diagram of the memory circuit 839.

Terminal 870, terminal 871 and terminal 8 in FIG.
Reference numeral 72 is connected to each of the terminals f, g, and h of the timing clock generation circuit 819 shown in FIG. That is, the output of the frequency divider 912 of the PLL circuit 910 is input to the terminal 870, and the output signal of the loop filter 915 of the PLL circuit 910 is input to the terminal 871. The terminal 873 of FIG. 25 is connected to the output terminal of the control circuit 832 of FIG.

The counter 874 is a 10-bit counter generally called a synchronous counter in which the counting operation and the clearing of the count value are performed in synchronization with the rising edge of the clock input to the terminal CK. Q0 to Q9 indicate count values. Q0 indicates the lower bit and Q9 indicates the upper bit. Further, when the rising edge is input to the terminal CK when the terminal CLR is at the high level, the count value is cleared. The clock input to the terminal 870 is the counter 874.
Is input to the terminal CK. The count value of the counter 874 is sent to the comparator 875. In addition, the conversion circuit 876,
It is sent to the address bus of the RAM 878 via the switch 879. The comparator 875 outputs a high level when the input value is 999. The output signal of the comparator 875 is input to the terminal CLR of the counter 874. Therefore, the count values Q0 to Q9 of the counter 874 are the terminal CK.
0 to 999 are repeated according to the clock input to. The disk used in this embodiment has 1000 tracks per track.
It is composed of individual blocks. That is, 1 for 1 track
There are 000 clock marks.

By the way, the PLL input to the terminal 870
The output of the frequency divider 912 of the circuit 910 is synchronized with the clock mark, and even if the clock mark is not formed due to a disc manufacturing error, the pulse is interpolated almost at that position. Therefore, the count value of the counter 874 indicates the rotational position of the disc, and the period in which the count value changes from 0 to 999 indicates the period in which the disc makes one rotation. The low pass filter 880 removes a frequency component higher than the component of the rotation frequency of the disc from the signal input to the terminal 871.

The A / D converter 881 is the low-pass filter 8
The output signal of 80 is converted into a digital signal. The input terminal of the D / A converter 882 is connected to the data bus of the RAM 878, converts a digital signal into an analog signal, and sends it to the switch 883 via the low pass filter 884.

The signal input to the terminal 871 is transferred to the RAM 87.
The operation of writing data in No. 8 will be described. During the writing operation, the control circuit 832 sets the switch 879 to the terminals b and c, connects the switch 883 to the terminals b and c, and sets the RAM 878 to the write mode. Since the terminal b of the switch 883 is set to the zero level, it does not affect the loop of the PLL circuit 910.

The waveform (a) of FIG. 26 shows an example of the relationship between the count value of the counter 874 and the signal input to the terminal 871. The horizontal axis represents the count value of the counter 874, and the vertical axis represents the level of the signal input to the terminal 871. The signal shown in the waveform (a) is converted into a digital value by the A / D converter 881 via the low pass filter 880. The converted digital value is written in the address corresponding to the value of the counter 874 of the RAM 878. The low-pass filter 8
80 causes a phase delay and the value written in the RAM 878 becomes the value shown in the waveform (b). The control circuit 832 switches to the read mode when the write operation is performed during the period in which the disk makes one rotation or more.

The operation of reading the value written in the RAM 878 will be described.

During the reading operation, the control circuit 832
Thus, the switch 879 connects the terminals a and c, the switch 883 connects the terminals a and c, and RA
M878 is set to the read mode.

Since the value written in the RAM 878 is a value (waveform (b)) in which a phase delay has occurred by the low pass filter 880, the address read by the conversion circuit 876 is shifted when reading. That is, when the count value of the counter 874 is zero, the value at address U is read out. Therefore, terminal 8
The signal at 72 has a waveform (c), which is almost the same as the waveform (a). The low pass filter 884 is a filter for removing high frequency noise.

The optical disk device of the third embodiment of the present invention will be described below with reference to the block diagram of FIG. The same blocks as those in the first or second embodiment are designated by the same reference numerals and the description thereof will be omitted.

The optical pickup 803 reads the reflected light for the mark on the disc as a current, and the I / V
It is sent to the converter 114. The output signal of the I / V converter 114 is sent to the delay circuit 922 and the peak detection circuit 133. The delay circuit 922 delays the input signal by a predetermined time and outputs it to the tracking error detection circuit 115. The output of the peak detection circuit 133 is sent to the terminal b of the AND gate 921. A gate signal for detecting a clock mark is sent from the terminal b of the timing clock generation circuit 920 to the terminal a of the AND gate 921. Therefore, AND gate 9
The output of 21 becomes a clock mark signal. The clock mark signal is the terminal a of the timing clock generation circuit 920.
Sent to. The timing clock generation circuit 920 is PL
It has a built-in L circuit. The PLL circuit is synchronized with the clock signal input to the terminal a of the timing clock generation circuit 920 and generates a clock signal having a frequency 22 times that of the clock signal. The timing clock generation circuit 920 also outputs a gate signal for detecting the first and second wobble marks from the terminals c and d. The tracking error detection circuit 115 uses the gate signal for detecting the first and second wobble marks to delay circuit 9
A tracking error signal is detected from the output waveform of 22. A timing clock generation circuit 920 will be described with reference to FIG.
Will be explained. The terminal 920 corresponds to the terminal a of the timing clock generation circuit 920 in FIG. 27, the terminal 927 corresponds to the terminal c, the terminal 928 to the terminal d, and the terminal 929 corresponds to the terminal b.

The same blocks as those of the timing clock generation circuit 119 (a block diagram of which is shown in FIG. 9) of the first embodiment are designated by the same reference numerals. Further, the same blocks as those of the timing clock generation circuit 819 (the block diagram of which is shown in FIG. 13) of the second embodiment are designated by the same reference numerals. Timing clock generation circuit 119 of the first embodiment
The block different from is the frequency divider 912. However, the frequency divider 912 is the same as the frequency divider used in the timing clock generation circuit 819 of the second embodiment. Therefore, PL
The L circuit 930 generates a clock signal in synchronization with the clock mark signal input to the terminal 920 and 22 times the frequency thereof. The operation of the optical disk device shown in FIG. 27 will be described with reference to FIG. FIG. 29A is a diagram schematically showing the arrangement of marks on the disc shown in FIG.

The waveform (b) is the output signal of the I / V converter 114, the waveform (c) is the output signal of the peak detection circuit 133, and the waveform (d) is the gate signal for detecting the first wobble mark. The timing clock generation circuit 9 is the output signal of the terminal c of the clock generation circuit 920, and the waveform (e) is a gate signal for detecting the second wobble mark.
20 shows the terminal d, and the waveform (f) shows the output waveform of the delay circuit 922. In the first embodiment, the rising edge of the peak detection signal coincides with the center position of the mark, but the rising edge of the peak detection signal may shift depending on the processing speed of the peak detection circuit 133. Waveform (c) shows the case where the time is delayed by D. In this case, the clock mark signal delayed by the time D from the clock mark is input to the terminal a of the timing clock generation circuit 920. Therefore, the timing clock generation circuit 920 operates in synchronization with the clock mark signal delayed by the time D. Therefore, the gate signal for detecting the first wobble mark and the gate signal for detecting the second wobble mark are similarly delayed by the time D. If delayed by the time D, the wobble mark detection gate signal cannot detect the wobble mark accurately, and the tracking error signal becomes inaccurate. Therefore, if the delay time of the delay circuit 922 is set to the time D and the signal of the delay circuit 922 shown in the waveform (f) is used, the tracking error signal can be accurately detected.

An optical disk device according to the fourth embodiment of the present invention will be described below with reference to the block diagram of FIG. The same blocks as those in the third embodiment are designated by the same reference numerals and the description thereof will be omitted. The difference from the third embodiment is that the delay circuit 922 is deleted and conversely the delay circuit 951 is
Is added, and the timing clock generation circuit 952
Is the difference in the configuration.

The timing clock generation circuit 952 will be described with reference to the block diagram. FIG. 31 shows a block diagram of the timing clock generation circuit 952. Terminal 961
Is a terminal a of the timing clock generation circuit 952 in FIG.
The terminal 962 corresponds to the terminal c, the terminal 963 corresponds to the terminal d, and the terminal 964 corresponds to the terminal b.

The same blocks as those of the timing clock generation circuit 920 of the third embodiment (a block diagram of which is shown in FIG. 28) are designated by the same reference numerals. The difference from the third embodiment is that a delay circuit 960 is added. Delay circuit 96
0 delays the input signal by the time D and outputs it. Therefore,
The PLL circuit 965 generates a clock signal having a phase advanced by the time D from the clock mark signal input to the terminal 961 and 22 times the frequency thereof. The operation of the optical disk device shown in FIG. 30 will be described with reference to FIG. Figure 3
2A is a diagram schematically showing the arrangement of marks on the disc shown in FIG.

The waveform (b) is the output signal of the I / V converter 114, the waveform (c) is the output signal of the peak detection circuit 133, and the waveform (d) is the clock mark signal output from the AND gate 921. The waveform (e) is the output waveform of the delay circuit 960 of the timing clock generation circuit 952 shown in FIG. 31, and the waveform (f) is the divided pulse of the frequency divider 925 of the timing clock generation circuit 952 shown in FIG. The waveform (g) is the output signal of the terminal c of the timing clock generation circuit 952 which is the gate signal for detecting the first wobble mark, and the waveform (h) is the timing clock generation which is the gate signal for detecting the second wobble mark. The terminal d of the circuit 952 and the waveform (i) show the output waveform of the terminal b of the timing clock generation circuit 952, which is a gate signal for clock mark detection. .

Similar to the third embodiment, the peak detection circuit 13
It is assumed that the rising edge of the peak detection signal deviates from the center of the mark because the processing speed of 3 is slow. Waveform (c) shows the case where the time is delayed by D. In this case, as shown in the waveform (d), time D from the clock mark
The clock mark signal delayed by only the AND gate 921
Is input to the terminal a of the timing clock generation circuit 952 via. The PLL circuit 965 operates so that the delayed divided pulse output from the delay circuit 960 of the timing clock generation circuit 952 shown in FIG. 31 and the clock mark signal shown in the waveform (d) are synchronized. As shown in the waveform (d) and the waveform (e), the pulse output from the delay circuit 960 and the clock mark signal are synchronized. The input signal of the delay circuit 960, which is the divided pulse, is a signal advanced by the time D with respect to the clock mark signal. In this state, the divided pulse coincides with the center of the clock mark as shown in the waveform (f). Therefore, the clock signal oscillated by the VCO 610 of the timing clock generation circuit 952 shown in FIG. 31 is synchronized with the center of the mark. That is, the clock signal oscillated by the VCO 610 becomes the reference clock signal. Therefore, the first wobble mark detection gate signal shown in the waveform (g) becomes a high level at the first wobble mark. Also,
As shown in the waveform (h), the gate signal for detecting the second wobble mark becomes high level at the second wobble mark. However, the gate signal for detecting the clock mark shown in the waveform (i) advances by the time D with respect to the clock mark detection signal. Therefore, the delay circuit 951 delays the time D and sends it to the AND gate 921. Therefore, the pulse corresponding to the clock mark can be accurately extracted from the peak detection signal.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to the embodiments. In the embodiment, the arrangement of the wobble mark and the clock mark is not limited to the one shown in the example, and it is needless to say that the same arrangement can be used even if the front and rear are interchanged and the circuit configuration is changed accordingly.

Further, in the present embodiment, marks are formed synchronously at positions where one block is divided into 22 equal parts, and one track has one track.
Although it is assumed that the circuit is formed of 000 blocks, the present invention is not limited to the example, and the circuit can be similarly used even if the number of divisions and the number of divisions are changed and the circuit is configured accordingly.

Needless to say, in the present invention, the tracks are not limited to the spiral shape and can be concentric.

Further, it is naturally used not only in a read-only optical recording medium having a reflective film such as aluminum or the like, but also in a recordable / reproducible optical recording medium, and in a recordable medium, a phase change recording medium, It does not matter whether it is a magneto-optical recording medium or not.

The same can be applied to an apparatus for recording or reproducing information using magnetism such as a magnetic disk apparatus.

[0150]

As is apparent from the above description,
According to the present invention, the frequency of the clock signal oscillated by the VCO is equal before and after detecting the unique distance, and the count value of the frequency divider is preset by the predetermined mark signal after detecting the unique distance. A stable and high-speed transition to the state synchronized with the clock mark can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of a reference clock signal generation device according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing waveforms at various parts of the embodiment.

FIG. 3 is a block diagram of a peak detection circuit according to the same embodiment.

FIG. 4 is a waveform diagram showing waveforms of respective parts of the peak detection circuit of the same embodiment.

FIG. 5 is a block diagram of a binarizing circuit of the same embodiment.

FIG. 6 is a waveform diagram showing waveforms of respective parts of the binarizing circuit of the embodiment.

FIG. 7 is a block diagram of a UD detection circuit of the same embodiment.

FIG. 8 is a block diagram of a gate generation circuit according to the same embodiment.

FIG. 9 is a block diagram of a timing clock generation circuit of the same embodiment.

FIG. 10 is a block diagram of a frequency divider according to the same embodiment.

FIG. 11 is a block diagram of a reference clock signal generation device according to a second embodiment of the present invention.

FIG. 12 is a waveform diagram showing waveforms at various parts of the embodiment.

FIG. 13 is a block diagram of a timing clock generation circuit of the same embodiment.

FIG. 14 is a waveform diagram showing the waveform of each part of the timing clock generation circuit of the same embodiment.

FIG. 15 is a block diagram of a phase comparator of the same embodiment.

FIG. 16 is a waveform diagram showing waveforms of respective parts of the phase comparator of the same example.

FIG. 17 is a block diagram of a loop filter of the same embodiment.

FIG. 18 is a Bode diagram of the loop filter of the example.

FIG. 19 is a block diagram of a frequency divider according to the same embodiment.

FIG. 20 is a block diagram of a noise detection circuit of the same embodiment.

FIG. 21 is a waveform diagram showing waveforms at various parts of the noise detection circuit of the same example.

FIG. 22 is a block diagram of a clock mark missing detection circuit according to the same embodiment.

FIG. 23 is a waveform diagram showing the waveform of each part of the clock mark dropout detection circuit of the same embodiment.

FIG. 24 is a time interval of clock marks and VC according to the embodiment.
Waveform diagram showing the relationship of O control voltage

FIG. 25 is a block diagram of a memory circuit according to the same embodiment.

FIG. 26 is a waveform chart for explaining the operation of the memory circuit of the same embodiment.

FIG. 27 is a block diagram of an optical disc device according to a third embodiment of the present invention.

FIG. 28 is a block diagram of the timing clock generation circuit of the same embodiment.

FIG. 29 is a waveform chart for explaining the operation of the optical disc device of the same example.

FIG. 30 is a block diagram of an optical disk device according to a fourth embodiment of the present invention.

FIG. 31 is a block diagram of a timing clock generation circuit according to the same embodiment.

FIG. 32 is a waveform diagram for explaining the operation of the optical disc device of the same example.

FIG. 33 is an optical disc for explaining a conventional reference clock signal generation device.

FIG. 34 is a schematic view of the optical disc.

[Explanation of symbols]

100 discs 101 motor 105 light source 106 coupling lens 107 Polarizing beam splitter 108 1/4 wave plate 109 total reflection mirror 110 Focusing lens 111 Photodetector 112 actuator 113 Tracking coil 114 I / V converter 115 Tracking error detection circuit 116 control circuit 119 Timing clock generation circuit 123 Motor control circuit 130 oscillator 132 Control circuit 133 Peak detection circuit 134 Binarization circuit 135 UD detection circuit 136 gate generation circuit 138 AND gate 139 switch 140 AND gate 803 Optical pickup 804 Optical pickup positioning mechanism 819 Timing clock generation circuit 823 Motor control circuit 830 Clock mark missing detection circuit 832 control circuit 839 memory circuit 920 Timing clock generation circuit 922 delay circuit 952 Timing clock generation circuit

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshiyuki Kino 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-112572 (JP, A) (58) Survey Fields (Int.Cl. ⁷ , DB name) G11B 20/10-20/16

Claims (3)

(57) [Claims] 1. A reference clock signal serving as a reference for information reproduction or recording by a PLL (phase locked loop) circuit with reference to a clock mark signal obtained by detecting a clock mark when information is reproduced or recorded. A VCO for generating a first clock signal in the generating device;
Frequency dividing means for dividing the frequency of the first clock signal output from the VCO, clock mark detecting means for detecting a clock mark based on the count value of the frequency dividing means, and second clock signal a clock oscillation circuit for generating, said a switching means for outputting switching an output signal of the output signal and the black <br/> click oscillating means of the clock mark detecting means, an output signal of said switching means and said dividing means Phase comparison means for comparing the phases of output signals and sending them to the VCO, unique distance detection means for detecting a unique distance based on the first clock signal output from the VCO, and based on the output signal of the unique distance detection circuit And a reference mark detecting means for detecting a predetermined mark. And the frequency division ratio of the frequency dividing means is set so that the oscillation frequency of the VCO becomes equal to the frequency of the reference clock signal. When the unique distance detecting means detects the unique distance, the switching means operates. Switching to output the signal of the clock mark detection means, the VC
After setting the frequency division ratio of the frequency dividing means so that the oscillation frequency of O becomes equal to the frequency of the reference clock signal, the predetermined mark is detected by the reference mark detecting means .
In the timing of one time count value of the frequency dividing means to a predetermined value
Was observed preset Thus, the reference clock signal generator of the sample servo type optical disc apparatus, characterized in that to obtain the desired reference clock from the VCO. 2. The reference clock signal generating device of the sample servo type disk device according to claim 1, wherein said clock oscillating means is configured to generate a clock signal according to the number of rotations of the disk. 3. A engagement value of said dividing unit as to constitute a reference mark detecting means so as to clock marks immediately after detecting the unique distance said predetermined mark
3. The reference clock signal generator of the sample servo type disk device according to claim 1, wherein zero is set as a preset .