JPH06180844A - Optical recording and reproducing device - Google Patents

Abstract

PURPOSE:To solve a program that the signal recording or reproducing is impos sible during a time for the drawing time due to the switch of a timing clock in the case of switching a zone at the time of recording or reproducing on a recording medium with a converged beam. CONSTITUTION:A reflected beam from the recording medium 101 is converted to a current by a photodetector 111, and is made a voltage waveform by an I/V converter 114 and binarized by a binarization circuit 118, and a synchronizing signal is detected by a CK mark detecetion circuit 117, and the timing clock suiting to the first zone of the recording medium is oscillated by a timing clock generation circuit 119 based on the synchronizing signal and used for a tracking servo and the address reading. Then, the present track is detected with an address read circuit 120 by a control circuit 119, and the timing clock suitable for a required zone is oscillated by a second oscillation circuit, and a clock selection circuit 122 is controlled to select suiting the timing clock and a gate interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical reproducing apparatus for recording information on a recording medium with a focused light beam or reproducing the recorded information. Regarding sample format format.

[0002]

2. Description of the Related Art In recent years, an optical recording / reproducing apparatus holds a large amount of data in a recording medium and can reproduce it, so that it occupies an important position in recording and reproducing audio information data, video information data, and various information equipment data. ing.

FIG. 13 shows a recording state on a recording medium of a sample format type in a conventional optical recording / reproducing apparatus. In FIG. 13, reference numeral 1301 denotes a recording medium substrate,
For example, it is formed of a resin such as polycarbonate having a thickness of 1.2 mm, and tracking marks (also referred to as tracking pits) 1305 and 1306 and clock marks (also referred to as clock pits) 1307 also referred to as wobble marks are injected on one surface. And the like. This tracking mark 1305,1
A servo area 1303 composed of 306 and clock marks 1307 is formed radially from the center of the recording medium substrate 1301, and is centered on each track indicated by the one-dot chain line 1304 and slightly on both sides thereof (for example, 1/4 track pitch each). ) Tracking marks 1305 and 1306 for tracking servo are arranged by being deviated,
Subsequently, a clock mark 130 for clock reading
7 are provided on the track center line 1304. Information areas 1308 are also radially formed between the servo areas 1303. Then, a recording thin film 1302 made of a phase change recording material containing Te (tellurium) as a main component is formed on the surface by a method such as sputtering.

Assuming that the recording medium of the sample format described above is rotated at a constant angular velocity as a premise, in order to effectively use the radial information area 1308, information recording of the information area 1308 portion between the servo areas 1303 is performed. The density should be closer to the outer circumference. For example, the surface of the recording thin film 1302 is concentrically divided into four zones (zones 0 to 3). For example, one information area in zone 0 has 10 bytes, and zone 1 has 14 bytes.
The amount of information is increased toward the outer periphery, such as 18 bytes for zone 2 and 22 bytes for zone 3.

[0005]

However, in order to make the information density of the recording medium closer to the outer circumference, the timing clock frequency for reading or writing the information is different for each zone, and the higher the outer circumference is, the higher the timing clock frequency is. If the timing clock for reading the address recorded on the recording medium or the timing clock for detecting the peak value of the wobble mark and the timing clock for reading or writing the information are combined, the frequency becomes It will be extremely high.

For example, the frequency of the timing clock for zone 0, zone 1, zone 2, and zone 3 is set to 10M.
Hz, 14 MHz, 18 MHz, 22 MHz, 10 MHz is used as a timing clock for detecting the position of the wobble mark, and a timing clock for detecting the peak value of the wobble mark and a timing clock for reading or writing information are used. Combined use, 10 MHz in zone 0 and 10 M in zone 1
70 MHz, which is the least common multiple of Hz and 14 MHz, and 9 which is the least common multiple of 10 MHz and 18 MHz in Zone 2.
At 0 MHz, in zone 3, the least common multiple of 10 MHz and 22 MHz is 110 MHz, and it is necessary to obtain a timing clock of a predetermined frequency by dividing the timing clock of these frequencies. Further, if it is intended to realize high density recording by providing versatility in zone division, for example, the timing clock for zone 0 is 9.85 MHz and that for zone 1 is 1
A frequency such as 4.8 MHz is required, and a clock with a higher frequency is required. Also, when the timing clock for reading the address and the timing clock for reading or writing the information are both used, the frequency becomes extremely high as well.

As described above, the conventional optical recording / reproducing apparatus has a problem that the circuit is complicated and expensive because it is necessary to handle a high frequency clock. Also,
In order to solve this, the zone division method is limited due to the limitation of the clock frequency, and high-density recording cannot be performed.

Further, in the conventional optical recording / reproducing apparatus, in order to make the information density of the recording medium closer to the outer circumference, the timing clock frequency for reading or writing information is different for each zone, and the timing clock frequency is closer to the outer circumference. Since it is necessary to increase the frequency, a PLL circuit normally used as a timing clock generation circuit requires a pull-in time of 3 to 5 mS when switching the timing clock frequency. There is a problem that signal recording or reproduction cannot be performed.

The present invention solves the above-mentioned conventional problems, enables high-density recording and reproduction with a low-frequency timing clock, and instantaneously records or reproduces a signal when a desired track is searched. It is an object of the present invention to provide a simple and inexpensive optical recording / reproducing device capable of starting reproduction.

[0010]

In order to achieve this object, an optical recording / reproducing apparatus of the present invention is, as a first invention,
A plurality of clock marks for synchronization and an address for identifying the position are provided per circle on a spiral or concentric track rotated at a constant angular velocity, and the clock mark connects with that of an adjacent track. The trajectories are arranged so as to be radial with respect to the center, and the addresses are recorded so that they can be reproduced in synchronization with the clock marks in all tracks and at the same timing clock, and in at least two zones in the radial direction. The divided information area records information by irradiating a light beam on a recording medium capable of accumulating information so that the amount of information per circle is larger in the outer zone than in the inner zone, or A device for reproducing recorded information, comprising: a conversion means for converting information recorded on a recording medium into an electric signal; Sync signal detecting means for detecting a sync signal corresponding to the clock mark from the signal of the step, and recording information in a specific zone on the recording medium based on the sync signal detected by the sync signal detecting means, or recording First timing clock generating means for generating a timing clock of a first frequency for reading the stored information, and the signal of the converting means is determined based on the timing clock from the first timing clock generating means. An address reading circuit for reading an address recorded on a recording medium, and recording information on the recording medium,
Alternatively, second timing clock generating means capable of generating a timing clock having one or more frequencies synchronized with the synchronizing signal for reading recorded information, and recording based on an address read by the address reading circuit Selecting the output of the first timing clock generating means when determining the zone in which the light beam on the medium is located, or when searching the desired track based on the address read by the address reading circuit, Or a control means for instructing the second timing clock generating means to generate a timing clock having a frequency suitable for the zone and deciding whether to select it.

A second invention is an apparatus for irradiating a light beam on a recording medium similar to that of the first invention for recording information or reproducing recorded information on the recording medium. Converting means for converting recorded information into an electric signal, synchronizing signal detecting means for detecting a synchronizing signal corresponding to the clock mark from the signal of the converting means, and synchronizing signal detected by the synchronizing signal detecting means First timing clock generating means for generating a timing clock of a first frequency for recording information in a specific zone on a recording medium or reading recorded information based on the recording medium; Period signal generating means for generating a period signal corresponding to each position of the pair of wobble marks based on a timing clock of the generating means; On the recording medium according to a difference between both peak values of the pair of wobble marks from the peak detecting means, the peak detecting means detecting the respective peak values of the pair of wobble marks based on the period signal of the signal generating means. Control means for controlling the optical beam of the optical disc to be positioned on the track center line, and one or a plurality of frequencies for recording information on the recording medium or for reading the recorded information based on the synchronization signal. And a second timing clock generating means capable of generating the timing clock.

In a third aspect of the invention, the first timing generating means is different from the first timing generating means in the first aspect of the invention for recording information in a specific zone or for reading recorded information. But also second
Is different from the second timing generating means in the first aspect of the invention, it is capable of generating timing clocks of a plurality of frequencies synchronized with the synchronizing signal, and the control means is the control means of the first aspect of the invention. Different from the address read by the address reading circuit, determine the zone where the light beam on the recording medium is located,
Alternatively, when searching for a desired track based on the address read by the address reading circuit, the second timing clock generating means is instructed to generate a timing clock having a frequency suitable for the zone. is there.

In a fourth invention, the first timing generating means is different from the first timing generating means in the first invention for recording information in a specific zone or for reading recorded information. But also second
The timing generating means is different from the second timing generating means in the first aspect of the invention in that it can generate timing clocks of a plurality of frequencies synchronized with the synchronizing signal.

[0014]

In the first aspect of the present invention, the synchronizing signal is detected from the clock mark of the recording medium, and the first timing clock generating means is the timing of the first frequency synchronized with the synchronizing signal. A clock is generated, and the address recorded on the recording medium is read by an address reading circuit based on the clock, while the second timing clock generating means generates a timing clock of one or a plurality of frequencies synchronized with the synchronizing signal. Then, the control means determines the zone in which the light beam is located on the recording medium based on the read address, or searches the desired track based on the address read by the address reading circuit. Matches the track's zone if the timing clock is not in a specific zone Controlling the second timing clock generating means to generate the timing clock of the wave number, selecting the timing clock of the first or second timing clock generating means according to the zone, and recording the information on the recording medium. Or it acts to read the recorded information.

In the second invention, the period signal generating means generates a period signal corresponding to each position of the pair of wobble marks based on the timing clock from the first timing clock generating means, and the period signal is generated. Based on the above, the peak detecting means detects the respective peak values of the pair of wobble marks, thereby performing tracking control for controlling the light beam on the recording medium to be located on the track center line according to the difference between the two peak values. So that the second timing clock generating means can generate the timing clock of one or more frequencies based on the synchronization signal to record the information on the recording medium or to read the recorded information. To work.

Further, in the third invention, the synchronizing signal is detected from the clock mark of the recording medium, the first timing clock generating means generates the timing clock of the first frequency synchronized with the synchronizing signal, and The address recorded on the recording medium is read by the address reading circuit based on the above, and the control means determines the zone where the light beam is located on the recording medium based on the read address, or the address reading circuit reads it. When searching for the desired track based on the address
The second timing clock generating means is controlled to generate a timing clock having a frequency suitable for the zone of the track, the timing clock of the second timing clock generating means is selected according to the zone, and information is recorded on the recording medium. Acts to record or read recorded information.

Further, in the fourth invention, the period signal generating means generates a period signal corresponding to each position of the pair of wobble marks based on the timing clock from the first timing clock generating means, and the period signal is generated. Based on the above, the peak detecting means detects the respective peak values of the pair of wobble marks, thereby performing tracking control for controlling the light beam on the recording medium to be located on the track center line according to the difference between the two peak values. The second timing clock generating means is operative to generate timing clocks of a plurality of frequencies based on the sync signal to record information on the recording medium or to read the recorded information.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An optical recording / reproducing apparatus according to embodiments of the present invention will be described below with reference to the drawings. First of the present invention
1 of the block diagram showing the embodiment, the phase change type recording medium 101 is attached to the rotating shaft 102a of the motor 102 and rotated at a predetermined angular velocity. Transfer stand 10
4, a light source 105 such as a semiconductor laser, a coupling lens 106, a polarization beam splitter 107,
Quarter wave plate 108, total reflection mirror 109, photodetector 111
A fixed portion (not shown) of the actuator 112 is attached, and the transfer table 104 is configured to move in the radial direction of the recording medium 101 by the transfer motor 103 such as a linear motor.

An optical beam generated by a light source 105 such as a semiconductor laser arranged in the transfer table 104 is collimated by a coupling lens 106, and then polarized beam splitters 107, 1/4. After passing through the wave plate 108, the total reflection mirror 1
09, the recording medium 10 is reflected by the focusing lens 110.
The first recording surface is focused and irradiated. The reflected light reflected by the recording surface of the recording medium 101 passes through the focusing lens 110, is reflected by the total reflection mirror 109, and is reflected by the quarter wavelength plate 10.
After passing through 8, the light is reflected by the polarization beam splitter 107 and irradiated onto the photodetector 111. Focusing lens 110
Is attached to the movable part of the actuator 112. The actuator 112 is composed of a tracking coil 113 provided in the movable part and a permanent magnet (not shown) attached to the fixed part. Therefore, when an electric current is passed through the tracking coil 113, the focusing lens 11 is generated by the electromagnetic force received by the coil.
0 is the radial direction of the recording medium 101, that is, the recording medium 10
Move across the upper track (left and right in the figure).

A coil (not shown) for a focus is also attached to the movable part of the actuator 112, and when an electric current is passed through this coil, an electromagnetic force is received by the coil from a permanent magnet (not shown). The focusing lens 110 is configured to be movable in a direction perpendicular to the surface of the recording medium 101. The focusing lens 110 is used for the recording medium 10
Focusing control is performed so that the light beam radiated on the beam 1 is always in a predetermined focusing state.

The output of the photodetector 111 is input to an I / V converter 114 that converts a current into a voltage, and the photodetector 111 is output.
Output current is converted to voltage and output. I / V converter 1
One of the output signals of 14 is the tracking error detector 11
5, the tracking error detector 115 detects the tracking error from the position of the focused light with respect to the wobble mark in FIG. 13 described above. The tracking error signal from the tracking error detector 115 is applied to the actuator 112 via the control circuit 116, and the recording medium 10
The light beam on No. 1 is tracking-controlled so as to be located between the wobble marks 1305 and 1306, that is, on the track center line.

The output signal of the I / V converter 114 is CK.
It is input to the mark detection circuit 117 and the binarization circuit 118. The binarization circuit 118 binarizes the output signal of the I / V converter 114, and sends this binarized signal FIG. 5C to the CK mark detection circuit 117. The interval between the second tracking mark and the clock mark in FIG. 5A has a unique distance of t as shown in FIG. 5C, and this time interval is configured not to occur in other parts. The CK mark detection circuit 117 detects the clock mark position by utilizing this fact, and differentiates the waveform of the portion corresponding to the output of the clock mark of FIG. 5B to obtain the synchronization signal of FIG. Is output. The timing clock generation circuit 119 generates a timing clock for detecting the servo area, reading the address, and reading the information recorded in the zone 0 in synchronization with the synchronization signal shown in FIG. 2 to 3 and a circuit for generating a timing clock for reading the information recorded in Nos. 3 to 3.
The timing clock generating circuit for reading the information recorded in the zones 1 to 3 is the control circuit 12
In response to the instruction No. 1, the timing clock adapted to each zone of the recording medium is generated. Then, the timing clock generation circuit 119 uses the synchronization signal shown in FIG.
With reference to (c), a timing clock is generated according to the zone of the recording medium, and a gate output is given to each section. This will be described in detail later. The address reading circuit 120 is supplied with the binary signal of the binarizing circuit 118 and the timing clock for the zone 0 of the outputs of the timing clock generating circuit 119. The address read circuit 120 outputs 2 based on this timing clock.
The address on the recording medium is read by determining whether the digitized signal is 1 or 0, and the read address is used by the control circuit 12.
Send to 1. The control circuit 121 controls the clock selection circuit 122 so as to select the timing clock for zone 0 when the address read by the address reading circuit 120 is zone 0.

When the address read by the address read circuit 120 is in zones 1 to 3, the control circuit 121 causes the timing clock generation circuit 119 to operate.
Control circuit to generate a timing clock corresponding to the zone corresponding to the address position and select the timing clock for zones 1 to 3
22 is controlled. The data reading circuit 123 includes a binarized signal from the binarizing circuit 118 and a clock selecting circuit 122.
The read clock signal selected in is input.
The data reading circuit 123 determines the binarized signal based on the read clock signal and reads the information recorded on the recording medium 101.

The search for a desired track will be briefly described. When the address of the desired track is input to the control circuit 121, the control circuit 121 reads the address of the track where the light beam on the recording medium 101 is located from the address sent from the address reading circuit 120, and reads the desired address. Calculate the distance to the track you want to go to. If the calculated distance exceeds the predetermined range, the tracking control is disabled as the sparse search, the transfer motor 103 is driven, and the transfer table 104 is moved to the recording medium 101.
In the radial direction, the tracker control is operated again by detecting the arrival at the vicinity of the desired track, and the light beam on the recording medium 101 is positioned from the address sent from the address reading circuit 120. The address of the existing track is read and the distance to the desired track is calculated. When the calculated distance exceeds the predetermined range, the sparse search described above is performed again. When it is within the predetermined range, the actuator 112 is driven to perform the fine search by jumping track by track. After that, the address is read again, and if the read address matches the address of the desired track, the search is ended, and if it does not match, the above-described search operation is repeated to search for the desired track.

Then, the control circuit 121 selects the timing clock for zone 0 when the address is zone 0, and selects the timing clock for zones 1 and 3 when the address is zones 1 to 3. Controls the circuit 122. When searching for the desired track, if the desired address is in zones 1 to 3, the control circuit 121 corresponds to the desired address position immediately after the desired track is input or during the search operation. Timing clock generation circuit 11 so as to generate a timing clock corresponding to a zone
Control 9 Therefore, when the search is finished,
Since the clock selection circuit 122 outputs the timing clock having the frequency corresponding to the zone corresponding to the desired track position, the data reading circuit 123 synchronizes with the clock sent from the clock selection circuit 122 to obtain the necessary data area. The data of can be read immediately.

Before going into the detailed description of the circuit operation, it will be explained how the data on the recording medium is arranged. FIG. 6 conceptually shows the format on the recording medium. As shown in FIG. 6A, servo areas and information areas are alternately arranged on the tracks on the recording medium.
One block is made up of a pair of servo area and information area. Then, as shown in FIG. 6B, one sector is composed of (n + 1) blocks, and the information area of the first block of the sector is an address area in which an address for identifying the position of the sector is recorded. And the data is recorded in the information area of the n blocks following it. Next, as shown in FIG. 6C, one track in a certain zone is composed of (m + 1) sectors, and when one track is not divisible by one sector length, a surplus area is provided at the end of the track.

Next, the circuit operation will be described with reference to FIG. 2 showing the details of the timing clock generation circuit 119 and the clock selection circuit 122 in FIG. 1 and FIG. 5 showing the marks on the recording medium and the waveforms of each circuit portion. . Here, a case where the zones of the recording medium are formed by four zones 0 to 3 will be exemplified. In FIG. 2, the phase comparator 200 and the VCO
(voltage controlled ocsilator) 210 and frequency divider 220
Is the first timing clock generating means PLL (p
hase locked loop) 1 is formed, and the counter circuit 230 which is the first counting means, the decoder C240 which is the first decoding means, the AND circuit 250 and the AND circuit 260 in the clock selection circuit 122 are in the servo area. Generation of timing clock frequencies for detection, address reading, zone 0 data reading and gating for zone 0. The frequency divider 220 divides the clock frequency of the VCO 210, and for example, the frequency divider 220.
If the frequency division ratio is 1/200, the oscillation frequency of the VCO 210 is 200 times the clock mark frequency of the clock mark detector 117. The counting circuit 230 is VC
The output clock of O210 is counted and reset by the clock signal sent from the frequency divider 220. Since the PLL 1 operates so that the signal of the clock mark detector 117 and the signal of the frequency divider 220 have the same phase, the count value of the counting circuit 230 is the time from the clock mark detected by the clock mark detector 117, that is, the distance. Is represented. The decoder 240 includes two bit comparators, one of which detects that the count value of the counting circuit 230 has exceeded a predetermined value, and the other of which has a count value of the counting circuit 230 equal to or less than a predetermined value. Detect that there is.

Then, it is detected from the logical product of both bit comparators that the count value of the counter circuit 230 is in a predetermined range, that is, a period corresponding to the information recorded in zone 0, and a high level signal is ANDed during this period. Send to circuit 250. Therefore, the clock signal output from the AND circuit 250 becomes a clock signal for reading the address recorded in the entire area and the information recorded in the zone 0. The decoder A242 and the decoder B243 are the decoder C240.
The gate operation for detecting the first and second servo marks is performed respectively.

The phase comparator 201, the VCO 211 and the frequency divider 221 form a PLL2 which is the second timing clock generating means, and this and the counting circuit 231 which is the second counting means and the second decoding means. A decoder D24
1. The AND circuit 251 and the AND circuit 261 in the clock selection circuit 122 generate a timing clock frequency for reading data in zones 1 to 3 and perform a gate operation. The decoder 241 has the same configuration as the decoder 240, but is configured so that the control circuit 121 can control the comparison value of the bit comparator.
Further, the frequency division ratio of the frequency divider 221 is also controlled by the control circuit 121.
It is configured to be controlled by.

The control circuit 121 includes a frequency divider 221.
And the decoder D241 to control the timing clock frequency of the PLL2 including the frequency divider 221. The gate period of the decoder 241D is determined by the number of counts of the counting circuit 231. The decoder C240 or the decoder D241 gates the gate period. A signal for selecting the selected clock is sent to the AND circuit 260 or 261 and the OR circuit 2
70 outputs one timing clock selected from the clock outputs of the AND circuit 260 or 261;
This is sent to the data reading circuit 123.

FIG. 5A is a diagram schematically showing the arrangement of marks (pits) on the recording medium. The first and second tracking marks are located above and below the center line (dotted line). They are deviated, and so-called wobble marks are formed.
FIG. 5B shows an output pulse waveform of the I / V converter 114,
The binarization circuit 118 binarizes it as shown in FIG.
The time interval t between the second tracking mark and the clock mark is called a so-called unique distance, and the mark interval is arranged so that this interval t cannot appear in other parts. In the CK mark detection circuit 117, paying attention to this time t, the pulse after this interval is detected as a synchronization signal and the signal shown in FIG. 5D is output. This output is applied to each of the phase comparators 200 and 201 of the timing clock generation circuit 119. When the zone 0 of the four-zone circuit shown in the figure is explained, the phase comparator 200,
The timing clock shown in FIG. 5 (f) is output from the VCO 210 by the PLL 1 including the VCO 210 and the frequency divider 220. This is synchronized with the phase of the timing clock by the frequency divider 220, and at the position of the synchronization signal as shown in FIG.
The waveform of (e) is generated, and the counting circuit 23 reset by this
0 counts the number of data in the information area of zone 0,
As in the waveform of FIG. 5 (i), the decoder C240 determines how many gates of the counting circuit 230 to open the gate, and outputs the output and the VCO output of FIG. 5 (f) to the AND circuit 250. Output.

In this case, in the example of FIG. 13, in the zone 0, it is detected by the counting circuit 230 that the information area is completed by counting 10 bytes, that is, by 80 pulses, but in FIG. It is shown as finished. Decoder A242, Decoder B2
Output waveforms 43 of FIGS. 5 (g) and 5 (h) are given to the tracking error detector 115 as gates for detecting the first and second tracking marks, and the first and second tracking marks of FIG. The peak value of each output waveform is detected, the difference between the two peak values is obtained by a differential amplifier (not shown), and the control circuit 116 makes both waveforms have the same level.
The recording medium 10 by controlling the actuator 112 via the
Tracking control is performed so that the optical beam focused on the optical disc 1 is always located on the track center line. Further, the transfer table 104 is applied from the control circuit 116 to the transfer motor 103, and the transfer table 104 is transferred and controlled so that the focusing lens 110 moves in the radial direction of the recording medium centering on the natural state. The waveform (i) in FIG. 5 becomes high at the falling edge of the first clock of the timing pulse shown in FIG. 5 (f) after the decoder C240 outputs the clock mark, and becomes low at the falling edge of the 11th clock. It is described that the gate is opened as described above to operate so as to detect 10 pulses in the information area.

The structure of the tracking error detector 115 will be described with reference to FIG. The tracking error detector 115 detects and holds the peak value of the first tracking mark shown in FIG. 5A and holds the peak value of the second tracking mark. The second peak detection circuit 1220 and the differential amplifier 1217 that outputs a signal according to the difference between the outputs of the peak detection circuits 1210 and 1220 are included.
The output signal of the I / V converter 114 is input to the switches 1211 and 1221 in the first and second peak detection circuits 1210 and 1220. Also, the gate signal for the first tracking mark shown in FIG. 5 (g) sent from the timing clock generation circuit 119 is input to the first peak detection circuit 1210, and the gate signal for the second tracking mark shown in FIG. h) is the second peak detection circuit 122
It is input to 0. The operation of the first peak detection circuit 1210 will be briefly described. Reference numerals 1211, 1213 and 1215 are switches, 1214 is an inverting circuit for inverting the polarity of an input signal, and 1212 and 1216 are amplifiers having high input impedance. The gate clock period signal (high level signal) for the first tracking mark is output from the timing clock generation circuit 119 to the switches 1211, 1
When input to the gate signal input terminal of 215 and the inverting circuit 1214, the switches 1211, 1215 are in a short-circuited state,
The switch 1213 is in an open state. I / V converter 11
The signal No. 4 is stored in the capacitor C11 via the switch 1211 and the diode D11. Diode D11
Is an I / V converter 11 higher than the potential of the capacitor C11
Since the output signal of No. 4 is passed and the signal of low potential is not passed, the potential of the capacitor C11 becomes the highest potential in the gate period for the first tracking mark sent from the timing clock generation circuit 119. When the timing clock generation circuit 119 completes the gate period signal for the first tracking mark, that is, when it becomes a low-level signal, the switches 1211, 1215 are opened and the switch 1213 is short-circuited. The charge accumulated in the capacitor C11 is switched to the switch 1213.
The potential of the capacitor C11 becomes zero due to the discharge through the capacitor C11, but the peak potential accumulated in the capacitor C12 is held because the switch 1215 is opened. Then, the timing clock generation circuit 119 again returns to the first
When the gate period signal for the tracking mark is input, the peak signal of this period is accumulated in the capacitor C11, and the amplifier 1212, the switch 1215, and the resistor R1.
A new peak potential is held in the capacitor C12 via 1. Since the configurations of the first peak detection circuit 1210 and the second peak detection circuit 1220 are exactly the same,
The operation of the peak detection circuit 1210 is omitted.
In this way, the peak potential is held in the capacitors C12 and C22, and the held peak signal is stored in the amplifier 12
16 and 1226 to the differential amplifier 1217. The differential amplifier 1217 outputs a tracking error signal according to the difference between the two peak signals, and this signal is output to the control circuit 1
Send to 16.

Next, as shown in FIG. 13, the servo areas 1303 are radially arranged on the recording medium 1301. This is based on the premise that the sample format recording medium has the same number of wobble marks and clock marks per rotation on all tracks when the recording medium 1301 is rotated at a constant angular velocity, and is reproduced. The marks are arranged so that the time intervals between the marks are also the same. This is to speed up track access and signal recording / reproduction. That is, in the present invention, the clock mark 1307 serves as a reference for obtaining a synchronization signal for accurately recording or reproducing a signal near the center of the track, and it is desirable that this can be always identified. If the clock marks 1307 are present in different tracks for each track, the pull-in operation for extracting the sync signal must be performed each time the desired track is accessed. For example, when a track jump is performed from one track to another track, if there is a phase or frequency difference between the clock mark 1307 on the jump destination track and the clock mark 1307 on the original track, synchronization will be lost on the new track. ,
There is a problem that it takes time until synchronization is performed again, and signal recording / reproduction cannot be executed immediately after the track jump ends. Therefore, the clock marks 1307 are arranged so as to have the same phase over all tracks.

FIG. 7 shows time intervals of address data when the address area provided at the head of each sector on the track is reproduced for data access. Similar to the servo area, the mark reproduction frequency is the same in the address area. That is, the addresses of all areas are recorded so that the information recorded in the innermost zone 0 can be read by the clock for reproducing. This is for the same reason as above, so that the address can be read immediately when searching for the desired track,
This is to realize high-speed search. The information amount of one sector is constant, for example, 1024 bytes. On the other hand, since the amount of information per rotation of the recording medium differs depending on the zone, the number of sectors per rotation differs depending on the zone, and therefore the number of addresses also necessarily varies depending on the zone. For example, if the addresses of the sector 0 are provided so as to be radially arranged in the radial direction of the recording medium over all the zones, the addresses of other sectors are arranged radially in the same zone, but the addresses of the other zones are not necessarily the same. Do not line up radially. However, since an address mark that can identify the address position is also recorded at each address, it is possible to instantaneously read based on this address mark.

By arranging the servo areas in this way, the distance between the servo areas becomes wider toward the outer circumference, and if the number of recordable bits in the data areas between the servo areas is the same on the inner and outer circumferences, the data bits are inevitably divided. The interval becomes wider toward the outer circumference, and the amount of data decreases.

For the above reason, in the present embodiment, the number of recordable bits in the data area on the outer periphery of the recording medium is increased so that the spatial interval between the data in the data area becomes substantially constant. Then, the clock frequency for data reproduction in the data area inevitably becomes higher in the outer zone.

Therefore, it is necessary to increase the timing clock frequency in the outer peripheral zone. In this embodiment, the output frequency of the PLL is set higher toward the outer zone of the recording medium. For example, in FIG. 8, V in zone 3
The CO output is higher than that of zone 0. Therefore, when reading data in the zone 0, the control circuit 121 sends a high level signal to the AND circuit 260 only during the period of reading data (in the normal state, the control circuit 121 sends the high level signal to the AND circuit 260 and the AND circuit 261). The control signal is at low level). Since the VCO 210 outputs the timing clock signal for zone 0 and the decoder C240 outputs the gate signal for reading the data in the information area of zone 0, the AND circuit 250 only outputs the data in the information area of zone 0. Outputs the timing clock signal. Then, the clock signal from the AND circuit 250 is transferred to the data reading circuit 12 via the OR circuit 270.
The data reading circuit 123 can read the data by determining whether the binarized signal from the binarizing circuit 118 is 1 or 0 in synchronization with this clock signal.

A case where a desired track in zone 3 is searched from the state where the light beam is located on the track in zone 0 will be described. Since the timing clock signal for zone 0 is constantly supplied to the address reading circuit 120 via the AND circuit 250, the control circuit 121 can read the address of the track where the light beam is located. Control circuit 121
Reads the address of the track where the light beam is located on the recording medium 101 from the address sent from the address reading circuit 120, calculates the distance to the desired track, and starts the search operation. At the same time, the control circuit 121 sets the frequency division ratio of the frequency divider 221 and
The O211 controls so as to oscillate a timing clock having a frequency suitable for the zone 3, and the decoder D2
The gate period of the decoder D241 is set so that 41 outputs the signal only during the gate period that matches the zone 3. Then, within the period in which the desired track is searched, P
Since LL2 becomes stable and the VCO 211 oscillates a timing clock having a frequency suitable for zone 3, the search for the desired track is completed and the control circuit 12
If 1 sends a high level signal to the AND circuit 261 (the control signal which is always sent from the control circuit 121 to the AND circuit 260 is low level as a matter of course), the timing clock signal via the AND circuit 251 becomes The data is sent to the data reading circuit 123 via the OR circuit 270, and the data reading circuit 123 can immediately read the desired data in the zone 3.

As described above, since the positions of the clock marks in each zone are in the same phase, when reproducing any one of the zones, the sync signals of the other zones are also zone 0.
The phase is the same as that of the control signal, and the timing clock is controlled by the control circuit 121 based on this synchronization signal so that the timing clock is generated in a period required for each zone. Also, the timing clock adapted to the zone can be supplied immediately upon the zone switching.

Here, the pull-in time of the PLL 2 after the frequency of the timing clock adapted to each zone is determined and instructed by the control of the control circuit 121 is 3 to.
Although it takes 5 ms, it usually takes about 5 to 50 ms until the address area is searched and the access is completed. Therefore, the PLL circuit is completely pulled in by the completion of the access, and the timing clock frequency becomes stable. Therefore, the data can be read out immediately.

As described above, in the first embodiment, the timing clock frequency is oscillated by the first PLL for detecting the servo area, reading the address, and reading the data of the zone 0, and the other zones are set to the first clock at the time of access. 2 PL
The timing clock frequency suitable for the zone is oscillated by L, and the pulling-in of the timing clock frequency is completed during the period until the desired track in the desired zone is accessed. Therefore, immediately when the desired track is accessed, Since it is possible to switch to the timing clock of that zone, it is possible to solve the conventional problem that signal reproduction cannot be performed during this period due to the pull-in time of the timing clock generation circuit due to timing clock switching.

Further, there are two PLLs, that is, a PLL 1 which generates a timing clock for detecting the position of the wobble mark, an address reading and a data reading of the zone 0 and a PLL 2 which generates a timing clock for reading the data of the zones 1 to 3. Both P because it is configured
The oscillation frequency of the CVO in LL can be lowered. For example,
Timing clock frequencies for zone 0, zone 1, zone 2 and zone 3 are 10MHz, 14MHz, 18M
Assuming Hz and 22 MHz, the oscillation frequency of the VCO 210 is 10 MHz in all zones, and the oscillation frequency of the VCO 211 is 14 MHz in zone 1 and 18 MH in zone 2.
For z, zone 3 it may be 22 MHz.

In the above, the case of the reproducing apparatus has been described in the first embodiment, but the same applies to the case of the recording apparatus. Figure 3
A block diagram of the optical recording apparatus of the second embodiment is shown in FIG.
3, constituent elements having the same functions as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

When recording a signal, which will be described in detail later,
The control circuit 301 puts the random access memory (RAM) in the recording pulse generation circuit 302 into a storage state, and thereafter, recording data from the outside is modulated by the modulation circuit 303.
Entered in. The modulation circuit 303 modulates the recording data,
This modulated data is sent to the recording pulse generation circuit 302 together with a data storage clock in the RAM. The recording pulse generation circuit 302 stores the modulation data in the RAM, and sends a storage completion signal to the control circuit 301 when the storage of the predetermined data is completed. Then, the control circuit 301 puts the RAM of the recording pulse generation circuit 302 in the read mode and sends a recording gate signal for recording a signal to a predetermined storage area on the recording medium to the recording pulse generation circuit 302. The recording pulse generation circuit 302 sends a predetermined recording pulse according to the modulation data stored in the RAM to the drive circuit 304. The drive circuit 304 strongly modulates the light source 105 according to the recording pulse and records a signal in a predetermined recording area on the recording medium 101.

The recording pulse generation circuit 302 will be described with reference to FIGS. 4 and 9. FIG. 4 shows the recording pulse generation circuit 3
It is a block diagram of 02. Explaining the relationship between FIG. 3 and FIG. 4, the modulation signal from the modulation circuit 303 is on the line (a),
The data storage clock signal is input to the line (a). Also, it is sent from the control circuit 301,
The R / W signal for switching the RAM 401 of the recording pulse generation circuit 302 between the storage mode and the reproduction mode has a line (D) with a clock for storing data in the RAM 401 and a timing clock for reading data from the RAM 401. A clock switching signal for switching is input to the line (f), and a recording gate signal is input to the line (ki). A storage completion signal indicating that the predetermined modulation data is stored in the RAM 401 from the recording pulse generation circuit 302 is sent from the line (e). Clock selection circuit 12
The timing clock signal from No. 2 is input to the line (K), and the recording pulse signal to the drive circuit 304 that drives the light source is sent from the line (C).

When a signal is recorded on the recording medium 101, the control circuit 301 sets the RAM 401 in line (d).
Is set to the storage mode, and the CK switching circuit 402 is switched so that the data storage clock signal from the modulation circuit 303 is input to the counting circuit 403 by the line (F). After that, the modulation data and the data storage clock signal are sent from the modulation circuit 303 to the recording pulse generation circuit 302. The counting circuit 403 counts the data storage clock signal every moment, and sequentially sends the count value to the RAM 401 and the comparison circuit 404. The RAM 401 stores the modulation data sent from the modulation circuit 303 using the count value of the counting circuit as an address. The comparison circuit 404 is the counting circuit 4
It is detected that the count value of 03 reaches a predetermined value, and the RAM
A storage completion signal indicating that predetermined modulation data is stored in 401 is transmitted to the control circuit 301 from the line (e). When the storage completion signal is input from the comparison circuit 404, the control circuit 301 receives R from the line (D).
The AM 401 is set in the read mode, and the CK switching circuit 402 is switched by the line (f) so that the timing clock signal from the gate circuit A 405 is transmitted to the counting circuit 403. Then, the control circuit 301 searches for a predetermined recording area on the recording medium in which the data stored in the RAM 401 is to be stored, and the recording gate signal for starting recording is shown in FIG. It is sent to the gate circuit A405. Inversion circuit 40
The timing clock signal shown in FIG. 9 (e) selected by the clock selection circuit 122 of FIG. Simultaneously with the recording gate signal, an inverted timing clock signal FIG. 9 (g) is output from the gate circuit A 405, and this timing clock signal is sent to the recording pulse generating circuit 407 and the counting circuit 403 via the CK switching circuit 402. Entered in. The counting circuit 403 is from the gate circuit A405,
The gated and inverted timing clock signal is counted and the count value is sent to the RAM 401 and the comparison circuit 404. The recording pulse generation circuit 407 is a gated and inverted clock signal from the gate circuit A 405. FIG.
A recording clock signal of FIG. 9 (i) having a more predetermined pulse width is generated, and this signal is sent to the gate circuit B 408. On the other hand, the RAM 401 sequentially transfers the data stored in the address corresponding to the count value of the counting circuit 403 to the gate circuit B4.
Send to 08. The gate circuit B 408 is a data signal sent from the RAM 401, FIG. 9 (h) and a recording clock pulse signal, FIG. 9 (i) is a recording pulse signal, and FIG.
(J) is created and sent to the drive circuit 304 by the line (c). The drive circuit 304 strongly modulates the light source according to the recording pulse signal from the gate circuit B 408 and records the signal on the recording medium. The comparator circuit 404 detects that the count value of the counter circuit 403 has reached a predetermined value, and the RAM 401
A recording completion signal indicating that the recording of the data stored in (3) is completed is transmitted to the control circuit 301 from the line (e). When the recording completion signal is input from the comparison circuit 404, the control circuit 301 sets the recording gate signal of line (K) in FIG. 9F to the LOW level to end the recording.

As described above, the detection of the servo area, the reading of the address, and the recording of the data in the zone 0 are performed by the first P.
The timing clock frequency is oscillated in the LL, and the other zones oscillate a timing clock frequency that matches the zone in the second PLL at the time of access,
Since the timing clock frequency has been pulled in until the desired track in the desired zone is accessed, when the desired track is accessed, it is possible to immediately switch to the timing clock for that zone. The conventional problem that the signal cannot be recorded during this period due to the pull-in time of the timing clock generation circuit due to switching can be solved. As described above, the present invention can be applied not only to reproduction only, to recording only, but also to recording and reproduction.

Further, in the first and second embodiments, except for the case where a certain continuous data is continuous from one zone to the next zone, except when the zone 0 is shifted to the zone 1.
At the boundary of the zone, the timing clock may not be pulled in by the PLL circuit only once, but such a probability is small, so that it does not cause much trouble depending on the application.

Next, an optical reproducing apparatus of the third embodiment will be described with reference to FIG. 10 which is a block diagram thereof and FIG. 11 which is a block diagram of a timing clock generating circuit which is a main part thereof. 1 and 2 in FIGS.
The same reference numerals are given to the constituent elements having the same functions as, and detailed description thereof will be omitted. In the first and second embodiments, in the timing clock generation circuit, one block has both the detection of the servo area and the reading of the address, as well as the generation of the timing clock for the zone 0 and the gate operation. In this embodiment, the block for performing timing clock generation and gate operation for detecting the servo area and address reading and the block for performing timing clock generation and gate operation for zones 0 to 3 are separated. There is.

In FIG. 10, reference numeral 1001 is a timing clock generation circuit, and 1002 is a control circuit. Further, in FIG. 11, the phase comparator 200, the VCO 210, and the frequency divider 220 form a PLL1 which is the first timing clock generating means, and this, the counting circuit 230 which is the first counting means, and the first decoding means. A decoder C24
The 0 and the AND circuit 250 form one block, and are dedicated to timing clock generation and gate operation for detecting a servo area and reading an address.

Further, the phase comparator 201, VCO 211 and frequency divider 221 form a PLL2 which is a second timing clock generating means, and this and a counting circuit 231 which is a second counting means and a second decoding means. A decoder D24
1 and AND circuit 251 form one block, and this portion performs timing clock generation and gate operation for zones 0 to 3. Decoder A24
2, the decoder B243 has the first and second decoders as in the case of FIG.
To make a gate for servo mark detection.

The operation of the above configuration will be described. The control circuit 1002 causes the VCO 211 to generate a timing clock having a frequency suitable for the zone of the track where the light beam is located based on the address read by the address reading circuit 120. Frequency divider 2 to do
21 and controls the gate period of the decoder D241 depending on how many counts of the counting circuit 231 are taken.
A timing clock signal having a predetermined gate period is sent to the data reading circuit 123 by 51.

Further, when trying to access a desired track in a desired zone, the control circuit 1002 controls the frequency divider 221 to set a timing clock frequency in the PLL 2 including the frequency divider 221 which is suitable for the desired zone. Decoder D241 is determined depending on how many counts of counting circuit 231 are taken when the desired track is accessed.
, And sends a timing clock signal to the data reading circuit 123 for a predetermined gate period by the AND circuit 251. In this embodiment as described above, the process for accessing a desired track in a desired zone from a certain zone is the same as that in the first embodiment.

In the third embodiment, only the case of reproduction is explained, but
The same applies to the case of recording. As described above, in the third embodiment, in the timing clock generation circuit, a block that performs timing clock generation and gate operation for detecting a servo area and address reading, and a timing clock generation and generation block for zones 0 to 3 are provided. Since the block for performing the gate operation is separated, the oscillation frequency of the VCO can be lowered and the circuit structure can be simplified.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to the embodiments. For example, in the present invention, the track can be formed in a spiral shape as well as the concentric shape. Although the number of zones has been described as 4, the number may be increased or decreased as necessary. Further, the positional relationship between the wobble mark and the clock mark is not limited to the example shown. Further, different timing clocks can be used for wobble mark position detection and address reading.

[0057]

As described above, the optical recording / reproducing apparatus of the present invention reproduces the synchronizing signal from the clock mark of the recording medium, and at least the servo area is detected and the address is read based on the synchronizing signal. First timing clock generating means for generating a timing clock of a first frequency for adapting to a specific recording zone if necessary;
On the other hand, by providing a second timing clock generating means for generating a timing clock of one or more kinds of frequencies suitable for a desired recording zone of the recording medium in accordance with an instruction from the control means on the basis of the synchronizing signal, the desired zone is desired. Before accessing the track, generate a timing clock that is suitable for that zone and stabilize it, and when you access it, you can immediately switch to a timing clock that matches that zone. for,
There is no problem that the signal cannot be reproduced or recorded during this period, the signal can be reproduced or recorded immediately, and the frequency of the timing clock can be lowered, so that an effective effect that the circuit can be made simple and inexpensive can be obtained. .

[Brief description of drawings]

FIG. 1 is a block diagram of an optical reproducing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of the timing clock generation circuit and the clock selection circuit of the same.

FIG. 3 is a block diagram of the optical recording / reproducing apparatus of the second embodiment.

FIG. 4 is a block diagram of the recording pulse generation circuit of the same.

FIG. 5 is a schematic diagram of a recording medium and an operation waveform diagram of each part of the circuit in the first embodiment of the present invention.

FIG. 6 is a schematic diagram of an arrangement state of recording data on the recording medium.

FIG. 7 is a schematic diagram of a recording state of a servo area and an address area.

FIG. 8 is a schematic diagram of a recording medium and an operation waveform diagram of each circuit portion in a plurality of zones.

FIG. 9 is a schematic diagram of a recording medium according to a second embodiment of the present invention and an operation waveform diagram of each circuit portion during recording.

FIG. 10 is a block diagram of an optical reproducing apparatus according to the third embodiment of the same.

FIG. 11 is a block diagram of the timing clock generation circuit of the same.

FIG. 12 is a block diagram of a tracking error detector according to the first embodiment of the present invention.

FIG. 13 is a recording area layout diagram of a recording medium common to a conventional example and an example of the present invention.

[Explanation of symbols]

 101 recording medium 111 photodetector 114 I / V converter 115 tracking error detector 117 CK mark detection circuit 118 binarization circuit 119 timing clock generation circuit 120 address reading circuit 121 control circuit 122 clock selection circuit 123 data reading circuit 200, 201 phase comparator 210, 211 VCO 220, 221 frequency divider 230, 231 counting circuit 240 decoder C 241 decoder D 242 decoder A 243 decoder B 250, 251, 260, 261 AND circuit 270 OR circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Yamada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (6)

[Claims] 1. A plurality of clock marks for synchronization and an address for identifying a position are provided per circle on a spiral or concentric circular track rotated at a constant angular velocity, and the clock marks are adjacent to each other. It is arranged so that the track connecting it with the track is radial to the center,
The addresses are recorded on all tracks so as to be reproduced at the same timing clock in synchronization with the clock marks, and the information area divided into at least two zones in the radial direction has an information amount per circle. A device for irradiating a light beam onto a recording medium capable of accumulating information so that the outer zone is larger than the inner zone and recording the information, or reproducing the recorded information. Conversion means for converting the information recorded on the medium into an electric signal; synchronization signal detection means for detecting a synchronization signal corresponding to the clock mark from the signal of the conversion means; and detection by the synchronization signal detection means Timing of a first frequency for recording information in a specific zone on a recording medium based on a synchronization signal or reading the recorded information First timing clock generating means for generating a lock, and address reading for reading the address recorded on the recording medium by judging the signal of the converting means based on the timing clock from the first timing clock generating means A circuit, and second timing clock generation means capable of generating a timing clock of one or more frequencies synchronized with the synchronizing signal for recording information on a recording medium or reading recorded information, The zone in which the light beam on the recording medium is located is determined based on the address read by the address reading circuit, and the output of the first timing clock generating means is selected, or the frequency of the frequency matching the zone is selected. The second timing clock generator for generating the timing clock Optical recording and reproducing apparatus comprising a control means for instructing to determine whether to select it. 2. The control means, when searching for a desired track based on the address read by the address reading circuit, judges which recording zone the desired track is, and the control means of the first timing clock generating means. 2. An optical system according to claim 1, wherein the output is selected or the second timing clock generating means is instructed to generate a timing clock having a frequency matching the zone of the desired track to determine whether to select it. Recording / playback device. 3. A plurality of synchronizing clock marks and a pair of wobble marks are provided per circle on a spiral or concentric track which is rotated at a constant angular velocity, and clock marks, clock marks, and wobbles of adjacent tracks are provided. The traces connecting the marks and the wobble marks are arranged so as to be radial with respect to the center, and the pair of wobble marks are equidistantly spaced from each other outward and inward with respect to the track center line, and The information areas, which are spaced apart in the track direction and are divided into at least two zones in the radial direction, accumulate information so that the amount of information per circle is larger in the outer zone than in the inner zone. A device for irradiating a light beam onto a recording medium to record information or reproducing recorded information, which is recorded on the recording medium. Based on the synchronization signal detected by the synchronization signal detection means, the conversion means for converting the information into an electric signal, the synchronization signal detection means for detecting the synchronization signal corresponding to the clock mark from the signal of the conversion means, First timing clock generating means for generating a timing clock of a first frequency for recording information in a specific zone on a recording medium or reading recorded information; and the first timing clock generating means. Period signal generating means for generating a period signal corresponding to each position of the pair of wobble marks based on the timing clock of the pair, and a peak value of each of the pair of wobble marks based on the period signal of the period signal generating means. And a pair of wobble marks of the pair of wobble marks from the peak detection means. Tracking control means for controlling the light beam on the recording medium to be positioned on the track center line according to the difference in value; and the synchronization signal for recording information on the recording medium or reading the recorded information. An optical reproducing apparatus comprising: a second timing clock generating means capable of generating a timing clock having one or more frequencies based on the above. 4. A plurality of clock marks for synchronization and an address for identifying a position are provided per circle on a spiral or concentric track rotated at a constant angular velocity, and the clock marks are adjacent to each other. It is arranged so that the track connecting it with the track is radial to the center,
The addresses are recorded on all tracks so as to be reproduced at the same timing clock in synchronization with the clock marks, and the information area divided into at least two zones in the radial direction has an information amount per circle. A device for irradiating a light beam onto a recording medium capable of accumulating information so that the outer zone is larger than the inner zone and recording the information, or reproducing the recorded information. Conversion means for converting information recorded on the medium into an electric signal; synchronization signal detection means for detecting a synchronization signal corresponding to the clock mark from the signal of the conversion means; and a first synchronization with the synchronization signal. A first timing clock generating means for generating a timing clock of a frequency; and a timing clock from the first timing clock generating means. Address reading circuit for reading the address recorded on the recording medium by judging the signal of the converting means based on the clock, and for recording the information on the recording medium or reading the recorded information. Second timing clock generation means capable of generating timing clocks of a plurality of frequencies synchronized with the synchronization signal, and determining the zone where the light beam on the recording medium is located based on the address read by the address reading circuit. An optical recording / reproducing apparatus comprising: control means for instructing the second timing clock generating means to generate a timing clock having a frequency suitable for the zone. 5. The control means, when searching for a desired track based on the address read by the address reading circuit, determines which recording zone the desired track is and matches the zone of the desired track. The optical recording / reproducing apparatus according to claim 4, wherein the second timing clock generating means is instructed to generate a timing clock of a frequency. 6. A plurality of clock marks for synchronization and a pair of wobble marks are provided per circle on a spiral or concentric track that is rotated at a constant angular velocity, and clock marks, clock marks, and wobbles of adjacent tracks are provided. The traces connecting the marks and the wobble marks are arranged so as to be radial with respect to the center, and the pair of wobble marks are spaced equidistantly from each other outward and inward with respect to the track center line, and the tracks are mutually tracked. The information areas, which are spaced apart in the direction and are divided into at least two zones in the radial direction, can store information such that the amount of information per circle is larger in the outer zone than in the inner zone. A device for irradiating a recording medium with a light beam to record information or reproducing recorded information, which is recorded on the recording medium. Based on the synchronization signal detected by the synchronization signal detection means, a conversion means for converting the information that is present into an electrical signal, a synchronization signal detection means for detecting a synchronization signal corresponding to the clock mark from the signal of the conversion means, A first timing clock generating means for generating a timing clock having a frequency of 1; and a period for generating a period signal corresponding to each position of the pair of wobble marks based on the timing clock of the first timing clock generating means. Signal generating means, peak detecting means for detecting respective peak values of the pair of wobble marks based on the period signal of the period signal generating means, and both peak values of the pair of wobble marks from the peak detecting means. The track that controls the light beam on the recording medium to be located on the track center line according to the difference. And a second timing clock generation means capable of generating timing clocks of a plurality of frequencies based on the synchronization signal for recording information on the recording medium or reading the recorded information. Optical playback device.