JPH06150323A - Optical recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a means capable of recording and reproducing a signal quickly by solving the problem that at the time of recording or reproducing to a recording medium with a converged light beam, the recording or reproduc ing of a signal cannot the performed during a pull-in time due to the switching of a timing clock at the time of a zone switching. CONSTITUTION:A reflected light from a recording medium 101 is converted to a current by an optical detector 111 and made to be a voltage form by an I/V converter 114 and binarized by a binarization circuit 118, and at the same time, a synchronous signal is detected in a CK mark detecting circuit 117, timing clocks having defferent timing at every zone of the recording medium are oscillated in advance in a timing clock generation circuit 119. Then, a zone where data to be reproduced are stored, is detected in an address read- out circuit 120 and the control circuit 119 is constituted so that the timing clock matched with the zone and a perscribed gate period are selected with a clock selection circuit 122.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical recording / reproducing apparatus for recording / reproducing information on / from a recording medium by means of a focused light beam. More specifically, the recording system for recording medium is of a sample format type. Regarding

[0002]

2. Description of the Related Art In recent years, an optical recording / reproducing apparatus holds a large amount of data in a recording medium and can reproduce it, so that it occupies an important position in recording and reproducing audio information data, video information data, and various information equipment data. ing.

FIG. 12 shows a recording state on a recording medium of a sample format type in a conventional optical recording / reproducing apparatus. In FIG. 12, 1201 is a substrate of the recording medium,
For example, it is formed of a resin such as polycarbonate having a thickness of 1.2 mm, and tracking marks (also referred to as tracking pits) 1205 and 1206, which are also called wobble marks, and clock marks (also referred to as clock pits) 1207, which are also called wobble marks, are injected on one surface. And the like. This wobble mark 1205,120
Servo area 1 consisting of 6 and clock mark 1207
203 is formed radially from the center of the recording medium substrate 1201 and is slightly displaced (for example, 1/4 track pitch) on both sides of each track indicated by the chain line 1204 for tracking servo. Wobble marks 1205 and 1206 are arranged, and subsequently, a clock mark 1207 for clock reading is provided on the track center line 1204. Then, between the servo areas 1203, the information areas 1 are also radially formed.
208 is formed. And Te on the surface
A recording thin film 1202 made of a phase change recording material containing (tellurium) as a main component is formed by a method such as sputtering.

As a premise, since the recording medium of the sample format type rotates at a constant angular velocity, in order to effectively use such a radial information area 1208, information recording of the information area 1208 portion between the servo areas 1203 is performed. The density should be closer to the outer circumference. For example, the surface of the recording / reproducing material 1202 is concentrically divided into four zones (zones 0 to 3). For example, one information area of zone 0 has 10 bytes, zone 1 has 14 bytes, and zone 2 has 18 bytes. The information density in the bytes and zone 3 is 22 bytes, and the information density is increased toward the outer circumference.

[0005]

However, in the conventional optical recording / reproducing apparatus, in order to make the information density of the recording medium closer to the outer periphery, the timing clock frequency for reading or writing the information is different for each zone. On the other hand, since the timing clock frequency needs to be increased toward the outer circumference, a PLL circuit normally used as a timing clock generation circuit requires a pull-in time of 3 to 5 mS when switching the timing clock frequency. There was a problem that it could not be done.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an optical recording / reproducing apparatus which solves the above-mentioned conventional problems and can continuously record or reproduce signals.

[0007]

In order to achieve this object, an optical recording / reproducing apparatus of the present invention comprises a sync signal reproducing means for reproducing a sync signal from a clock mark of a recording medium,
A plurality of timing clock generating means for generating timing clocks of different frequencies based on the synchronization signal, a counting means for counting the timing clocks of the respective timing clock generating means, and a count value of the counting means for receiving the count value. Decoder means for opening the gate only between different specific counts determined for a plurality of recording zones of the recording medium, control means for checking the address of the recording medium to determine which recording zone it is, and the control means Under the control of the clock zone selecting means for selecting one of the outputs of the plurality of timing clock generating means and the gate period of the decoding means in correspondence with the recording zone. It is divided into multiple zones in the radial direction, and each zone can be recorded. The number of data are recorded differently.

[0008]

According to the present invention, in the above construction, a timing clock generating means for reproducing a synchronizing signal from a clock mark of a recording medium and generating a timing clock having a frequency corresponding to each of a plurality of recording zones on the basis of the synchronizing signal. Are prepared for the number of zones of the recording medium, at the time of recording or reproduction, the address of the recording medium is confirmed, and which recording zone is determined by the control means,
The control means selects the timing clock generating means corresponding to the recording zone by using the clock selecting means, counts the timing clock by the counting means, and opens the gate means only during a specific count corresponding to the zone. It will act to control.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An optical recording / reproducing apparatus according to embodiments of the present invention will be described below with reference to the drawings. First of the present invention
1 of the block diagram showing the embodiment, the phase change type recording medium 101 is attached to the rotation shaft of the motor 102 and rotated at a predetermined angular velocity. Inside the transfer table 104, a light source 105 such as a semiconductor laser, a coupling lens 106, a polarization beam splitter 107, a quarter wavelength plate 1
08, a total reflection mirror 109, a photodetector 111, and a fixed portion (not shown) of the actuator 112 are attached, and the transfer table 104 is moved in the radial direction of the recording medium 101 by a transfer motor 103 such as a linear motor. It is configured to move.

The light beam generated by the light source 105 is converted into parallel light by the coupling lens 106 and then polarized by the beam.
The light passes through the beam splitter 107 and the quarter-wave plate 108, is reflected by the total reflection mirror 109, and is focused and irradiated on the recording medium 101 by the focusing lens 110. The reflected light reflected by the recording medium 101 passes through the focusing lens 110, is reflected by the total reflection mirror 109, passes through the quarter-wave plate 108, is reflected by the polarization beam splitter 107, and is detected by the photodetector 111. Irradiated on. The focusing lens 110 is attached to the movable part of the actuator 112. The actuator 112 is composed of a tracking coil 113 provided in the movable part and a permanent magnet (not shown) attached to the fixed part. Therefore, when a current is passed through the tracking coil 113, the focusing lens 110 moves in the radial direction of the recording medium 101, that is, across the track on the recording medium 101 (left and right in the figure) by the electromagnetic force received by the coil. To do.

A coil (not shown) for a focus is also attached to the movable part of the actuator 112, and when a current is passed through this coil, an electromagnetic force is received by the coil from a permanent magnet (not shown). The focusing lens 110 is configured to be movable in a direction perpendicular to the surface of the recording medium 101. The focusing lens 110 is used as the recording medium 1.
Focusing control is performed so that the light beam radiated on 01 is always in a predetermined focusing state.

The output of the photodetector 111 is input to an I / V converter 114 that converts a current into a voltage, and the photodetector 111 is output.
Output current is converted to voltage and output. I / V converter 1
One of the output signals of 14 is the tracking error detector 11
5, the tracking error detector 115 detects the tracking error from the position of the focused light with respect to the wobble mark shown in FIG. The tracking error signal of the tracking error detector 115 is applied to the actuator 112 via the control circuit 116, and the actuator
Tracking control is performed on the data 112 so that the light beam on the recording medium 101 is positioned between the wobble marks 1205 and 1206, that is, on the track center.

The output signal of the I / V converter 114 is C
It is input to the K mark detection circuit 117 and the binarization circuit 118. The binarization circuit 118 binarizes the output signal of the I / V converter 114, and sends this binarized signal FIG. 5C to the CK mark detection circuit 117. The interval between the second tracking mark and the clock mark in FIG. 5A has a unique distance of t as shown in FIG. 5C, and this time interval is configured not to occur in other parts. By utilizing this fact, the CK mark detection circuit 117 detects the clock mark position and differentiates the waveform of the clock mark portion of FIG. 5B to obtain the synchronization signal of FIG. 5D.
Is output. The timing clock generation circuit 119 generates a timing clock in accordance with the zone of the recording medium on the basis of this synchronization signal and gives a gate output to each section. This will be described in detail later. The address reading circuit 120 is inputted with the binarized signal of the binarizing circuit 118 and the timing clock for the zone 0 of the outputs of the timing clock generating circuit 119. Address reading circuit 1
20 reads the address on the recording medium from the binarized signal based on the timing clock, and sends the read address to the control circuit 121.

The search for the desired track will be briefly described. When the address of a desired track is input to the control circuit 121, the control circuit 121 controls the clock selection circuit 122 to select the clock frequency corresponding to the zone corresponding to the address position, and the address read circuit 120 sends it. The address of the track where the optical beam on the recording medium 101 is located is read from the address that comes in and the distance to the desired track is calculated.
If the calculated distance exceeds the predetermined range, the tracking control is disabled and the transfer motor 103
Is driven to move the transfer table 104 in the radial direction of the recording medium 101, the arrival of the vicinity of a desired track is detected, the tracking control is operated again, and recording is performed from the address sent from the address reading circuit 120. Medium 101
The address of the track on which the upper optical beam is located is read and the distance to the desired track is calculated. When the calculated distance exceeds the predetermined range, the sparse search described above is performed again, and when it is within the predetermined range, the actuator 112 is driven to perform the fine search by jumping one by one. After that, the address is read again, and if the read address matches the address of the desired track, the search is ended, and if it does not match, the above-described search operation is repeated to search for the desired track. Data reading circuit 12
3 includes a signal of the binarization circuit 118 and a clock selection circuit 12
Since the clock selection circuit 122 outputs the clock frequency corresponding to the zone corresponding to the desired track position when the search signal has been input, the data reading circuit 123 outputs the data reading circuit 123 from the clock selection circuit 122. The data in the required data area can be read in synchronization with the clock that is sent.

Before going into the detailed description of the operation, it will be explained how the data on the recording medium is arranged. FIG. 8 conceptually shows the format on the recording medium. As shown in FIG. 8A, servo areas and information areas are alternately arranged on the tracks on the recording medium. And the information area form one block. Then, as shown in FIG. 8B, one sector is composed of (n + 1) blocks and has an address area for recording an address for identifying the position of the sector in the information area of the first block of the sector. , The data is recorded in the information area of the n blocks following it. Next, FIG.
As shown in (c), one track in a certain zone is composed of m sectors, and when one track cannot be divided by one sector length, a surplus area is provided at the end of the track.

Next, the timing clock generation circuit 11
9 and details of the clock selection circuit 122;
The mark on the recording medium and the waveform of each part of the circuit will be described together with FIG. In FIG. 2, the phase comparator 200 is for zone 0, and the phase comparators 201, 202 and 203 are for zones 1, 2, and 3, respectively. Hereinafter, VCO (voltage controlled ocsilator) 210
-213, frequency dividers 220-223, counting circuits 230-2
33, decoders 240 to 243, AND circuits 250 to 2
53, AND circuits 260 to 60 in the clock selection circuit 122
263 has a similar combination. The decoder A 254 and the decoder B 255 create timings for detecting the first and second servo marks. The control circuit 122 sends a signal for selecting a clock to the OR circuit 270, and the OR circuit 270 causes the AND circuits 260-2.
One clock selected from 63 clock outputs is output and sent to the data reading circuit 123.

FIG. 5A is a diagram schematically showing the arrangement of marks (pits) on the recording medium. The first and second tracking marks are located above and below the center line (dotted line). They are deviated, and so-called wobble marks are formed.
FIG. 5B shows an output pulse waveform of the I / V converter 114,
The binarization circuit 118 binarizes the signal as shown in FIG. The time interval t between the second tracking mark and the clock mark is called a so-called unique distance, and the mark interval is arranged so that this interval t cannot appear in other parts. In the CK mark detection circuit 117, paying attention to this time t, the pulse after this interval is detected as a synchronization signal and the signal shown in FIG. 5D is output. This output is applied to each of the phase comparators 200 to 203 of the timing clock generation circuit 119. In the circuit of the four zones shown in the figure, the zone 0 will be described.
0, VCO 210, frequency divider 220 PLL
The (phase locked loop) circuit outputs the timing clock of FIG. 5 (f) from the VCO 210. This is synchronized with the phase of the timing clock by the frequency divider 220, and the waveform of FIG. 5 (e) is generated at the position of the synchronization signal, and the reset counting circuit 230 counts the number of data in the information area of zone 0. As shown in the waveform of FIG. 5 (i), the decoder C240 determines how many gates of the counting circuit 230 the gate is opened, and outputs the output from the AND circuit 250 of the VCO output of FIG. 5 (f).
Output to.

The phase comparator 200, the VCO 210, and the frequency divider 220 constitute a first timing clock generating means. In this embodiment, the timing clock generating means is 4
Individually shown. This number corresponds to the number of zones on the recording medium and is not limited to four. The counting circuit 230 and the decoder C240 are subordinate to the set of the phase comparator 200, the VCO 210, and the frequency divider 220 which are the first timing clock generating means. In the first embodiment, four such dependency relationships are provided.

In this case, in the example shown in FIG. 12, in the zone 0, the counting circuit 230 detects that the information area is completed by counting 10 bytes, that is, 80 pulses, but in FIG. It is shown as finished. Decoder A244, Decoder B2
Output waveforms 45 of FIGS. 5 (g) and 5 (h) are given to the tracking error detection circuit 115 as gates for detecting the first and second tracking marks.
The peak value of each output waveform of the second tracking mark is detected, and the difference between both peak values is detected by a differential amplifier (not shown).
Control circuit 11 so that both waveforms are at the same level.
Controlling the actuator 112 via the recording medium 1
The tracking control is performed so that the optical beam focused on 01 is always located on the track. In addition, the control circuit 1
16 is added to the transfer motor 103, and the focusing lens 11
The transfer table 104 is transferred and controlled so that 0 moves in the radial direction of the recording medium around the natural state. Waveform (i) in Figure 5
In this figure, the decoder C240 opens the gate so that the timing pulse after the output of the clock mark becomes high at the falling edge of the first clock of FIG. 5 (f) and becomes low at the falling edge of the eleventh clock. Describes that it operates so as to detect 10 pulses in the information area.

Next, as shown in FIG. 12, the servo areas 1203 are radially arranged on the recording medium 1201. As described above, since the recording medium of the sample format format rotates at a constant angular velocity as described above, the number of wobble marks and clock marks on all tracks is the same, and the time interval between marks when reproduced is large. Are also arranged to be the same. This is to speed up track access and signal recording / reproduction. That is, in the present invention, the clock mark 120
Reference numeral 7 serves as a reference for obtaining a synchronization signal for accurately recording or reproducing a signal near the center of the track, and it is desirable that this can always be identified. If the clock marks 1207 are present in different tracks for each track, the pull-in operation for extracting the sync signal must be performed each time the desired track is accessed. For example,
When jumping from one track to another, clock mark 1 on the jump destination track
207 and clock mark 1207 on the original track
If there is a difference in phase or frequency between the two, the new track will be out of synchronization, and it will take some time before the synchronization takes place again, and there will be a problem that the recording / reproducing of the signal cannot be executed immediately after the end of the track jump. Therefore, the clock marks 1207 are arranged so as to have the same phase over all tracks.

FIG. 6 shows the time intervals of the address data when the address area provided at the head of each sector on the track for data access is reproduced.
As with the servo area, the address area also
The reproduction frequencies of the marks are the same for the same reason as above.

However, when the servo areas are arranged in this manner, the distance between the servo areas becomes wider toward the outer circumference, and if the number of recordable bits in the data areas between the servo areas is the same on the inner and outer circumferences, the data bits are inevitably divided. The interval becomes wider toward the outer circumference, and the amount of data decreases.

For the above reasons, in the present embodiment, the number of recordable bits in the data area on the outer periphery of the recording medium is increased so that the space between the data in the data area is substantially constant. Then, the clock frequency for data reproduction in the data area inevitably becomes higher in the outer zone.

Therefore, it is necessary to increase the timing clock frequency in the outer peripheral zone. In this embodiment, the output frequency of the PLL is set higher toward the outer zone of the recording medium. For example, in FIG. 7, V in zone 3
The CO output is higher than that of zone 0. Therefore, when data is being read in zone 0, the AND circuit 260 is controlled by the control circuit 121.
The data reading circuit 123 reads the data from the data reading circuit 123 by outputting the range of the gate opened by the decoder C240 from the OR circuit 270 at the oscillating frequency of the VCO 210 in the zone 0. In this case, since the clock of zone 0 is always supplied to the address reading circuit 120, the address area of the target track is searched by this clock frequency, and when the address can be accessed, the control circuit 121 immediately causes the AND circuit. VCO in Zone 3 by 263
213 is the frequency oscillating and the decoder F24
The gate range opened at 3 is output from the OR circuit 270, and the data reading circuit 123 reads the desired data in the zone 3. Moreover, as described above, the clock mark positions in each zone are in phase, so when reproducing any zone, the sync signals in the other zones are also in phase, and based on this sync signal, The timing clock is generated in a cycle required for each zone, and the timing clock adapted to the zone can be supplied immediately upon the zone switching.

As described above, in this embodiment, the different timing clock frequencies for the respective zones are used for the dedicated PLs.
When the target track of the target zone is accessed by oscillating in advance at L, the timing clock of the zone can be immediately switched. Therefore, due to the pull-in time of the timing clock generation circuit by the timing clock switching, It is possible to solve the conventional problem that the signal cannot be reproduced.

Next, a second embodiment of the present invention will be described with reference to FIG.
And it demonstrates using the block diagram of FIG. This is a simplification of the circuits of FIGS. 1 and 2, and parts having the same functions as those of FIGS. 1 and 2 are designated by the same reference numerals and the description thereof will be omitted. Figure 3
In FIG. 4, the timing clock generation circuit 301, the clock selection circuit 302 and the control circuit 303 are different from those of the first embodiment, and the decoders D, E and F of FIG. 1 are omitted in FIG.
401 is added. The clock selection circuit 302 includes
It also has a count value switching circuit 402, a clock switching circuit 403, and an AND circuit 404.

In this configuration, the control circuit 30
When accessing the data of a certain zone, 2 controls the clock switching circuit 403 to select the output of the PLL generating the clock suitable for the zone and output it to the AND circuit 404, and also the count value switching. The circuit 402 is controlled to select a count value suitable for the zone to select the decoder G.
401 to output the gate period of the decoder G401,
It may be controlled so as to fit the zone being accessed. For further simplification, the counting circuit may be 230 dedicated to zone 0 and the ones for other zones, and the decoder G401 may have the function of the count value switching circuit 402. In this case, it is necessary to devise the switching of the count value by resetting with the clock mark and counting immediately after that.

As described above, also in the second embodiment, different timing clock frequencies for each zone are oscillated in advance by dedicated PLLs, and when the target track of the target zone is accessed, the zone is immediately The same effect as that of the first embodiment can be obtained in that the timing clock can be switched to.

The case of the reproducing apparatus has been described above in the first and second embodiments, but the same applies to the case of the recording apparatus. FIG. 9 shows a block diagram of the recording apparatus of the third embodiment. 9, those having the same functions as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

When recording a signal, which will be described in detail later,
The control circuit 901 puts the random access memory (RAM) in the recording pulse generation circuit 902 into a storage state, and then the recording data from the outside is modulated by the modulation circuit 903.
Entered in. The modulation circuit 903 modulates the recording data,
This modulated data is sent to the recording pulse generation circuit 902. The recording pulse generation circuit 902 stores the modulation data in the RAM, and sends a storage completion signal to the control circuit 901 when the storage of the predetermined data is completed. Then, the control circuit 901 puts the RAM of the recording pulse generation circuit 902 in the read mode and sends a recording gate signal for recording a signal to a predetermined storage area on the recording medium to the recording pulse generation circuit 902. The recording pulse generation circuit 902 sends a predetermined recording pulse according to the modulation data stored in the RAM to the drive circuit 904. The drive circuit 904 strongly modulates the light source 105 according to the recording pulse, and the recording medium 1
The signal is recorded in a predetermined recording area on 01.

Recording pulse generation circuit 902 is shown in FIG.
Will be described with reference to FIG. FIG. 10 is a block diagram of the recording pulse generation circuit 902. Explaining the relationship between FIG. 9 and FIG. 10, the modulation signal from the modulation circuit 903 is input to the line (a), and the data storage clock signal is input to the line (a). The R / W signal sent from the control circuit 901 for switching the RAM 1001 of the recording pulse generation circuit 902 between the storage mode and the reproduction mode is in line (d), and the clock for storing data in the RAM 1001 and the RAM 1001. The clock switching signal for switching the timing clock for reading the data is input to the line (f), and the recording gate signal is input to the line (ki). R from the recording pulse generation circuit 902
A storage completion signal indicating that the predetermined modulation data has been stored in the AM 1001 is transmitted from the line (e). The timing clock signal from the clock selection circuit 122 is input to the line (H) and the drive circuit 90 that drives the light source.
The recording pulse signal to 4 is transmitted from the line (c).

When recording a signal, the control circuit 9
01 sets the RAM 1001 in the storage mode, and switches the CK switching circuit 1002 so that the data storage clock signal from the modulation circuit 903 is input to the counting circuit 1003. Then, the modulation circuit 903 outputs the modulated data and the data storage clock signal to the recording pulse generation circuit 902.
Will be sent to. The counting circuit 1003 counts the data storage clock signal every moment, and the count value is stored in the RAM 100.
1 and the comparison circuit 1004 sequentially. RAM1001
Stores the modulation data sent from the modulation circuit 903 using the count value of the counting circuit as an address. Comparison circuit 100
Reference numeral 4 denotes a control circuit 901 which detects that the count value of the counting circuit 1003 has reached a predetermined value and outputs a storage completion signal indicating that the RAM 1001 has stored predetermined modulation data.
Communicate to. The control circuit 901 is the comparison circuit 100.
4 receives the storage completion signal, the RAM 1001 is set to the read mode and the gate circuit A10 is set.
The timing clock signal from 05 is the counting circuit 1003.
The CK switching circuit 1002 is switched so as to be transmitted to. The control circuit 901 is the RAM 100.
The recording gate signal for searching a predetermined recording area on the recording medium where the data stored in 1 is to be stored and starting recording is sent to the gate circuit A 1005. The inverting circuit 1006 includes the clock selection circuit 12 of FIG.
11 (e), which is a gated timing clock signal selected from No. 2, is input to the inverting circuit 1006.
Inverts the input signal and sends the inverted signal to the gate circuit A1005. A timing clock signal shown in FIG. 11 (g) is output from the gate circuit A1005 at the same time as the recording gate signal.
CK switching circuit 1002
Is input to the counting circuit 1003 via. Counting circuit 10
03 counts the gated and inverted timing clock signal from the gate circuit A 1005, and counts the counted value in the RAM 1
001 and the comparison circuit 1004. The recording pulse generation circuit 1007 generates a recording clock signal of FIG. 11 (i) having a predetermined pulse width from the clock signal from the gate circuit A1005 (FIG. 11 (g)), and outputs this signal to the gate circuit B1.
Send to 008. On the other hand, the RAM 1001 sequentially sends the data stored in the address corresponding to the count value of the counting circuit to the gate circuit B1008. The gate circuit B1008 is R
A recording pulse signal (FIG. 11 (j)) is created from the data signal sent from the AM 1001 and the recording clock pulse signal (FIG. 11 (i)) and sent to the drive circuit 904. The signal is recorded on the recording medium by modulating the intensity of the light source according to the recording pulse signal.

As described above, the number of recording data in each recording area varies depending on the zone to be recorded on the recording medium.
The control circuit 901 determines the number of data to be recorded in the RAM accordingly, and operates with the timing clock of the zone 0 until the target track of the target zone is accessed. It is sufficient to switch to the gate time instantly for recording. As described above, the present invention can be applied not only to reproduction only, to recording only, but also to recording and reproduction.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments. For example, in the present invention, the track can be formed in a spiral shape as well as the concentric shape. Although the number of zones has been described as 4, the number may be increased or decreased as necessary.

[0035]

As described above, in the optical recording / reproducing apparatus of the present invention, a plurality of timing clock frequencies different for each zone of the recording medium are oscillated in advance by a plurality of dedicated timing clock generating means. Every time the target track of the target zone is accessed, the timing clock of that zone can be immediately switched, so there is a problem that signal reproduction or recording cannot be performed during this time due to the pull-in time due to the timing clock switching. Therefore, it is possible to obtain an effective effect that the signal can be reproduced or recorded immediately.

[Brief description of drawings]

FIG. 1 is a block diagram of an optical reproducing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of the same timing clock generation circuit.

FIG. 3 is a block diagram of an optical reproducing apparatus of the second embodiment as well.

FIG. 4 is a block diagram of the timing clock generation circuit of the same.

FIG. 5 is a schematic diagram of a recording medium and an operation waveform diagram of each part of the circuit in the first embodiment of the present invention.

FIG. 6 is a schematic diagram of a recording state of a servo area and an address area.

FIG. 7 is a schematic diagram of a recording medium in a plurality of zones and an operation waveform diagram of each part of the circuit.

FIG. 8 is a schematic diagram of an arrangement state of recording data on the recording medium.

FIG. 9 is a block diagram of the optical recording / reproducing apparatus of the third embodiment.

FIG. 10 is a block diagram of the same recording pulse generator.

FIG. 11 is a schematic diagram of the recording medium and an operation waveform diagram of each part of the circuit.

FIG. 12 is a recording area layout diagram of a recording medium common to a conventional example and an example of the present invention.

[Explanation of symbols]

101 recording medium 111 photodetector 114 I / V converter 115 tracking error detector 117 CK mark detection circuit 118 binarization circuit 119 timing clock generation circuit 120 address reading circuit 121 control circuit 122 clock selection circuit 123 data reading circuit 200, 201, 202, 203 Phase comparator 210, 211, 212, 213 VCO 220, 221, 222, 223 Frequency divider 230, 231, 232, 233 Counting circuit 240 Decoder C 241 Decoder D 242 Decoder E 243 Decoder F 244 Decoder A 245 Decoder B 250,251,252,253,260,261,2
62,263 AND circuit 270 OR circuit

Claims (4)

[Claims] 1. A sync signal reproducing means for reproducing a sync signal from a clock mark of a recording medium, and the sync signal as a reference.
A plurality of timing clock generating means for generating timing clocks of different frequencies, a counting means for counting the timing clocks of the respective timing clock generating means, and a plurality of recording zones of the recording medium for receiving the count values of the counting means. Decoder means for opening the gate only between different specific counts determined for each, control means for confirming the address of the recording medium to determine which recording zone, and the recording zone by the control of the control means. An optical recording / reproducing apparatus correspondingly provided with a clock selecting means for selecting one of outputs of the plurality of timing clock generating means and a gate period of the decoding means. 2. The optical recording / reproducing apparatus according to claim 1, wherein the recording medium is divided into a plurality of zones in the radial direction, and recording is performed so that the number of recordable data is different for each zone. 3. An address read circuit is operated, which is dependent on a specific timing clock generating means, counts the timing clock, and uses the output of the decoder means for opening the gate only for a specific count. Item 1. The optical recording / reproducing device according to item 1. 4. An optical recording / reproducing apparatus according to claim 3, further comprising decoder means for counting a timing clock of a specific timing clock generating means and opening a gate only during detection of a servo mark.