JPH10320783A - Wobble signal detecting circuit, wobble abnormality detecting circuit, information processor and information processing method using them and storage medium to be used in them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high-quality recording and reproducing processing by shaping the waveform of the wobble signal read out from a recording medium and supplying it to a PLL circuit and outputting the clock synchronized with the wobble signal to generate a timing generating clock constantly. SOLUTION: A reference clock CLKO is frequency demultiplexed in a frequency divider circuit 57 and the clock for recording and reproducing timing generation 62 of a PLL circuit 55 is frequency demultiplexed in a frequency divider 56 to be fed back to a phase and frequency comparator 95. There is not a wobble part in an identification part and a wobble signal 60 is not generated in the part, since when this device is left as it is, the PLL circuit 55 runs away out of control, an oscillation frequency is retained in the part by stopping the operation of the phase and frequency comparator 95 with a PLL holding signal 63 from a control circuit 35. Thus, the frequency of the wobble signal 60 and the frequency of the feedback 59 almost coincide and the frequency is held constantly even in the identification part and the PLL circuit is operated constantly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing technique capable of recording or reproducing information with high reliability. In particular, the present invention relates to a wobble signal detection circuit for detecting a wobble signal from a recording medium such as a disk, a wobble abnormality detection circuit for detecting an abnormality of a wobble signal, or an information processing apparatus or an information processing method using these detection circuits Further, the present invention relates to a recording medium used in these information processing apparatuses and information processing methods.

[0002]

2. Description of the Related Art As a recording medium for performing recording and reproduction, a groove track and an inter-groove track are provided on a substrate, and they are slightly rocked (wobbled) in a radial direction. Recording media having an information recording area on both of the inter-groove tracks have been developed. This recording medium has a predetermined wobble pattern, and at the time of recording or reproduction, position information or a position signal is obtained by using a wobble signal based on the wobble pattern, and recording or reproduction of information is performed based on the position signal. Is what you do.

Conventionally, a wobble signal based on a wobble pattern from the above-described recording medium cannot be normally generated due to a defect on the recording medium or a control deviation at the time of reproduction, and a wobble signal is lost. There is a problem that a position signal cannot be obtained.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wobble signal detection circuit for stably obtaining a timing generation clock from a wobble signal from a recording medium and an information processing apparatus using the same. It is another object of the present invention to provide a wobble abnormality detection circuit that determines the quality of a recording state during recording using a wobble signal from a recording medium and an information processing apparatus using the same. Still another object of the present invention is to provide a more stable, high-density, and highly reliable information processing technology.

[0005]

A wobble signal detection circuit according to the present invention binarizes a wobble signal, supplies it to a PLL circuit through a polarity switching circuit and a clock switching circuit, and outputs a recording / reproduction timing generation clock to the output of the PLL circuit. Generate. This clock is frequency-divided by the frequency divider and fed back to the PLL circuit. The phase difference between the wobble signal and the feedback signal is detected by an inversion detection circuit. When the phase difference exceeds a predetermined value, a polarity switching signal of the wobble signal is generated, and the polarity of the polarity switching circuit is inverted by this signal. You.

Further, the identification information recorded in the identification section of the recording medium includes an address mark and a sector type. The position where the identification information is inserted can be detected from the address mark, and the position of the identification unit and the position information of the switching unit that switches between the groove track and the inter-groove track can be detected from the sector type.

In another embodiment of the present invention, identification information is detected from the address mark, a sector type is further detected from the identification information, a position of the switching section is detected from the sector type, and another polarity switching signal is detected. Can be obtained.

An error in the identification information is detected, and when the wobble signal is abnormal, the reference clock is supplied to the PLL circuit instead of the wobble signal, and the oscillator of the PLL circuit is synchronized with the reference clock. The wobble signal is not recorded in the section, and in order to suppress the fluctuation of the oscillation frequency of the oscillator of the PLL circuit, the identification section is detected from the address mark and supplied to the PLL circuit, and the oscillation of the PLL circuit is performed between the identification sections. I keep it.

Further, according to the present invention, the number of wobble patterns in one sector is determined or the period of the wobble pattern is determined from the binary signal by the comparator at the time of recording. Can re-record the same data.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples. FIG. 1 is a plan view showing the arrangement of tracks and sectors on a recording medium used in the present invention. In the figure, reference numeral 8 denotes a recording medium. Numeral 1 is a sector divided for each recording unit. Sector 1 is composed of an identification section 2 indicating a division of the sector 1 and a groove track 3 or an inter-track track 4. The identification section 2 is located at the beginning of the sector 1. Be placed. Plural circumferential groove tracks 3 and inter-groove tracks 4 arranged in the radial direction of the disk-shaped recording medium 8
Form one group, the recording medium 8 has a plurality of groups 91, 92, and 93 arranged in the radial direction.
That is, in FIG. 1, the group 91 is composed of the groove track 3 and the inter-groove track 4 that go around. In each of the groups 91, 92 and 93, the discriminating portions 2 of the groove track 3 and the inter-groove portion 4 arranged at the head thereof are aligned in the radial direction. The groove track 3 is slightly wobbled (wobbled) in the radial direction. The length of the sector 1 is determined so as to be substantially constant regardless of the group.

FIG. 2 is a plan view showing a detailed arrangement example of tracks and sectors on a recording medium. Track width 0.7μ
m, groove track 3 having a depth of 60 nm and track width 0.7
μm inter-groove tracks 4 are alternately arranged. Groove track 3 and inter-groove track 4 have one groove in one round.
Track switching section 5 between grooves (hereinafter simply referred to as switching section 5)
Are connected to each other. That is, the groove track 3
Is configured to be connected to the adjacent groove track 4 after one round of the track, and to be connected to the adjacent groove track 3 after one round of the track. Each of the tracks 3 and 4 is divided into a plurality of arc-shaped recording units indicated by a sector 1, and an identification unit 2 is provided at the head of each information recording unit 1. The identification unit 2 is divided into a switching unit 5 and a non-switching unit 6, and the identification unit 2 records identification information 2a. The length of the sector 1 is, for example, about 8 mm, which corresponds to a user capacity of 2048 bytes. The groove track 3 and the groove track 4 are slightly wobbled in the radial direction with an amplitude of about 20 nm. The wobble cycle is 1/232 of the sector length, and the wobble cycle is selected so that an integral multiple of the channel clock cycle of the recording data becomes the wobble cycle. This allows
A recording / reproduction timing generation clock can be generated from the wobble clock. Note that, in FIG.
Reference numeral 2 denotes a sector before and after the switching unit 5, which is used for explaining the numbering of the identification information 2a in FIG. The sector 11 includes the non-switching portion 6 and the groove track 3 or the inter-groove track 4, that is, the recording area 81. The sector 12 includes the switching unit 5 and a recording area 82.

FIG. 3 is a chart showing an example of numbering of identification information of a recording medium used in the present invention. Hereinafter, the numbering of the identification information 2a for identifying the groove track 3 and the groove track 4 will be described with reference to the drawings. The identification information 2a is N-1-S, NS, N-1 ... N-1 + 2
S, N + 2S, and N + 3S. Also identification information 2
“a” is divided into first identification information 21 located on the left side of the switching unit 5 or the non-switching unit 6 in FIG. 3 and second identification information 22 located on the right side. K of K-2 and K-1 indicates the groove track 3 or the track 4 between grooves.
A description will be given with K being the groove track 3 and K-1 and K + 1 being the inter-groove tracks 4.

In this example, information is recorded and reproduced by relatively scanning the light spot 7 from left to right. The groove track K on the left side of the switching section 5 is connected to the inter-groove track K + 1 on the right side of the switching section 5. The inter-groove track K + 1 on the right side of the switching section 5 is connected to the groove track K + 2 via the switching section 5 after one round of this track. In this example, the first identification information 21 of the non-switching portion 6 of the groove track K is N-1 + 2S, and the second identification information 22 is N-1 + S. Here, S indicates the sum of the optical recording information units per track circumference, that is, the number of sectors 1. The non-switching portion 6 of the groove track K is formed by a light spot 7 or the like.
When the identification information 2a is reproduced, N−1 + 2S is reproduced as the first identification information 21 and N−2S is reproduced as the second identification information 22.
1 + S is reproduced. In this case, by deciding to always use the smaller number as the recording area number, N-1 + S of the second identification information 22 is adopted as the identification information 2a of the groove track K. Similarly, when scanning the inter-groove track K-1, N-1 of the first identification information 21 is adopted as the identification information 2a. Therefore, the groove track 3 and the inter-groove track 4 can be distinguished depending on whether the first identification information 21 or the second identification information 22 is employed.

When reproducing the groove track 3 or the groove track 4 in the switching section 5, it is possible to identify the groove track 3 or the groove track 4 in exactly the same manner. Further, since the values of the first identification information 21 and the second identification information 22 are different for each sector 1, the position of each sector 1 of the recording medium 8 can be detected using this. Further, the first identification information 21 and the second identification information 22 indicate whether the information is stored in the switching unit 5 or the non-switching unit 6, and whether the next location is the switching unit 5 or the non-switching unit 6. Is written in 3 bits. This information is information for specifying the switching unit 5 or the non-switching unit 6, and is hereinafter referred to as identification unit specifying information.

Next, the identification information will be described in more detail with reference to FIG. 4 (a), 4 (b), 4
(C) is a schematic diagram showing identification information. In the figure, for example, numerals such as header 1, header 2, PID1 are different from the reference numbers, and the first header, the second header, the first P
Indicates the ID. In order to distinguish the header 1 and the header 2 from the reference numbers, these numbers are shown in parentheses. In the figure, the first identification information 21 includes a header (1) and a header (2). The second identification information 22 includes a header (3) and a header (4).

As shown in FIG. 4B, the header (1) and the header (3) have VFO (1) and header (2) at the beginning.
And a VFO (2) in the header (4).
This VFO is a variable frequency oscillator (Variable F
frequency Oscillator),
It is used to synchronize a PLL circuit (not shown) of the reproduction system. The AM commonly inserted in each of the headers (1) to (4) is an address mark (Address Mark).
And is used to extract information included in the first and second identification information based on the AM (address mark). Each of the headers (1), (2), (3), and (4) has a PID (Physical Identific).
ation) (1), PID (2), PID (3), P
ID (4) is arranged. This is illustrated in FIG.
This will be described in detail with reference to FIG. Furthermore, header (1)-
In (4), IEDs (1) to (4) are arranged. What is the IED? ID Error Detection
n, that is, the ID error detection code. PAs (1) are arranged in the heads (1) and (3), and PAs (2) are arranged in the heads (2) and (4). PA
Is an abbreviation of postamble, and is used to suppress DC reproduction when each data is reproduced and to facilitate binarization.

As shown in FIG. 4C, the PID is composed of sector information (Sector Information) and a sector number (Sector Number). The sector information includes an empty portion (Reserved),
Physical ID # (Physical ID Number),
Sector type (Sector Type), layer #
(Layer Number) is arranged. The physical ID number includes information such as a track number and a sector number. PID (1) is a binary code (00), PD
I (2) is a binary code (01), (3) is (10),
(4) is identified by (11). The sector type includes the number of the sector 1 counted from the switching unit 5. For example, the read-only sector is a binary code (000),
RAM first sector (RAM first sec)
tor) is the first sector of the RAM, that is, the switching unit 5
, The last sector of the RAM is represented by (101), the RAM last sector is represented by (101), and the RAM before sector is represented by (RAM before last sector).
r) represents the second last sector of the RAM by (110), and the RAM other sector (RAM other s).
(ector) represents the other sectors of the RAM by (111).

FIG. 5 is a block diagram showing an embodiment of the information processing apparatus according to the present invention. In the figure, a recording medium 8 is held and rotated by a spindle motor 31. Here, a phase change type recording film (GeSbTe) is used as a recording film forming the recording medium 8. The optical head 32 includes a semiconductor laser that emits laser light for recording and reproducing information, an optical system that forms light from the semiconductor laser as a light spot 7 of about 1 micron on a disk surface, It is composed of a photodetector and the like for obtaining an electric signal necessary for performing reproduction of information, automatic focus control, tracking control, and the like using the reflected light. This optical head 3
2, the information is recorded on the recording medium 8 such as an optical disk, and the information is reproduced from the recording medium 8. The optical head 32 has a linear motor (not shown) for moving the optical head 32 at high speed in the disk radial direction and stopping it near a designated position.

In an information processing apparatus, an optical disk device is usually connected to a host computer 33 (hereinafter abbreviated as a host) such as a personal computer or a workstation, for example, by using a SCSI (Small Computer System).
m Interface) or ATAPI (AT Att)
It is connected by an interface cable conforming to the standard of an Accurated Packet Interface (ACH), and the command and information data from the host 33 are decoded by the interface control circuit 34 in the optical disk device, and the information is transmitted through the control circuit 35 including a microcomputer. Records,
Perform playback and seek operations.

First, the recording operation will be described. The recording data is added with recording position information (address information) on the recording medium 8 from the host 33, and a recording command is issued in this state. The recording data is stored in a buffer memory (not shown) in the control circuit 35 and then sent to the modulation circuit 36 in a time series. In the modulation circuit 36, the recording data is a run-length limited (RLL) code,
For example, a pulse train corresponding to a (1, 7) RLL code, a (2, 7) RLL code, or a code train corresponding to a (2, 10) RLL code, and further corresponding to a mark shape formed on a recording film, for example, When the mark position is recorded, the pulse train is converted to a pulse train corresponding to the code "1". When the mark edge recording is performed, the code "1" is converted to a pulse train corresponding to the pulse edge. Here, (2, 10) RL
An 8/16 conversion code corresponding to the L code is used. That is, 8-bit information is converted into 16 bits and written,
Code conversion for converting 16 bits to 8 bits for reading is performed. These pulse trains are guided to a laser drive circuit 37 to turn on and off the semiconductor laser on the optical head 32 to emit high output pulses. This light pulse is applied to the optical head 32
And a minute spot 7 is formed. The light spot 7 forms a recording mark of an amorphous region on a recording medium 8 having a phase change recording film.

Next, the reproducing operation will be described. At the time of reproduction, the optical head 32 is positioned at the groove track 3 and the groove track 4 on the recording medium 8 specified by the reproduction command from the host 33, and the signals are reproduced from the tracks 3 and 4. First, when the semiconductor laser provided in the optical head 32 is set to a low output, and DC light is emitted to irradiate the recording film on the recording medium 8, reflected light corresponding to the recording mark is obtained. The light is received by the photodetector divided into two, and is subjected to photoelectric conversion, and is input to the reproducing circuit 38 as an electric signal. A reproduction signal for reproducing data can be obtained from a total signal of the photodetector divided into a plurality, that is, a sum signal. Further, since the identification information 2a is disposed at an intermediate portion between the groove track 3 and the inter-groove track 4, the identification signal, which is a reproduction signal of the identification information 2a, is generated between the output signals of the photodetector divided into a plurality. It can be obtained from the differential signal. Therefore, a signal switching circuit is provided in the reproducing circuit 38,
The data signal (sum) and the identification signal (difference) separately detected for binarization at one slice level are the identification information 2a.
The signals are switched according to the timing extracted from, and become a series of signals. This is a combined data signal. This reproduction circuit 3
Reference numeral 8 denotes a signal switching circuit, an automatic gain control circuit for maintaining a constant signal amplitude, a waveform equalizing circuit for correcting optical spatial frequency deterioration, a binarizing circuit, and a PLL (Phase Loc).
(Ked Loop) circuit and a discrimination circuit. After the combined data signal is binarized by a binarization circuit (not shown), it is discriminated by a discrimination circuit (not shown) and converted into discrimination data. That is, it is converted into a signal in which the phase of the reference clock matches the phase of the binary data. The discriminated binarized data is input to the demodulation circuit 39, and (1, 7) RLL
Code, (2,7) RLL code or (2,10)
The original data is demodulated by demodulating the RLL code. The demodulated data is guided to the control circuit 35 and transferred from the interface control circuit 34 to the host 33 in response to a reproduction command from the host 33.

In the photodetector in the optical head 32, in addition to the reproduction signal, an automatic focus control signal for controlling the focus of the light spot 7 on the recording film and a specific groove track 3 or a specific track 4 between the grooves are traced. A tracking control signal for performing track tracking control can be detected. The automatic focus control signal and the tracking control signal for controlling the light spot are input to the servo control circuit 40. Servo control circuit 4
Numeral 0 is composed of an error signal generating circuit, a phase compensating circuit, and a driving circuit, and performs recording and reproduction of information by tracing the optical head 32 on a specific groove track 3 or a specific groove track 4.

The detection of a wobble signal from the wobble pattern arranged in each sector 1 can be obtained from a differential signal between output signals of a plurality of divided photodetectors. For example, in order to obtain a wobble signal from the groove track 3, ± 1st-order diffracted light is obtained from the light reflected from the light spot 7 irradiated on the groove track 3 by a diffraction grating, and the photoelectric conversion element has a plurality of divided regions. To obtain the difference between the output signals of the photoelectric conversion elements. From the signal thus obtained, not only a wobble signal but also a tracking control signal can be obtained. The frequency of the tracking control signal changes in a range of about 1 to 3 KHz, and the objective lens of the optical head 32 changes in response to the frequency in this range. On the other hand, the wobble signal is set at a considerably higher frequency, for example, about 157 KHz, so that tracking is not controlled by the wobble signal. Therefore, even if the wobble signal is mixed in the tracking control signal, the tracking control is not affected. A wobble signal is obtained by filtering this difference signal.

Next, a wobble detection circuit for generating a timing generation clock from a wobble signal will be described with reference to FIG. FIG. 1 is a block diagram showing an embodiment of a wobble signal detection circuit according to the present invention. In the figure, reference numeral 41 denotes a wobble detection circuit, and the wobble signal extracted from the reproduction circuit 38 and the identification signal obtained from the identification information 2a are supplied to the wobble signal detection circuit 41. The identification signal includes a position on the recording medium 8, that is, an address in the recording medium 8, information on whether the track is a groove track or a track between grooves, and information on the position of the switching unit 5 or the non-switching unit 6. The polarities of the tracking error signal obtained from the groove track 3 and the tracking error signal obtained from the inter-groove track 4 are inverted. As a result, the phase of the wobble signal is inverted by the switching unit 5.

In FIG. 6, a wobble signal and an identification signal are extracted from the reproduction circuit 38 and input to the wobble detection circuit 41. The wobble amount is about 20 nm, which is 1 / of the track width.
Since it is a very small amount of 10 or less, a band limiting filter (BPF) 51 and an amplifier (not shown) are used for detecting a wobble signal. Therefore, it is not always necessary to provide an amplifier.) To obtain a stable wobble signal by reducing noise and securing the amplitude. The analog state wobble signal is supplied to the comparator 5
It is binarized by 2. Wobble signal is light spot 7
Of the wobble signal when passing through the groove track 3 and when passing through the groove track 4, since the diffracted light from the light source changes depending on the positional relationship between the light spot 7 and the groove track 3 and between the light spot 7 and the groove track 4. Is inverted. For this reason, it is necessary to switch the polarity for each groove track / inter-groove track by the polarity switching circuit 53. There are two means for generating the switching timing. The first means can be detected by the control circuit 35 by identifying the identification signal (obtained from the identification information 2a on the recording medium) of the switching section 5 located at one place around the track. That is, the detection can be performed by determining whether the first identification information 21 or the second identification information 22 is employed from the identification signals obtained from the differential signals of the plurality of photodetectors. In this case, the polarity switching signal detected by the control circuit 35 is SL / SG (se
select land / select groove), and is indicated by a signal 83. When the optical head 32 starts tracking the groove track 3 or the track 4 between grooves, a normal wobble signal is obtained, and the control circuit 35 detects the normal switching timing.
Is valid. Details of the first means will be described later with reference to the drawings.

The second means will be described with reference to FIG. In the figure, a wobble signal and an identification signal are input to a band limiting filter 51 of a wobble detection circuit 41, and a wobble signal in an analog state is extracted from the filter 51. This signal is compared with a reference signal by a comparator 52, binarized, supplied to a phase frequency comparator 95 of a PLL circuit 55 as a wobble signal 60 through a polarity switching circuit 53 and a clock switching circuit 54, and inverted. It is supplied to the detection circuit 58. Wobble signal 6
0 is output as a recording / reproduction timing generation clock 62 (hereinafter simply referred to as a timing generation clock) through a phase frequency comparator 95, a phase compensator 96, and a voltage controlled oscillator 97. The frequency of the wobble signal 60 is set lower than the normal timing generation clock 62. In this example, the frequency of the wobble signal 60 is set to 1/186 of the timing generation clock 62. Therefore, the timing generation clock 62 is frequency-divided by the frequency divider 56 and fed back to the phase frequency comparator 95 of the PLL circuit 55. The phase of the feedback signal 59 and the wobble signal 60 are compared by a phase frequency comparator 95, the voltage control oscillator 97 is controlled through a phase compensator 96, and the timing generation clock 62 adjusted to the phase of the wobble signal 60 is supplied to the PLL circuit 55. Is output from the output terminal. This timing generation clock 62 is frequency-divided by the frequency dividing circuit 56 so as to have the same frequency as the frequency of the wobble signal 60. The frequency-divided signal is supplied as a feedback signal 59 to the PLL circuit 55 and the inversion detection circuit 58.
When the phase difference between the wobble signal 60 and the feedback signal 59 becomes larger than a predetermined value, a second polarity switching signal 61 is generated from the inversion detection circuit 58 and supplied to the polarity switching circuit 53 to invert the polarity of the wobble signal.
Normally, the first polarity switching signal 83, which is SL / SG, from the control circuit 35 passes through the EOR gate 75 in the inversion detection circuit 58 and is supplied to the polarity switching circuit 53 to invert the phase of the wobble signal. However, when the bit of the identification unit 2 is crushed or the bit is defective, the first and second identification information 21 and 22 are not reproduced. Therefore, the first polarity switching signal 83 is not generated or is generated erroneously.
This signal 83 cannot be used. In this case, the polarity of the wobble signal 60 is switched using the second polarity switching signal 61.

Also, the wobble signal 60 is not reproduced when the optical head 32 is started or during a seek, and therefore, the timing generation clock 62 cannot be secured.
In this case, the frequency of a reference clock CLKO from a reference oscillator (not shown) is divided by a frequency dividing circuit 57 so that the frequency is the same as the frequency of the wobble signal 60 and supplied to the clock switching circuit 54. When the optical head 32 starts up or seeks, a clock switching signal 64 is generated from the control circuit 35, so that the reference clock divided by the clock switching signal 64 is supplied to the PLL circuit 55. Therefore, the PLL circuit 55 operates normally even at the time of start-up or seek, and a timing generation clock is output at its output. As described above, by inputting the reference clock from the crystal oscillator until the optical head 32 starts track tracking and obtains the normal wobble signal 60,
The PLL circuit 55 for the wobble clock always operates stably.

Next, generation of a timing generation clock by the PLL circuit 55 will be further described. The frequency of the wobble signal to be detected is set to, for example, 1
When / 186 is set, the phase frequency comparator 95 in the input stage of the PLL circuit 55 has a problem that the period of the wobble signal 60 is too slow and the phase comparison gain is small, so that the pull-in time to reach the reference frequency becomes long. Occurs. Further, there is also a problem that a PLL of a type that performs frequency pull-in cannot be adopted because the difference between the frequencies of the timing generation clock 62 and the wobble signal 60 is large. For this reason,
In this embodiment, the reference clock CLK0 from the crystal oscillator is frequency-divided by the frequency dividing circuit 57 in order to match the input frequency of the phase frequency comparator 95 with the wobble signal 60, and the recording / reproducing timing generating clock 62 of the PLL circuit 55 is generated. The frequency is divided by the frequency divider 56 and fed back to the phase frequency comparator 95. In addition, the identification unit 2 has no wobble portion,
Since the wobble signal 60 is not generated, P
Since the LL circuit 55 goes out of control, the PL
The oscillation frequency is held by stopping the operation of the phase frequency comparator 95 of the PLL circuit 55 during the identification unit 2 by the L holding signal 63. As a result, the input wobble signal 6
The frequency of 0 and the frequency of the feedback signal 59 are substantially the same, the frequency is kept constant in the identification unit 2, and the PLL circuit 55 operates stably.

CLV (Constant Linear)
Velocity) or ZCLV (Zone C)
When the recording medium 8 recorded in (LV) is reproduced, the number of revolutions of the spindle motor 31 fluctuates at the time of seeking, and the reproducing process cannot be executed until the number of revolutions reaches the specified value, so that the effective seek time becomes longer. Sometimes. This problem can be solved by providing the PLL circuit 55 with a function similar to the wide capture reproduction employed in the CD-ROM device. Specifically, if the PLL circuit 55 is provided with a frequency pull-in function, even if the rotational speed is out of the steady state, the PLL circuit 55 is synchronized with the input wobble signal 60 to obtain
The LL circuit 55 operates to perform a reproducing operation.

PLL circuit 5 having frequency pull-in function
5, the PLL circuit 55 is synchronized with the input wobble signal 60 even when the rotational speed is out of the steady state.
Operates to perform a reproducing operation. When a PLL circuit including only a comparator is employed, a frequency detector is separately added, and a VCO (Voltage Control OSCi) in the PLL circuit in the reproduction circuit 38 is added.
llator) is changed in the direction in which the rotational speed fluctuates until the frequencies match, and when the frequencies match, the PLL circuit is locked and synchronization is performed, whereby a similar effect can be obtained.

As another embodiment, the PL in the reproducing circuit 38
The signal input of the L circuit converts the recording / reproduction signal and the reference clock to RD.
In the case of a type that can be switched by GATE (READ GATE), by inputting the output of the wobble detection circuit 41 as a reference clock, the VC of the PLL circuit 55 is always output.
The O frequency can be made to coincide with the wobble frequency, and the time during which the rotation speed of the spindle motor 31 falls within an allowable range can be reduced, so that the seek time can be reduced.

A specific circuit configuration of the inversion detection circuit 58 will be described with reference to FIG. FIG. 7A is a block diagram showing an embodiment of the inversion detection circuit used in the wobble signal detection circuit according to the present invention, and FIG. 7B is a time chart of a signal used for describing the inversion detection circuit according to the present invention. It is a chart. In FIG. 7A, a wobble signal 60, which is an output signal of the clock switching circuit 54, and a feedback signal 59 obtained by dividing the output of the PLL circuit 55 to 1/186 by the frequency dividing circuit 56 are the EOR (inverting detection circuit 58). Exclsi
(ve OR) gate 71. The feedback signal 59 and the wobble signal 60 are slightly out of phase as shown in FIG. The feedback signal 59 and the wobble signal 60 are controlled by the PLL circuit 55 so that they are in phase. However, a slight shift occurs in the phase due to a delay in the response of the PLL circuit 55 or the like. An output pulse A is generated at the output terminal of the EOR gate 71 due to the phase difference between the feedback signal 59 and the wobble signal 60. This pulse A is ANDed with the clock CLK0 by the AND gate 72, and a pulse B is obtained at the output of the AND gate 72. This pulse B is counted by the counter 73 at the next stage. Here, if the counter 73 is set so that the output of the counter 73 is turned on when the counter 73 measures, for example, 64 or more pulses, the output of the counter 73 becomes high level when the pulse becomes 64 or more. ,
A pulse C is generated at the output of the counter 73. The flip-flop 74 of the next stage is inverted at the timing of the rising of the pulse C, and the output thereof is the second polarity switching signal 61.
Is generated. This signal 61 becomes an output of the inversion detection circuit 58 through the EOR gate 75 and is supplied to the polarity switching circuit 53 to invert the polarity of the wobble signal.

Thus, the output 6 of the clock switching circuit 54
0 is switched, and the phase difference between the feedback signal 59 and the wobble signal 60 almost disappears.
Since the counter 73 is cleared by the output signal A of the gate 71, the counter 73 stops counting. After one round, when the signal enters the switching unit 5 again, the polarity of the flip-flop 74 is inverted again and the polarity is continuously switched. On the other hand, the first polarity switching signal 83 obtained from the control circuit 35 as described later is supplied to the EOR gate 75. The first polarity switching signal 83 is supplied to the EOR gate 75
Is supplied to the polarity switching circuit 53 through The first polarity switching signal 83 switches the polarity of the wobble signal by the switching signal 83 when the light spot 7 is accurately tracing the groove track 3 or the inter-groove track 4. , The first polarity switching signal 83 cannot be obtained. Even in this case, the second polarity switching signal 61 is output from the inversion detection circuit 58 as described above.
Is selected, the polarity of the wobble signal can be switched stably, and the PLL circuit 55 can be operated stably.

Next, a control circuit according to the present invention will be described with reference to FIGS. FIG. 8 is a block diagram showing one embodiment of the control circuit according to the present invention. FIG. 9 is a block diagram showing one embodiment of the AM detector and the timing controller shown in FIG. In the figure, a reproduced data sequence and a reproduced clock synchronized with the reproduced data sequence are input to an input terminal 101 from a demodulation circuit 39 shown in FIG. 5, and a first identification information detector 102, a second identification information detector 103, and an AM (Address mark) is supplied to the detector 104. The timing generation clock 62 is input to the input terminal 106 from the PLL circuit 55 shown in FIG.

First, the AM detector 104 and the timing controller 112 will be described with reference to FIG. In FIG. 8, the input terminal 101 is shown as the input terminal 101 of the AM detector 104. The input terminal 101 is an input terminal 101a to which a reproduced data string is input and an input terminal 101b to which a reproduced clock is input.
It is composed of The AM detector 104 includes a shift register 108, a comparator 109, and an AM pattern sequence generator 11.
0.

The pattern sequence of the address mark is a unique pattern sequence, and this pattern sequence is not used in this system except for the address mark. The reproduced data sequence is sequentially sent through the shift register 108 with the reproduced clock, and A
When the same pattern sequence as the M pattern sequence comes, an AM detection pulse is output to the comparator 109. This AM detection pulse is supplied to the counter 114 of the timing controller 112.
Further, the counter 114 is supplied with the timing generation clock 62 from the PLL circuit 55 shown in FIG.

The counter 114 is cleared by the AM detection pulse, and starts counting the timing generation clock 62. Since the positions of the first identification information position, the second identification information position, the identification portion position, and the sector start position are determined from the AM detection pulse, the timing generation clocks are counted from the AM detection pulse, and are counted to predetermined positions. is there. Therefore, by comparing the output of the counter 114 with the output of the first identification information position generator 116 by the comparator 118, the first identification information detection pulse is taken out to the output terminal 120. Similarly, by comparing the counter 114 with the second identification information position detector 122 and the comparator 124, the second identification information detection pulse is taken out to the terminal 126. Furthermore,
By comparing the output of the counter 114 with the discrimination position generator 128 and the comparator 130, a discrimination part detection pulse is taken out to the terminal 132. By comparing the output of the counter 114 with the output of the sector position generator 134 by the comparator 136, a sector start position detection pulse can be extracted from the output terminal 138.

In FIG. 8, the first identification information detection pulse taken out from the terminal 120 is supplied to the first identification information detector 102. Since the reproduction data string is supplied from the terminal 101 to the detector 102, the first identification information 21 and the IED are extracted at the timing of the first identification information detection pulse.
The extracted first identification information is supplied to the error detector 140, and the presence or absence of an error is ticked by the error detection code IED, and the result is supplied to the identification information selector 142. Similarly, the second identification information 22 is extracted from the second identification information detector 103, the presence or absence of an error is ticked by the error detector 144, and supplied to the identification information selector 142.
When there is an error in the first and second identification information 21 and 22 in the error detectors 140 and 144, a pulse is generated, and when there is no error, no pulse is generated.
The outputs of the error detectors 140 and 144 are output from the identification information selector 14.
2 is supplied. As shown in FIG. 10, the identification information selector 142 includes flip-flops 147 and 146 and AND
The circuit 148 includes an error detector 140,
The output of 44 is supplied to flip-flops 146 and 147, respectively, and the output is further supplied to AND circuit 148. If there is an error in both the first and second identification information 21 and 22, a pulse is generated on the flop flops 146 and 147, and a pulse is generated on the output of the AND circuit 148. If one or both of the first and second identification information 21 and 22 are correct, no pulse is generated at the output of the AND circuit 148. The output pulse of the AND circuit 148 is supplied to the continuous reproduction detector 150. The circuit 150 is mainly composed of a counter. The counter counts the output of the AND circuit 148, and when the number exceeds a predetermined number, the output of the continuous reproduction detector 150 rises.
This signal is supplied as a clock switching signal 64 to a clock switching circuit 54 shown in FIG. The counter of the continuous reproduction detector 150 is a flop flop 146, 1
A signal obtained by passing the output of the NOR circuit 47 through the NOR circuit 170 and the identification unit detection pulse 132 from the timing controller 112 are represented by A
The ND circuit 171 is reset by a pulse that is ANDed. The pulse indicating the end of the identification signal is the counter 11 in FIG.
4 and the output of the identification information end position generator (not shown) are obtained by comparing with the comparator (not shown).

Thus, the wobble pattern is missing,
When the wobble signal 60 is no longer output, the frequency of the timing generation clock 62 goes out of order. Then, the counter 114 shown in FIG.
The identification information 21 and 22 cannot be taken out, and an error occurs in the first and second identification information 21 and 22. The clock switching signal 64 is generated from the error information as described above, and FIG.
By switching the clock switching circuit 54 and supplying a reference clock from the external crystal oscillator to the PLL circuit 55, runaway of the PLL circuit 55 can be prevented.

The outputs of the flop-flops 146 and 147 of the identification information selector 142 are supplied to the identification information register 152 in FIG. 8, and the first and second identification information detectors 10 are provided.
2, 103 outputs are provided.

The outputs of the flops 146 and 147 are used as 2-bit data. When both the first and second identification information 21 and 22 are correct (00), when an error occurs in the first identification information 21 (01), when an error occurs in the second identification information 22, Is (10), and if an error occurs in both the first and second identification information 21 and 22, the data of (11) is stored in the identification information register 152.
Is input to

In the case of (00), the identification information of the smaller number is stored (see FIG. 3 and its description), and (0)
In cases 1) and (10), the correct identification information is stored. In the case of identification information having a larger number, the number of sectors S is subtracted and stored. (11), ie, first and second identification information 2
When there is an error in both the information 1 and 22, the information is complemented from the preceding identification information and stored. This stored information indicates the current position of the light spot 7 and is used when measuring the distance from the target at the time of seeking.

The sector type detector 154 has first and second
The 3-bit sector type extracted by the identification information detectors 102 and 103 is supplied. This sector type is the first,
Since the position of the second identification information 21 or 22 is known, the counter is reset by the first identification information detection pulse and the second identification information detection pulse, and then the reproduction clock is counted by the counter. It can be easily detected. The sector type detector 154 determines the sector type extracted from the first identification information 21 and the sector type extracted from the second identification information 22 by the error detector 140,
Using the output of 144, an error-free sector type is output. In order to extract a sector type having no error, the sector type detector 154 may be turned off by an error output from the error detectors 140 and 144 to cut off the sector type path. In this way, the sector type (100) having no error, that is, the first sector type is extracted, the first polarity switching signal 83 is output to the output of the sector type detector 154, and this signal 83 is supplied to the polarity switching circuit 53. By doing so, the polarity of the wobble signal is switched.
When both outputs of the error detectors 140 and 144 are errors, the first polarity switching signal 83 is generated by complementing the information immediately before the switching unit of the sector types (101) and (110).

If all these detections cannot be made, the polarity of the wobble signal is switched by the second polarity switching signal 61 from the inversion detector 58.

The identification section detection pulse extracted from the timing controller 126 is supplied to the OR circuit 156, and becomes an identification section pulse of 1 in the identification section and 0 in other portions. The wobble signal 60 and the timing generation clock 62 are supplied to the number-of-clocks-in-period detector 158, and one cycle of the wobble signal 60 is counted by the timing generation clock 62. Outputs periodic abnormal pulse. The wobble cycle abnormal pulse is supplied to the OR circuit 156 as an abnormality of the wobble shape, logically ORed with the identification unit detection pulse, and supplied to the PLL circuit 55 as the PLL holding signal 63.

The sector start position pulse from the timing controller 112 is supplied to the intra-sector pulse number detection circuit 160 to generate a pulse at the interval of the sector 1, and the interval is counted by the wobble signal 60. If the count is not correct, it is determined that there is a defect somewhere in sector 1 and this output is stored in defect detection register 162 and used to detect a defect in sector 1. Pulses at intervals of sector 1 can be easily obtained by counting the timing generation clock 62.

Next, an embodiment of the wobble abnormality detection circuit is shown in FIG.
1 will be described. FIG. 11 is a block diagram showing one embodiment of the wobble abnormality detection circuit according to the present invention. In the figure, reference numeral 76 denotes a wobble abnormality detection circuit.
6 is to detect a wobble signal even during recording, to detect that the wobble signal has become abnormal due to a defect in the wobble pattern, etc., and to maintain high reliability by re-recording the same data when an abnormality is detected. Provided. The counter 77 of the wobble abnormality detection circuit 76 has a wobble detection circuit 4
The wobble signal 60 is supplied from one clock switching circuit 54. The counter 77 counts the number of wobble signals 60 in one sector of the minimum recording unit by the counter 77 and outputs the result to the determination circuit 78. The judgment circuit 78 outputs a judgment signal 79 when the set judgment value exceeds the value or when the value is insufficient. The determination signal 79 is supplied to a register (not shown) in the control circuit 35, and an error bit is set. A case where the count value of the counter value is larger than the set value of the determination circuit 78 is considered to be due to a boiling defect, and a case where the count value is insufficient is considered to be a wobble pattern missing due to the defect. ECC (Error Correction) of the device
An error bit is set when the correction capability exceeds the on-code correction capability. In this case, the recording data of the sector recognized as abnormal recording and determined to be abnormal is rewritten to the same sector or another sector. Therefore, recording is performed while referring to the error bit. When the error bit is set, re-recording is performed.

FIG. 12 is a block diagram showing another embodiment of the wobble abnormality detection circuit according to the present invention.
Numeral 0 denotes a wobble abnormality detection circuit, and this circuit 80 comprises a cycle measurement circuit 84 and a cycle determination circuit 85.
The wobble signal 60 is supplied to the cycle measuring circuit 84, the cycle of the wobble signal 60 is measured, and the output is supplied to the cycle determining circuit 85 of the next stage. If the cycle is less than the set determination value in the cycle determination circuit 85 or exceeds the determined value, a determination signal 87 is output from the output, and this signal 87 is output to a register in the control circuit 35 by an error. Set a bit. At the time of recording, the control circuit 35 continues the recording process while referring to the error bit. If the control circuit 35 recognizes the error bit, the control circuit 35 recognizes that the recording is abnormal and the sector or recording information unit determined to be abnormal. Thus, the same data is re-recorded in the same sector or block for a block composed of a plurality of sectors, and high reliability can be maintained.

[0049]

As described above, according to the present invention, a timing generation clock can be stably generated by using the wobble detection circuit, so that highly reliable recording / reproducing processing can be performed without being affected by defects or the like. Becomes Further, according to the present invention, the quality of the recording state at the time of recording can be determined using the wobble signal, so that more stable, high-density, and highly reliable information processing can be performed.

[Brief description of the drawings]

FIG. 1 is a plan view showing the arrangement of tracks and sectors on a recording medium used in the present invention.

FIG. 2 is a plan view showing a detailed arrangement of tracks and sectors of a recording medium used in the present invention.

FIG. 3 is a chart showing an example of numbering of identification information of a recording medium used in the present invention.

FIG. 4 is a schematic diagram showing identification information, headers of the identification information, and contents of physical identification information used in the present invention.

FIG. 5 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

FIG. 6 is a block diagram showing an embodiment of a wobble signal detection circuit according to the present invention.

FIG. 7 is a block diagram showing an embodiment of an inversion detection circuit used in a wobble signal detection circuit according to the present invention, and a time chart of signals used for explaining the inversion detection circuit.

FIG. 8 is a block diagram showing one embodiment of a control circuit according to the present invention.

FIG. 9 is a block diagram showing one embodiment of an AM detector and a timing controller shown in FIG. 8;

FIG. 10 is a block diagram showing one embodiment of the identification information selector of FIG. 8;

FIG. 11 is a block diagram showing one embodiment of a wobble abnormality detection circuit according to the present invention.

FIG. 12 is a block diagram showing another embodiment of the wobble abnormality detection circuit according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sector, 2 ... identification part, 3 ... groove track, 4 ... groove track, 5 ... switching part, 6 ... non-switching part, 35 ... control circuit, 51 ... band limiting filter, 52 ... comparator, 5
3: polarity switching circuit, 54: clock switching circuit, 55: P
LL circuit, 56, 57: frequency dividing circuit, 58: inversion detecting circuit, 60: wobble signal, 61: second polarity switching signal, 6
2: timing generation clock, 63: PLL holding signal,
64: clock switching signal; 83: first polarity switching signal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuya Ikeda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Video Information Media Division (72) Inventor Toshiaki Ishibashi Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292, Hitachi, Ltd.Video Information Media Division (72) Inventor Kazuo Shigematsu292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Hitachi, Ltd.Video Information Media Division

Claims (35)

[Claims] 1. A waveform shaping circuit and a PLL circuit, wherein a wobble signal read from a recording medium is shaped by the waveform shaping circuit, and the waveform-shaped signal is supplied to the PLL circuit to be converted into the wobble signal. A wobble signal detection circuit for outputting a synchronized clock. 2. A waveform shaping circuit for shaping the waveform of a wobble signal, a polarity switching circuit for switching the polarity of the wobble signal, and a wobble signal output from the polarity switching circuit are supplied to an output. When a PLL circuit that outputs a synchronized clock and a signal obtained by feeding back the wobble signal and the output signal of the PLL circuit are supplied, and a phase difference between the wobble signal and the feedback signal exceeds a predetermined phase difference. And a reversal detection circuit for generating a polarity switching signal, wherein the polarity switching signal is supplied to the polarity switching circuit to switch the polarity of a wobble signal input to the polarity switching circuit. circuit. 3. The wobble signal detection circuit according to claim 2, wherein said waveform shaping circuit is constituted by a comparator, and the wobble signal is binarized and supplied to said polarity switching circuit. . 4. A wobble signal detecting circuit according to claim 2, further comprising a frequency dividing circuit for dividing the output of said PLL circuit through said frequency dividing circuit so as to have substantially the same frequency as the frequency of the wobble signal. A wobble signal detection circuit for inputting the signal to the PLL circuit. 5. The wobble signal detection circuit according to claim 2, wherein said PLL circuit comprises a phase comparator and a voltage controlled oscillator. 6. The wobble signal detecting circuit according to claim 4, wherein a wobble signal output from said switching circuit and an output of said frequency dividing circuit are supplied to said inverting circuit. 7. The wobble signal detection circuit according to claim 2, wherein said inversion detection circuit is supplied with said wobble signal and said feedback signal, and generates an output according to a phase difference between said two signals. A counter that counts the pulse width and generates an output when the output of the counter exceeds a predetermined value, and a signal generation circuit that generates a polarity switching signal based on the output of the counter. A wobble signal detection circuit. 8. The wobble signal detection circuit according to claim 7, wherein said signal generation circuit comprises a flip-flop. 9. A groove track and an inter-groove track are alternately arranged, a wobble section is provided between the groove track and the inter-groove track, and a connection between the groove track and the inter-groove track is provided. A switching unit, wherein the switching unit detects an identification signal reproduced from identification information in order to detect a wobble signal from a recording medium on which no wobble unit is recorded, and the identification information detector And a detector for detecting a signal indicative of the switching unit from the output signal of the above and outputting a polarity switching signal. 10. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and a connection between the groove track and the inter-groove track is provided. Is performed by a switching unit, and identification information is recorded in the switching unit. The identification information is an address mark for extracting the identification information and a polarity of a wobble signal from a recording medium including sector type information indicating the switching unit. An address mark detector for detecting an address mark, a timing controller for generating an identification information detection pulse using an output of the address mark detector, and a timing controller for generating a signal for switching An identification information detector for detecting identification information using the identification information detection pulse of the above, and a sector type based on the identification information output from the identification information detector. A sector type detector for detecting and outputting a signal indicating a switching section from the sector type, wherein the output of the sector type detector is a polarity switching signal for switching the polarity of the wobble signal. Detection circuit. 11. The wobble signal detection circuit according to claim 10, wherein the identification information of the switching unit is the first identification information and the second identification information.
Detecting the identification information to obtain a polarity switching signal for switching the polarity of the wobble signal in the switching unit from the recording medium including the identification information and including the address mark and the sector type in the first and second identification information. A wobble signal detection circuit, wherein the detector comprises first and second identification information detectors. 12. The wobble signal detection circuit according to claim 11, further comprising an error detector, wherein outputs of said first and second identification information detectors are respectively supplied to an error detector. A polarity switching signal is output from the error-free identification information, and if there is no error in both the first and second identification information, the polarity switching signal is used by using the identification information that satisfies a predetermined condition. A wobble signal detection circuit. 13. A clock switching circuit to which a wobble signal and a clock obtained by dividing a reference clock are supplied, a PLL circuit to which an output of the clock switching circuit is supplied, and a clock switching signal which detects abnormality of the wobble signal. When a wobble signal cannot be detected normally, an output of the clock switching signal generator is supplied to the clock switching circuit to switch the clock switching circuit, and the PLL circuit A wobble signal detection circuit for supplying a divided reference clock. 14. A wobble signal detection circuit according to claim 13, wherein said clock switching signal generator detects identification information recorded on a recording medium, and an error detector detects an error in the identification information. And a wobble signal detection circuit. 15. The wobble detection circuit according to claim 14, wherein said clock switching signal generator further comprises a continuous reproduction detector for generating an output when the output of said error detector is generated continuously. A wobble signal detection circuit. 16. A PLL circuit to which a wobble signal is inputted and which generates a clock for generating recording / reproduction timing at an output thereof;
A PLL holding signal generator that detects the position of the identification unit from the identification information recorded in the identification unit of the recording medium and generates a PLL holding signal, by supplying the PLL holding signal to the PLL circuit, A wobble signal detection circuit for maintaining oscillation of an oscillator constituting a PLL circuit during a period of an identification unit. 17. The wobble signal detection circuit according to claim 16, wherein said PLL holding signal generator detects an address mark included in identification information recorded in an identification section of a recording medium. A wobble signal detection circuit, comprising: a timing controller that outputs an identification section detection pulse from an output of the address mark detector. 18. The wobble signal detection circuit according to claim 17, wherein said PLL holding signal generator further measures one cycle of a wobble signal using a recording / reproduction timing clock output output from said PLL circuit. A wobble signal detector comprising a measuring device that generates a wobble abnormality signal when the measured value is different from a predetermined value. 19. The wobble signal detection circuit according to claim 18, wherein the PLL holding signal generator further performs a logical sum of an output of the measuring device and an identification detection pulse output from the timing controller. And a wobble signal detection circuit. 20. An identification information detector for detecting identification information recorded in an identification section of a recording medium, an error detector for detecting an error in the detected identification information, and an identification for storing an output of the error detector. An information processing apparatus comprising: an information register. 21. An information processing apparatus according to claim 20, wherein said identification information comprises first and second identification information, said identification information detector comprises first and second identification information detectors, and An information processing apparatus, wherein the detector comprises first and second error detectors. 22. An information processing apparatus according to claim 21, further comprising: an identification information selector which receives the outputs of said first and second error detectors and selects and outputs an error of identification information. An information processing apparatus characterized by the above-mentioned. 23. An information processing apparatus according to claim 22, wherein said identification information selector comprises first and second flip-flops. 24. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and the groove track and the inter-groove track are recorded on an arc. An identification unit in which a wobble signal is not recorded is provided at the head of each sector, and one identification unit provided in one round is used for switching connection between the groove track and the inter-groove track. A timing controller for generating a sector start position detection pulse indicating a start position of the sector, in order to detect a defect of a sector of the recording medium on which the identification information is recorded, A sector length detector that measures the length of the sector using an output of a timing controller and generates an output when the length of the sector is different from a predetermined length. The information processing apparatus characterized by being composed of a register for storing the output of the sector length detector. 25. An information processing apparatus according to claim 24, wherein said sector length detector comprises an intra-sector pulse detector for counting said sector by a wobble signal. 26. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and a connection between the groove track and the inter-groove track is provided. Is performed by a switching unit, and identification information is recorded in the switching unit. The identification information is an address mark for extracting the identification information and a polarity of a wobble signal from a recording medium including sector type information indicating the switching unit. In order to generate a signal for switching the wobble signal, a waveform shaping circuit for shaping the waveform of the wobble signal, a polarity switching circuit for switching the polarity of the wobble signal, and a wobble signal output from the polarity switching circuit are supplied. A PLL circuit for outputting a clock synchronized with the PLL circuit, the wobble signal and the PLL
A signal obtained by feeding back an output signal of the circuit is supplied, and an inversion detection circuit for generating a polarity switching signal when a phase difference between the wobble signal and the feedback signal exceeds a predetermined phase difference, and detecting an address mark. Mark detector for generating an identification information detection pulse using the output of the address mark detector, and identification information detection for detecting identification information using the identification information detection pulse from the timing controller And a sector type detector that detects a sector type from the identification information output from the identification information detector and outputs a signal indicating a switching unit from the sector type,
An information processing apparatus, wherein an output of the inversion detection circuit and an output of the sector type detector are supplied to the polarity switching circuit to switch the polarity of a wobble signal. 27. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and the groove track and the inter-groove track are recorded on an arc. The discrimination unit is divided into sectors, and an identification unit in which a wobble signal is not recorded is provided at the head of each sector, and one identification unit provided in one circumference switches the connection between the groove track and the inter-groove track. A clock obtained by dividing a wobble signal and a reference clock in order to obtain a clock for generating a recording / reproducing timing from a wobble signal from a recording medium on which identification information including an address mark is recorded; , A PLL circuit to which an output of the clock switching circuit is supplied, an identification information detector for detecting identification information, and the identification information detection circuit. An error detector for detecting an error in the output of the device, and a continuous reproduction detector for generating an output when the output of the error detector is continuously generated, and when the wobble signal cannot be normally detected. An information processing apparatus for supplying an output of the continuous reproduction detector to the clock switching circuit to switch the clock switching circuit, and supplying the frequency-divided reference clock to the PLL circuit. 28. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and the groove track and the inter-groove track are recorded on an arc. The discrimination unit is divided into sectors, and an identification unit in which a wobble signal is not recorded is provided at the head of each sector, and one identification unit provided in one circumference switches the connection between the groove track and the inter-groove track. A switching unit, wherein the identification unit receives a wobble signal from a wobble signal from a recording medium on which identification information including an address mark is recorded, in order to obtain a recording / reproduction timing generation clock; A PLL circuit for generating a timing generation clock and an address mask for detecting an address mark included in identification information recorded in an identification section of the recording medium. A timing controller that outputs an identification information detection pulse from an output of the address mark detector; an identification information detector that detects identification information using the identification information detection pulse from the timing controller; A sector type detector for detecting a sector type from the identification information output from the device, and outputting a signal indicating a switching unit from the sector type, wherein the output of the sector type detector is a PLL holding signal and the PLL circuit is used as a PLL holding signal. An information processing apparatus characterized in that an oscillation of an oscillator forming a PLL circuit is maintained during a period of a discrimination unit by supplying the information to an information processing unit. 29. A wobble signal measuring device for supplying a wobble signal and measuring the wobble signal, and a judging device for judging a result measured by the wobble signal measuring device. A wobble abnormality detection circuit, wherein a signal is output to an output. 30. A wobble signal measuring device to which a wobble signal is supplied and measures a wobble signal, a determiner for determining a result measured by the wobble signal measuring device, and a result of the determination by the determiner, which is determined to be abnormal. Means for re-recording the same data in the same sector or block with respect to the selected sector or block as a recording information unit. 31. An information processing apparatus according to claim 30, wherein said wobble signal measuring device comprises a counter for counting the number of wobble signals of a wobble signal in a sector which is a minimum recording unit of a recording medium, and said judgment circuit comprises a counter. An information processing apparatus, wherein an abnormality is determined when a numerical value deviates from a preset value. 32. An information processing apparatus according to claim 30, wherein said wobble signal measuring device comprises a period measuring circuit for measuring a period of a wobble signal, and said judgment circuit is provided when a measured value deviates from a set judgment value. Is an information processing apparatus characterized by determining that the information is abnormal. 33. A recording medium on which information is recorded in accordance with a timing signal generated based on a clock phase-synchronized with a wobble signal. 34. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and a connection between the groove track and the inter-groove track is provided. Is performed by a switching unit, and identification information is recorded in the switching unit. The identification information is an address mark for extracting the identification information and a polarity of a wobble signal from a recording medium including sector type information indicating the switching unit. In order to generate a signal for switching the wobble signal, a waveform shaping circuit for shaping the waveform of the wobble signal, a polarity switching circuit for switching the polarity of the wobble signal, and a wobble signal output from the polarity switching circuit, A PLL circuit for outputting a clock synchronized with the wobble signal at an output, wherein a phase difference between the wobble signal and the feedback signal is a predetermined level. The polarity switching signal generated when exceeding the difference, an information processing method comprising the step of reversing the polarity of the wobble signal and supplies the polarity switching signal to said polarity switching circuit. 35. A groove track and an inter-groove track are alternately arranged, a wobble portion is provided between the groove track and the inter-groove track, and a connection between the groove track and the inter-groove track is provided. Is performed by a switching unit, and identification information is recorded in the switching unit. The identification information is an address mark for extracting the identification information and a polarity of a wobble signal from a recording medium including sector type information indicating the switching unit. In order to generate a signal for switching, the address mark is detected, an identification information detection pulse is generated using the address mark, identification information is detected using the identification information detection pulse, and the identification information is detected from the identification information. Detecting a sector type and outputting a signal indicating a switching unit from the sector type;
An information processing method, wherein the polarity of a wobble signal is switched by a signal indicating the switching unit.