JPH061752B2 - Method for joining semiconductor wafers - Google Patents

Method for joining semiconductor wafers

Info

Publication number
JPH061752B2
JPH061752B2 JP58230336A JP23033683A JPH061752B2 JP H061752 B2 JPH061752 B2 JP H061752B2 JP 58230336 A JP58230336 A JP 58230336A JP 23033683 A JP23033683 A JP 23033683A JP H061752 B2 JPH061752 B2 JP H061752B2
Authority
JP
Japan
Prior art keywords
semiconductor wafers
semiconductor
polished
bonding
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58230336A
Other languages
Japanese (ja)
Other versions
JPS60121715A (en
Inventor
優 新保
潔 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58230336A priority Critical patent/JPH061752B2/en
Publication of JPS60121715A publication Critical patent/JPS60121715A/en
Publication of JPH061752B2 publication Critical patent/JPH061752B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、シリコンなどの半導体ウエハの接合方法に関
する。
Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for bonding semiconductor wafers such as silicon.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体ウエハの面上に、同種のまたは組成や不純物濃度
の異なる他の半導体層を形成する技術は、種々の方法が
知られている。例えば、化学蒸着法や物理蒸着法を応用
した気相成長法、液相エピタキシヤル成長法、合金接合
法、半田などの接着層を利用した接着法、などである。
しかしながら、従来の各種蒸着法では堆積速度が遅く、
例えば数100μmといつた半導体層を形成しようとす
ると極めて長い時間を要するという問題がある。また異
種材料の接着層で半導体ウエハを接合する方法では、昇
温すると接着層材料が半導体中に拡散したり、化合物を
生成して変質をおこすという不都合がある。半導体ウエ
ハ同志が異物の介在なしに直接接合できれば、これらの
問題は解決される。
Various methods are known as techniques for forming another semiconductor layer of the same type or different in composition and impurity concentration on the surface of a semiconductor wafer. For example, a vapor phase growth method applying a chemical vapor deposition method or a physical vapor deposition method, a liquid phase epitaxial growth method, an alloy joining method, an adhesion method using an adhesive layer such as solder, and the like.
However, the deposition rate is slow in various conventional vapor deposition methods,
For example, there is a problem that it takes an extremely long time to form a semiconductor layer having a thickness of several 100 μm. Further, the method of joining the semiconductor wafers with the adhesive layer made of different materials has a disadvantage that the adhesive layer material is diffused into the semiconductor when heated, or a compound is generated to cause alteration. These problems can be solved if the semiconductor wafers can be directly bonded to each other without the presence of foreign matter.

本発明者らは、鏡面研磨した半導体ウエハの研磨面同志
を親水性処理した後、清浄な雰囲気下で圧接することに
より、半導体ウエハ同志がきわめて強固に接合すること
を見出し、これを先に提案している(特公昭62−27
040号公報)。この方法によれば、事実上異物の介在
なしに半導体ウエハの接合体が得られる。
The present inventors have found that after the mirror-polished semiconductor wafers are subjected to hydrophilic treatment on the polished surfaces, and then pressure-bonded in a clean atmosphere, the semiconductor wafers are bonded to each other extremely strongly, and this is first proposed. Yes (Japanese Patent Publication No. Sho 62-27)
040 publication). According to this method, a bonded body of semiconductor wafers can be obtained with virtually no intervening foreign matter.

ところが、数インチという大きい径の半導体ウエハの接
合にこの方法を用いた場合、ウエハの反りなどの影響で
全面接着が非常に難しいことがわかつた。これは、接着
面の一部に残留ガスがとり残されることが主要な原因と
考えられる。
However, it has been found that when this method is used for bonding semiconductor wafers having a large diameter of several inches, it is very difficult to adhere the entire surface due to the influence of the warp of the wafer. The main reason for this is that residual gas is left behind on a part of the adhesive surface.

〔発明の目的〕[Object of the Invention]

本発明は、大面積の半導体ウエハ同志であつてもこれを
簡単かつ強固に接合することができる半導体ウエハの接
合方法を提供することを目的とする。
An object of the present invention is to provide a semiconductor wafer bonding method capable of easily and firmly bonding large-area semiconductor wafers.

〔発明の概要〕[Outline of Invention]

本発明は、2枚の半導体ウェハの表面を鏡面研磨し、少
なくとも一方の半導体ウェハの研磨面に、少なくとも一
端が半導体ウェハ周縁で開口し、接着面にガスが閉じ込
められないように通気道としての機能を有する溝を設け
て、これらの2枚の半導体ウェハの各研磨面同士を清浄
な条件下で密着させて直接接合することを特徴とする半
導体ウェハの接合方法である。なお、各研磨面は好まし
くは表面粗さ500Å以下とする。またこれらの研磨面
は接着させる前に水洗などの親水性処理、すなわち表面
状態をより親水性にするための処理をすることが好まし
い。
According to the present invention, the surfaces of two semiconductor wafers are mirror-polished, and at least one end is opened at the peripheral edge of the semiconductor wafer on the polished surface of at least one of the semiconductor wafers so that a gas can be prevented from being trapped in the bonding surface. A semiconductor wafer bonding method is characterized in that a groove having a function is provided, and the respective polishing surfaces of these two semiconductor wafers are brought into close contact with each other under clean conditions to directly bond them. The surface roughness of each polished surface is preferably 500 Å or less. Further, it is preferable to perform a hydrophilic treatment such as washing with water, that is, a treatment for making the surface condition more hydrophilic, before these polishing surfaces are bonded.

このように、半導体ウエハの接着すべき面に溝を設けて
おけば、接着時に空気などのガスが面内に閉じ込められ
て接着を妨げることがなく、大口径の半導体ウエハでも
確実に全面接着することができる。形成される溝の形や
本数、方向などは必要に応じて選択されるべきである。
比較的小口径の半導体ウエハであれば、例えば面内中央
で交差する十字線状の溝が使われるであろう。多数のペ
レツトを得る大口径のウエハに応用する場合には、将来
のスクライブラインに合わせて溝を形成するものも一方
法である。溝のピツチを細かくすると、接着は容易にな
るが、実質的な接着面積は当然小さくなる。溝の形成に
は、ダイヤモンドブレード,化学エツチングなどが使わ
れる。溝の深さには特に制限はないが、ウエハの厚みと
関係で余り深くするとこわれ易くなる。要するにこの溝
は、接着面にガスが閉じ込められないように通気道とし
ての機能を有すればよく、少くとも一端がウエハ周縁で
外部に開口していればよい。ガスが接着面内に閉じ込め
られると、一時的に強固に接着されたとしても、昇温に
よる内部のガス膨張により容易にはがれることになるか
らである。
Thus, by providing a groove on the surface of the semiconductor wafer to be bonded, a gas such as air is not trapped in the surface at the time of bonding and the bonding is not hindered, and the entire surface of the semiconductor wafer having a large diameter can be bonded reliably. be able to. The shape, number, direction, etc. of the formed grooves should be selected as needed.
If the semiconductor wafer has a relatively small diameter, for example, cross-shaped grooves intersecting at the center of the plane may be used. In the case of applying to a large-diameter wafer for obtaining a large number of pellets, one method is to form a groove in accordance with a future scribe line. If the pitch of the groove is made fine, the adhesion becomes easy, but the substantial adhesion area is naturally small. A diamond blade, chemical etching, or the like is used to form the groove. The depth of the groove is not particularly limited, but if it is too deep in relation to the thickness of the wafer, it is easily broken. In short, this groove has only to have a function as a ventilation passage so that gas is not trapped on the bonding surface, and at least one end thereof may be opened to the outside at the wafer peripheral edge. This is because if the gas is confined within the bonding surface, even if the gas is temporarily strongly bonded, it will be easily peeled off due to the gas expansion inside due to the temperature rise.

〔発明の効果〕〔The invention's effect〕

本発明によれば、広い面積の半導体ウエハ同志を実質的
に異物の介在なしに強固に接合することができる。得ら
れた半導体接合体は、異物が介在しないため例えば半導
体自体の耐熱温度まで加熱することができ、各種半導体
デバイスの製造に広く応用することができる。
According to the present invention, semiconductor wafers having a large area can be firmly bonded to each other substantially without any foreign matter. The obtained semiconductor bonded body can be heated to, for example, the heat resistant temperature of the semiconductor itself because no foreign matter is present, and can be widely applied to the manufacture of various semiconductor devices.

〔発明の実施例〕Example of Invention

(1)表面粗さ500Å以下に鏡面研磨された2インチ径
のn型(100)シリコンウエハ(厚さ600μm、比
抵抗1Ω−cm)を用意し、酸素中1100℃で30分処
理して、表面に6000Åの熱酸化膜を形成した。この
ウエハ表面にダイヤモンドブレードにより、深さ100
μm,幅40μmの溝を5mmピツチで格子状に形成し
た。次いで、フツ酸−硝酸−酢酸の混液で処理して破砕
層を除去した。次に40%フツ化アンモニウム液に浸漬
して酸化膜層を除去し、王水中で煮沸した後水洗した
(親水性化処理)した。
(1) Prepare a 2-inch diameter n-type (100) silicon wafer (thickness 600 μm, specific resistance 1 Ω-cm) mirror-polished to a surface roughness of 500 Å or less, and treat it in oxygen at 1100 ° C. for 30 minutes, A 6000Å thermal oxide film was formed on the surface. With a diamond blade, a depth of 100
Grooves having a width of 40 .mu.m and a width of 40 .mu.m were formed in a grid pattern with a pitch of 5 mm. Then, the crushed layer was removed by treating with a mixed solution of hydrofluoric acid-nitric acid-acetic acid. Next, it was immersed in a 40% ammonium fluoride solution to remove the oxide film layer, boiled in aqua regia and washed with water (hydrophilization treatment).

別に表面粗さ500Å以下に鏡面研磨された2インチ径
のn型(100)シリコンウエハ(厚さ300μm,比
抵抗60Ω−cm)を用意し、これを硫酸ー過酸化水素混
液で洗浄処理した。
Separately, a 2-inch diameter n-type (100) silicon wafer (thickness 300 μm, specific resistance 60 Ω-cm) mirror-polished to a surface roughness of 500 Å or less was prepared and washed with a sulfuric acid-hydrogen peroxide mixture solution.

この二枚のウエハを更に純水中で充分に洗浄した後、フ
レオン乾燥し、ゴミ浮遊量20個/cm3以下のクリーン
ルーム内で両者の研磨面(一方は溝が形成されている)
を直接接触させて圧迫した。この結果、強固なウエハ接
合体が得られた。
These two wafers are further thoroughly washed in pure water, then freon dried, and both polished surfaces (one is grooved) in a clean room with a dust floating amount of 20 / cm 3 or less.
Was directly contacted and pressed. As a result, a strong wafer bonded body was obtained.

この接合体を窒素中で1200℃まで加熱したが何の変
化も認められなかつた。また赤外顕微鏡で接合面を観察
した結果、溝部以外はボイドなしに接合されていること
が確認された。
The bonded body was heated to 1200 ° C. in nitrogen, but no change was observed. Further, as a result of observing the joint surface with an infrared microscope, it was confirmed that the joints were bonded without voids except the groove.

(2)2インチ径で比抵抗5Ω−cmのp型シリコンウエハ
とこれと同径で比抵抗1Ω−cmのn型シリコンウエハを
用意した。両者とも、一方の面が表面粗さ500Å以下
に鏡面研磨されており、厚さは400μmである。両ウ
エハの研磨面に3mmピツチで深さ40μm,幅100μ
mのすだれ状溝を化学エツチングにより形成した。この
エツチングのマスクにはホトレジストを用い、エツチン
グ液にはフツ酸−硝酸−酢酸の混液を用いた。これらの
ウエハを硝酸中で煮沸した後、水洗,乾燥し、クリーン
ルーム内で両者の研磨面を溝が互いに直交するように接
触させ、圧迫して接着した。
(2) A p-type silicon wafer having a diameter of 2 inches and a specific resistance of 5 Ω-cm and an n-type silicon wafer having the same diameter and a specific resistance of 1 Ω-cm were prepared. Both of them have one surface mirror-polished to have a surface roughness of 500 Å or less, and have a thickness of 400 μm. Polished surface of both wafers with 3mm pitch, depth 40μm, width 100μ
The m-shaped interdigital groove was formed by chemical etching. A photoresist was used as a mask for this etching, and a mixed solution of hydrofluoric acid-nitric acid-acetic acid was used as an etching solution. These wafers were boiled in nitric acid, washed with water, dried, and brought into contact with each other in such a manner that their polished surfaces were perpendicular to each other in a clean room, and pressed and bonded.

得られたウエハ接合体を窒素中で1100℃まで加熱し
た後、溝に沿つてダイヤモンドブレードで分割し、3mm
口のダイオードペレツトとした。いずれのダイオードペ
レツトも十分な整流特性を示した。
After heating the obtained wafer bonded body to 1100 ° C. in nitrogen, divide along the groove with a diamond blade to obtain 3 mm
It was a mouth diode pellet. All diode pellets showed sufficient rectification characteristics.

フロントページの続き (56)参考文献 特開 昭56−13773(JP,A) 特公 昭37−114(JP,B1) 特公 昭49−26455(JP,B1)Continuation of the front page (56) References JP-A-56-13773 (JP, A) JP-B 37-114 (JP, B1) JP-B 49-26455 (JP, B1)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】2枚の半導体ウェハの表面を鏡面研磨し、
少なくとも一方の半導体ウェハの研磨面に、少なくとも
一端が半導体ウェハ周縁で開口し、接着面にガスが閉じ
込められないように通気道としての機能を有する溝を設
けて、これらの2枚の半導体ウェハの各研磨面同士を清
浄な条件下で密着させて直接接合することを特徴とする
半導体ウェハの接合方法。
1. The surface of two semiconductor wafers is mirror-polished,
At least one end of the polishing surface of at least one semiconductor wafer is opened at the periphery of the semiconductor wafer, and a groove having a function as a ventilation path is provided on the bonding surface so that gas is not trapped. A method for joining semiconductor wafers, wherein the respective polished surfaces are brought into close contact with each other under clean conditions to be directly joined.
【請求項2】鏡面研磨面の表面粗さが500A以下であ
る特許請求の範囲第1項記載の半導体ウェハの接合方
法。
2. The method for bonding semiconductor wafers according to claim 1, wherein the mirror-polished surface has a surface roughness of 500 A or less.
【請求項3】前記2枚の半導体ウェハを密着させる前に
各研磨面に親水性処理を施すようにした特許請求の範囲
第1項記載の半導体ウェハの接合方法。
3. The method for joining semiconductor wafers according to claim 1, wherein each polishing surface is subjected to a hydrophilic treatment before the two semiconductor wafers are brought into close contact with each other.
JP58230336A 1983-12-06 1983-12-06 Method for joining semiconductor wafers Expired - Lifetime JPH061752B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58230336A JPH061752B2 (en) 1983-12-06 1983-12-06 Method for joining semiconductor wafers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58230336A JPH061752B2 (en) 1983-12-06 1983-12-06 Method for joining semiconductor wafers

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP28395494A Division JPH07169659A (en) 1994-10-25 1994-10-25 Method of joining semiconductor wafer

Publications (2)

Publication Number Publication Date
JPS60121715A JPS60121715A (en) 1985-06-29
JPH061752B2 true JPH061752B2 (en) 1994-01-05

Family

ID=16906240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58230336A Expired - Lifetime JPH061752B2 (en) 1983-12-06 1983-12-06 Method for joining semiconductor wafers

Country Status (1)

Country Link
JP (1) JPH061752B2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271214A (en) * 1985-09-25 1987-04-01 Toshiba Corp Jointing method for semiconductor substrate
US4837177A (en) * 1987-12-28 1989-06-06 Motorola Inc. Method of making bipolar semiconductor device having a conductive recombination layer
JP2685244B2 (en) * 1988-09-30 1997-12-03 株式会社日本自動車部品総合研究所 Method for manufacturing semiconductor device
US5164218A (en) * 1989-05-12 1992-11-17 Nippon Soken, Inc. Semiconductor device and a method for producing the same
JPH0361331U (en) * 1989-10-19 1991-06-17
JPH03283636A (en) * 1990-03-30 1991-12-13 Nippon Soken Inc Manufacture of semiconductor substrate
JPH05152263A (en) * 1991-11-25 1993-06-18 Mitsubishi Materials Corp One-face polishing method of silicon wafer by both-face polishing machine
WO1994023444A2 (en) * 1993-04-02 1994-10-13 Harris Corporation Bonded wafer processing with oxidative bonding
JPH07169659A (en) * 1994-10-25 1995-07-04 Toshiba Corp Method of joining semiconductor wafer
JP2976929B2 (en) * 1997-05-30 1999-11-10 日本電気株式会社 Method for manufacturing semiconductor device
KR20070071965A (en) * 2005-12-30 2007-07-04 삼성전자주식회사 Silicon direct bonding method
JP5434056B2 (en) * 2008-12-02 2014-03-05 株式会社Sumco Method for evaluating metal contamination of semiconductor substrates
US11491737B2 (en) * 2018-09-25 2022-11-08 Raytheon Company Robust method for bonding optical materials

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2926741C2 (en) * 1979-07-03 1982-09-09 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Field effect transistor and process for its manufacture

Also Published As

Publication number Publication date
JPS60121715A (en) 1985-06-29

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