JPH0361331U - - Google Patents
Info
- Publication number
- JPH0361331U JPH0361331U JP12274389U JP12274389U JPH0361331U JP H0361331 U JPH0361331 U JP H0361331U JP 12274389 U JP12274389 U JP 12274389U JP 12274389 U JP12274389 U JP 12274389U JP H0361331 U JPH0361331 U JP H0361331U
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- bonded
- substrate
- substrate according
- grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Weting (AREA)
Description
第１図Ａ乃至Ｅは本考案Ｓｉウエハ張り合わせ
基板の一実施例の製造工程図、第２図は本考案一
実施例に係る溝の形成状態を示す上面図、第３図
は本考案他の実施例に係る溝の形成状態を示す断
面図である。
1A to 1E are manufacturing process diagrams of an embodiment of the Si wafer bonded substrate of the present invention, FIG. 2 is a top view showing the groove formation state according to the embodiment of the present invention, and FIG. FIG. 3 is a cross-sectional view showing how grooves are formed according to an example.
Claims (1)
エハを、溝が形成された表面を張り合わせ面とし
て、基板に張り合わしてなることを特徴とするＳ
ｉウエハ張り合わせ基板。 (2) Ｓｉウエハに形成される溝は、複数である
ことを特徴とする請求項１記載のＳｉウエハ張り
合わせ基板。 (3) Ｓｉウエハを張り合わせる基板はＳｉ基板
であることを特徴とする請求項１または２記載の
Ｓｉウエハ張り合わせ基板。 (4) Ｓｉウエハを張り合わせる基板及びＳｉウ
エハの張り合わせる面夫々に、Ｓｉ酸化膜が形成
されていることを特徴とする請求項１，２または
３記載のＳｉウエハ張り合わせ基板。 (5) Ｓｉウエハに形成される溝は、Ｓｉウエハ
の端部から延設されていることを特徴とする請求
項１，２，３または４記載のＳｉウエハ張り合わ
せ基板。[Claims for Utility Model Registration] (1) An S characterized by being made by laminating a Si wafer with grooves of a predetermined depth on its surface to a substrate with the grooved surface serving as the lamination surface.
i-wafer bonded substrate. (2) The Si wafer bonded substrate according to claim 1, wherein a plurality of grooves are formed in the Si wafer. (3) The Si wafer bonded substrate according to claim 1 or 2, wherein the substrate to which the Si wafer is bonded is a Si substrate. (4) The Si wafer bonded substrate according to claim 1, 2 or 3, wherein a Si oxide film is formed on each of the substrate to which the Si wafer is bonded and the surface to which the Si wafer is bonded. (5) The Si wafer bonded substrate according to claim 1, wherein the groove formed in the Si wafer extends from an end of the Si wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12274389U JPH0361331U (en) | 1989-10-19 | 1989-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12274389U JPH0361331U (en) | 1989-10-19 | 1989-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0361331U true JPH0361331U (en) | 1991-06-17 |
Family
ID=31670736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12274389U Pending JPH0361331U (en) | 1989-10-19 | 1989-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0361331U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008233473A (en) * | 2007-03-20 | 2008-10-02 | Ntt Electornics Corp | Manufacturing method of thin film panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60121715A (en) * | 1983-12-06 | 1985-06-29 | Toshiba Corp | Bonding method for semiconductor wafer |
| JPS61144839A (en) * | 1984-12-18 | 1986-07-02 | Toshiba Corp | Bonding method for semiconductor wafer |
| JPS62101031A (en) * | 1985-10-28 | 1987-05-11 | Nec Corp | Integrated circuit |
-
1989
- 1989-10-19 JP JP12274389U patent/JPH0361331U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60121715A (en) * | 1983-12-06 | 1985-06-29 | Toshiba Corp | Bonding method for semiconductor wafer |
| JPS61144839A (en) * | 1984-12-18 | 1986-07-02 | Toshiba Corp | Bonding method for semiconductor wafer |
| JPS62101031A (en) * | 1985-10-28 | 1987-05-11 | Nec Corp | Integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008233473A (en) * | 2007-03-20 | 2008-10-02 | Ntt Electornics Corp | Manufacturing method of thin film panel |
| JP4567015B2 (en) * | 2007-03-20 | 2010-10-20 | Ｎｔｔエレクトロニクス株式会社 | Thin film substrate manufacturing method |