JPH06168115A - No operation continuing step intructing system for arithmetic processor - Google Patents

Abstract

PURPOSE:To continue no operation processing for a certain time without being affected by the processing speed of an arithmetic processor. CONSTITUTION:An instruction code analyzing part 11 analyzes an instruction code, and an arithmetic clock counting part 12 controls the execution of no operation continuing step by the analysis result. A clock part 15 generates a standard clock for the operation of the arithmetic clock counting part 12. An arithmetic processor peculiar information setting and holding part 14 holds information peculiar to the arithmetic processor, and an execution part 13 is the execution part of the arithmetic processor. Thus, it is unnecessary to correct the timings of the arithmetic processor and an input/output device even if the capability of the arithmetic processor is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processor non-operation continuation step instruction system for continuing non-operation processing for a certain period without being affected by the processing speed of the arithmetic processor.

[0002]

2. Description of the Related Art Conventionally, this type of arithmetic processor has an instruction with no arithmetic step. Then, this non-operation step does not perform any processing other than updating the execution point of the operation processor to the next instruction. This instruction set is used for adjusting the timing of the loop or for timing with the input / output device.

[0003]

In the instruction set with no operation step of the conventional arithmetic processor, the timing time depends on the execution ability of the arithmetic processor. Therefore, even if the same external circuit is used, the ability of the arithmetic processor is reduced. There was a problem that it was necessary to review the input / output timing of all programs for improvement.

[0004]

In the arithmetic processor non-operation continuous step instruction system of the present invention, an instruction code analysis unit for analyzing an instruction code input from the outside and an execution result non-operation continuous step are controlled according to the analysis result. Of the operation clock count unit, a clock unit that generates information for operating the operation clock count unit, an operation processor unique information setting holding unit that holds operation processor unique information, and an operation processing of the operation processor. And an execution unit section which is an execution section for executing.

The clock unit may generate a standard clock from a reference time generated externally or internally.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of an arithmetic processor no-operation continuation step instruction system of the present invention, and FIG. 2 is a diagram showing a no-operation continuation instruction code format in this embodiment.

In this embodiment, as shown in FIG. 1, an instruction code analyzer 11 for analyzing an instruction code input from the outside.
And an arithmetic clock count unit 12 for controlling execution of the non-calculation continuation step based on the analysis result, a clock unit 14 for generating information for operating the arithmetic clock count unit 12, and arithmetic processor specific information. An arithmetic processor unique information setting holding unit 14 and an execution unit unit 13 that is an execution unit that executes arithmetic processor arithmetic processing are provided.

Next, the processing operation in this embodiment will be described with reference to FIG.

When the arithmetic processor of this embodiment shifts to a state in which instructions can be executed, the instruction code analysis unit 11 which analyzes an instruction code input from the outside requests the instruction code from the outside.

When the instruction code is read into the instruction code analysis unit 11 from the outside, the instruction code analysis unit 11 analyzes the instruction code to identify whether it is a normal operation instruction code or a non-operation continuation instruction code. .

When the instruction code analysis unit 11 recognizes that it is a no-operation continuation instruction code, the operation clock count unit 12 for controlling the execution of the no-operation continuation instruction code.
It provides the time order parameter, which is a numerical parameter, and the set time of the time counter, and requests the execution of the no-operation continuation instruction code.

Operation clock count unit 1 that receives a request
In order to measure the duration of the non-calculation process, 2 initializes the internal clock count and requests the execution unit section 13 to suspend the process.

At the same time, the arithmetic clock count unit 12 obtains the relationship between the unit time of arithmetic processing and the reference clock information from the clock unit 15 from the arithmetic processor unique information setting holding unit 14 that manages the unique information of the arithmetic processor. , The number of times in the actual arithmetic processing specified by the no-operation continuation instruction code from the set time configured by the obtained information and the second parameter of the no-operation continuation instruction code, the time order parameter and the time counter. It is calculated whether it corresponds to the processing unit of the number of clocks.

Then, the calculated clock number is stored in the operation clock count unit 12.

By executing the non-operation processing of the number of clocks, the time specified by the non-operation continuation instruction code can be consumed.

Further, the operation clock count unit 12 provides a standard provided from the clock unit 15 which generates a standard clock for timing execution of operation processing from the time when the execution unit unit 13 is requested to interrupt the processing. Start clock counting.

After that, the clock count in the arithmetic clock count unit 12 is updated each time the clock information, which is the reference of the arithmetic processing timing, is notified from the clock unit 15.

At the time of this update, the number of clocks required for processing the set time of the no-calculation continuation instruction calculated based on the arithmetic processor unique information setting holding unit 14 and the clock count in the arithmetic clock count unit 12 are compared. When the clock count values match, that is, when the counting of the set time amount specified by the time order parameter and the time counter, which is the second parameter of the no-operation continuation instruction code, is completed, the operation clock count The unit 12 requests the execution unit unit 13 to re-execute the arithmetic processing execution.

At this time, the operation clock count unit 12 notifies the instruction code analysis unit 11 that the execution of the no-operation continuing instruction code for the set time is completed. The instruction code analysis unit 11 that has received the notification requests the next operation instruction code to the outside in order to analyze the next operation instruction.

In this embodiment, the clock unit 15 may use either the reference time input from the outside or the reference time generated internally when generating the standard clock.

Next, the non-operation continuation instruction code format will be described with reference to FIG.

The no-operation continuation instruction code is composed of a first parameter and a second parameter.

The first parameter is a no-operation continuation instruction code. This non-operation continuation instruction code is a code that can be distinguished from other operation instructions. The execution control can be transferred to the operation clock / counter 12 by recognizing the non-operation continuation instruction code.

It is to be noted that the second parameter is used next by the first parameter.
Means that the parameter time order parameter and the time counter follow.

The second parameter of the no-operation continuation instruction code is a variable parameter value for setting the no-operation continuation time in the no-operation continuation instruction code.

The second parameter is divided into a time order parameter and a time counter. The time order parameter is used to specify the time order unit. This order parameter sets the unit order such as millisecond and microsecond.

The time counter indicates the count value on the order set by the time order parameter.

Since the second parameter is not simply the time counter value, the order of the processing time of the input and output is different from the unit of the order of the arithmetic processing time, and it is necessary to generate a time much longer than the unit processing time of the arithmetic processing.

Further, the storage device or the like needs to generate time in units of the calculation processing time order, and it is necessary to set the non-calculation continuation time in a wide range.

By changing the time order parameter of the second parameter and the value of the time counter, an arbitrary time can be created. If the second parameter is only the time counter, the second parameter is compared to the second parameter.
It is possible to prevent the code length of the parameter from increasing.

[0032]

As described above, according to the arithmetic processor no-operation continuous step instruction system of the present invention, the no-operation time independent of the capacity of the arithmetic processor can be set by adding the instruction set of the no-operation continuous step. .

Therefore, even if the capacity of the arithmetic processor is improved, it is not necessary to reexamine the timing of the affected loop and the timing with the input / output device.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of an arithmetic processor non-operation continuous step instruction system of the present invention.

FIG. 2 is a diagram showing a no-operation instruction code format in the present embodiment.

[Explanation of symbols]

 11 instruction code analysis unit 12 operation clock / count unit 13 execution unit unit 14 arithmetic processor unique information setting holding unit 15 clock unit

Claims (2)

[Claims] 1. An instruction code analyzing section for analyzing an instruction code input from the outside, an operation clock counting section for controlling execution of a non-operation continuing step based on the analysis result, and the operation clock counting section operate. A processor for generating information for a processor, a processor specific information setting holder for storing processor specific information, and an execution unit for executing processing of the processor. Continuous step instruction method. 2. The arithmetic processor non-operation continuous step instruction method according to claim 1, wherein the clock unit generates a standard clock from a reference time generated externally or internally.