JP2001166954A - Virtual computer device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely hold an inside clock by holding cyclic timer interruption, and then by generating it in a prescribed cycle. SOLUTION: This virtual computer device is provided with a main storage, a CPU, a timer interruption generating device 12 for generating timer interruption in a set cycle, and a hardware division controlling part 13 so that hardware including the main storage and the CPU can be logically divided and controlled. The hardware division controlling part 13 is provided with an interruption counter 17 for a first OS for counting timer interruption in the switching cycle of the first OS, an interruption counter 18 for a second OS for counting timer interruption in the switching cycle of the second OS, and a pseudo timer interruption cycle preserving part 19 for preserving a pseudo timer interruption cycle calculated by dividing the operating period of each OS by the counted value of each interruption counter. Then, when the CPU operates the OS, the pseudo timer interruption is generated in the cycle preserved in the pseudo timer interruption cycle preserving part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a virtual machine, and more particularly, to a virtual machine capable of operating two or more OSs.

[0002]

2. Description of the Related Art In a personal computer, usually only one OS operates in one computer. The OS includes a timer interrupt generator, and the timer interrupt generator generates a timer interrupt according to a set cycle. When such a timer interrupt generation device is used, once a cycle is set, a timer interrupt is automatically generated according to the cycle thereafter, so that the timer interrupt control program of the OS can be simplified.

On the other hand, as for the mainframe, Japanese Patent Laid-Open No. 06-103092 (virtual computer system)
It shows that a computer device is divided to form a virtual computer in one computer device, and the computer device is operated more effectively. As a division of a computer device, a physical division for physically dividing and a logical division for logically dividing are known. Since the logical partitioning is shared between virtual computer devices formed by dividing hardware such as a CPU, the sharing method is important.

Japanese Patent Application Laid-Open No. 06-187178 (input / output timer interrupt of a virtual machine system) discloses that in the mainframe, an interrupt cycle is sequentially changed in an interrupt processing program for each OS in an interrupt processing program to efficiently process an interrupt. It is shown to be.

Japanese Patent Application Laid-Open No. 08-263416 (an input / output processing method and processing system using an integrated mechanism) is provided with a device for sequentially processing generated interrupts, and by controlling this device, It has been shown that timer interrupts are handled efficiently.

[0006]

However, it is difficult to apply the technology disclosed in the above publication, that is, the technology applied to the mainframe, to a virtual computer system that operates a plurality of OSs on a personal computer.

That is, many personal computers have a common architecture, and an OS operating on the common architecture
Is designed on the basis of those architectures, and does not consider changing the timer interrupt cycle one by one or controlling additional devices. For this reason, the method of controlling the interrupt by sequentially changing the interrupt cycle of the timer interrupt used in the mainframe requires a significant change of the existing OS. Further, it is necessary to change the interrupt cycle for each interrupt.

In addition, the method of adding a device for sequentially processing generated interrupts changes the common architecture of a personal computer, and its application range is significantly narrowed.

That is, it is difficult to apply a timer interrupt control method used in a mainframe to an existing OS operating on a personal computer.
For this reason, it is also difficult to hold the internal clock accurately.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a virtual computer and a virtual computer capable of holding an internal clock accurately by suspending a periodic timer interrupt or measuring real time. An apparatus control method is provided.

[0011]

The present invention employs the following means in order to solve the above-mentioned problems.

A virtual machine which includes a main memory, a CPU, a timer interrupt generating device for generating a timer interrupt at a set cycle, and a hardware division control unit, and which logically divides and controls the hardware including the main storage and the CPU; In the apparatus, a first O is provided to the hardware division control unit.
A first OS interrupt counter for counting a timer interrupt or a timer interrupt queue within a switching cycle of S; a second OS interrupt counter for counting a timer interrupt or timer interrupt queue within a second OS switching cycle; A pseudo timer interrupt period storage unit for storing a pseudo timer interrupt period obtained by dividing the operation period of each OS by the count value of each interrupt counter, and when the CPU is operating the OS,
By generating a pseudo timer interrupt at the cycle stored in the pseudo timer interrupt cycle storage section, the internal clock is accurately held. Further, the timer interrupt can be replaced with a timer interrupt queue or an I / O interrupt.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a virtual machine device according to the present embodiment. In the figure, 1
0 is a main storage device, and 11 is a CPU. Reference numeral 12 denotes a timer interrupt generation device which periodically generates a timer interrupt signal and inputs it to the CPU 11. Reference numeral 13 denotes a hardware division control unit, which logically divides the hardware into a plurality of Os
S is appropriately assigned. 14 is the first memory formed in the main memory 10
OS (OS1) 15 is the second OS formed in the main memory 100.
OS (OS2) 16 is an interrupt control unit, which generates a timer interrupt for the operating OS. A timer interrupt counter 17 for the first OS counts the operating cycle of the first OS. Reference numeral 18 denotes a timer interrupt counter for the second OS, which counts the operating cycle of the first OS. A pseudo timer interrupt period storage unit 19 stores the pseudo period of the timer interrupt supplied to the first or second OS, and the operating period of the operating OS.
Divided by the count value of the timer interrupt counter for
The obtained pseudo timer interrupt cycle is stored. Reference numeral 20 denotes a timer interrupt processing unit for the first OS, which updates an internal clock. Reference numeral 21 denotes a timer interrupt processing unit for the second OS, which updates an internal clock and the like. Reference numeral 22 denotes an internal bus, which connects the CPU 11 and the main storage device 10.

FIG. 2 is a flowchart for explaining the processing performed by the hardware division control unit 13. First step 2
At 00, it is determined whether or not a timer interrupt by the timer interrupt generation device 12 has occurred. If a timer interrupt has occurred, the process proceeds to step 201; otherwise, the loop process ends. In step 201,
All the OS counters, that is, the first OS timer interrupt counter 17 and the second OS timer interrupt counter 18 are incremented, and the routine proceeds to step 210.

In step 210, it is determined whether it is time to switch the OS. If it is time to switch the OS, the process proceeds to step 211; otherwise, the process proceeds to step 220. In step 211, the corresponding O
The switching process to S is performed. In other words, the currently running OS
Is stopped, and hardware such as a CPU is reassigned to the next OS. In step 212, the pseudo timer interrupt cycle is calculated by the pseudo timer interrupt cycle = the operating time of the OS / counter value of the timer interrupt counter, and the obtained pseudo timer interrupt cycle is stored in the pseudo timer interrupt cycle storage unit 19. save. In step 213,
The count value of the timer interrupt counter is reset, and the loop processing ends.

In step 220, it is determined whether the pseudo timer interrupt period stored in the pseudo timer interrupt period storage unit 19 has elapsed. If the pseudo timer interrupt period has elapsed, the process proceeds to step 221; otherwise, the loop process ends. In step 221, the current CPU state is saved. In step 222, the CPU is set to a state in which a timer interrupt has been generated in a pseudo manner. At step 223, the timer interrupt processing unit of the currently operating OS (the currently operating OS
If it is 1, the timer interrupt processing unit 20 and the currently operating O
If S is OS2, the timer interrupt processing unit 21) is called.

Here, the timer interrupt processing units 20 and 21
Performs processing such as updating the internal clock. The process of updating the internal clock can be performed by adding a timer interrupt during which the OS is not operating to the internal clock. That is, since the pseudo timer interrupt occurs the same number of times as the actual timer interrupt within the predetermined time, the internal clock can be held accurately. Further, the timer interrupt processing units 20 and 21 return the processing to the interrupt control unit 16 when the respective processing is completed.

In step 224, the interrupt control unit 16 whose processing has been returned performs post-processing such as restoring the CPU state saved in step 221 and then ends the loop processing.

As described above, each time a timer interrupt occurs, the timer interrupt counter provided for each OS is incremented, and while the CPU is operating the corresponding OS, the timer interrupt corresponding to the counter is simulated. generate. In this method, the time and interval of the timer interrupt generated for the OS are different from the actual time and interval of the timer interrupt. However, since the number of timer interrupts generated in the OS within a certain time can be kept equal to that before logical division, it is not necessary to correct the OS for timer interrupts during logical division. On the other hand, the interval between timer interrupts to the OS is shorter than that before logical division. However, considering that the actual timer interrupt processing time of the OS accounts for a small percentage of the entire processing time, the possibility of a timer interrupt being missed is low. Low. That is, although the timer interrupt may be missed, the frequency can be kept extremely low.

As described above, according to the present embodiment,
The interrupt control unit 16 can generate a timer interrupt for the currently operating OS at an arbitrary cycle, and can generate a periodic timer interrupt for each OS without changing the OS.

FIG. 3 is a diagram showing a modification of the virtual machine shown in FIG. In the figure, 12a is an I / O interrupt generator, 17a is an I / O interrupt counter for the first OS, and 18a is an I / O interrupt counter for the second OS. In the drawing, the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

As described above, the I / O interrupt generator 12a shown in FIG. 3 can be used instead of the timer interrupt generator 12 shown in FIG. In this case, instead of the interrupt counters 17 and 18 shown in FIG. 1 provided for each OS, I / O interrupt counters 17a and 18a as shown in FIG.
Is used. In the case of this example, for example, at the time of keyboard input, the timing of keyboard input and the timing of character display can be matched.

FIG. 4 is a diagram showing another modified example of the virtual machine shown in FIG. In the figure, 17b is a timer interrupt queue for the first OS, and 17b is a timer interrupt queue for the second OS. In the case of this example, load information such as the CPU state at the time of interruption can be inserted into the queue itself. In the drawing, the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

FIGS. 5 and 6 are views showing a second embodiment of the present invention. In FIG. 5, reference numeral 23 denotes an internal clock formed by software in the first OS, which is updated and adjusted by the timer interrupt processing unit 20. Reference numeral 24 denotes an internal clock formed by software in the second OS, which is updated and adjusted by the timer interrupt processing unit 21. 25 is a real-time measuring device. In the drawing, the same portions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 6 is a flowchart for explaining processing performed by the hardware division control unit 13 and the timer interrupt processing units 20 and 21. First, in step 300, it is determined whether or not a timer interrupt has occurred by the timer interrupt generation device 12. If a timer interrupt has occurred, the process proceeds to step 301; otherwise, the process proceeds to step 310. In step 301, the currently operating OS, that is, the first OS or the second OS
A normal timer interrupt is notified to any of
In step 302, the processing is shifted to the timer interrupt control unit of the operating OS. In step 303,
The real time is read from the real time measuring unit 25. Step 30
At 4, the real time read is notified to the internal clock, and the internal clock is adjusted. In step 305, normal timer interrupt processing is executed, and the loop processing ends.
In step 310, it is determined whether it is time to switch the OS. If it is time to switch the OS, the process proceeds to step 311; otherwise, the loop process ends. In step 311, a process for switching to the corresponding OS is performed, and the loop process ends. That is, the currently running OS is stopped, and hardware such as the CPU is replaced with the next OS.
And the loop processing ends.

In the steps 303 to 304, the real time is read from the real time measuring unit 25, and the internal clock is adjusted using the read real time. The internal clock can also be adjusted by measuring the elapsed time and adding this time to the internal clock.

As described above, when a timer interrupt occurs, only the currently operating OS is notified of the timer interrupt, and each time the actual time is substituted into the internal clock of the OS, an accurate time is maintained. This method reduces the number of timer interrupts, but every time a timer interrupt occurs, the OS
The internal clock is adjusted according to the real time, so that the internal clock is not delayed.

In the above description, an example in which the first and second OSs are operated while being switched is shown. However, the number of OSs can be an arbitrary number of two or more.

The hardware division control unit, the OS, the timer interrupt processing unit, and the internal clock configured on the main storage device can be formed by software. Further, the processing performed by the hardware division control unit can be executed by software as shown in the above-described flowchart. Therefore, the present invention can be implemented by a computer-readable recording medium recording such software.

[0030]

As described above, according to the present invention, a periodic timer interrupt is suspended and then generated at a predetermined period, or a real time is measured and supplied to an internal clock. The internal clock can be maintained accurately.

[Brief description of the drawings]

FIG. 1 is a diagram showing a virtual machine according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a process performed by a hardware division control unit.

FIG. 3 is a diagram showing a modification of the virtual machine shown in FIG.

FIG. 4 is a diagram illustrating another modified example of the virtual machine illustrated in FIG. 1;

FIG. 5 is a diagram illustrating a virtual machine according to a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating processing performed by a hardware division control unit and a timer interrupt control unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 CPU 12 Timer interrupt generator 12a I / O interrupt generator 13 Hardware division control unit 14 First OS 15 Second OS 16 Interrupt control unit 17 First OS timer interrupt counter 17a First OS I / O interrupt counter 17b First OS timer interrupt queue 18 Second OS timer interrupt counter 18a Second OS I / O interrupt counter 17b Second OS timer interrupt queue 19 Pseudo timer interrupt cycle storage 20 Timer interrupt processing unit for first OS 21 Timer interrupt processing unit for second OS 22 Internal bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoko Kaku 5030 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Software Division, Hitachi, Ltd. 5B098 BA04 GA02 GAH HH04

Claims (5)

[Claims] 1. A main memory, a CPU, a timer interrupt generation device for generating a timer interrupt at a set cycle, and a hardware division control unit, wherein hardware including the main storage and the CPU are logically divided and controlled. In the virtual machine device, the hardware division control unit includes: a first OS interrupt counter for counting a timer interrupt or a timer interrupt queue within a first OS switching cycle; and a timer within a second OS switching cycle. A second OS interrupt counter for counting an interrupt or a timer interrupt queue; and a pseudo timer interrupt period storage for storing a pseudo timer interrupt period obtained by dividing the operating period of each OS by the count value of the respective interrupt counter. Part,
A virtual machine device wherein a pseudo timer interrupt is generated at a period stored in the pseudo timer interrupt period storage unit when a CPU operates an OS. 2. A main memory, a CPU, and I / O at a set cycle.
A virtual machine device comprising: an I / O interrupt generation device that generates an interrupt; and a hardware division control unit, wherein the hardware including the main storage and the CPU is logically divided and controlled, wherein the hardware division control unit comprises: A first OS interrupt counter that counts I / O interrupts within the first OS switching cycle, a second OS interrupt counter that counts I / O interrupts within the second OS switching cycle, A pseudo timer interrupt period storage unit for storing a pseudo timer interrupt period obtained by dividing the operating period of each OS by the count value of each interrupt counter;
A virtual machine device wherein a pseudo timer interrupt is generated at a period stored in the pseudo timer interrupt period storage unit when a CPU operates an OS. 3. A system comprising a main memory, a CPU, a timer interrupt generation device for generating a timer interrupt at a set cycle, a real-time measurement device, and a hardware division control unit, wherein the hardware is logically divided. A plurality of OSs each having an internal clock and operating a timer interrupt by the timer interrupt generation device.
A real-time measuring device that notifies the real-time measuring device and the elapsed time from the previous interrupt to the internal clock of the operating OS to correct the internal clock of the OS. 4. A main memory, a CPU, a timer interrupt generation device for generating a timer interrupt at a set cycle, and a hardware division control unit, wherein hardware including the main storage and the CPU are logically divided and controlled. A method for controlling a virtual machine, comprising: a first OS interrupt counter for counting a timer interrupt or a timer interrupt queue within a first OS switching cycle; and a timer interrupt or timer interrupt queue within a second OS switching cycle. A second OS interrupt counter that counts the number of times, and a pseudo timer interrupt period storage unit that stores a pseudo timer interrupt period obtained by dividing the operating period of each OS by the count value of the respective interrupt counter, When the CPU is operating one OS, the pseudo timer interrupt A pseudo timer interrupt is generated in the one OS at the period stored in the storage unit, and when the CPU is operating the other OS, the other OS is generated at the period stored in the pseudo timer interrupt period storage unit. Generating a pseudo timer interrupt in a virtual machine device. 5. A plurality of units each comprising a main memory, a CPU, a timer interrupt generating device for generating a timer interrupt at a set cycle, a real time measuring device, and a hardware division control unit, wherein the hardware is logically divided. A timer interrupt control method of a virtual machine controlling an OS of the virtual machine, wherein each of the plurality of OSs has an internal clock, and the OS is operating a timer interrupt by the timer interrupt generator.
And the processing is shifted to the interrupt processing unit. Then, the real time measured by the real time measuring device or the elapsed time from the previous interrupt is supplied to the internal clock of the operating OS, and
A method for controlling a virtual machine device, wherein the internal clock of S is adjusted.