JPH06164369A - Integrated semiconductor circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a detecting circuit and further to decrease the layout area by employing simple constitution for the detecting circuit which detects the use state of the circuit. CONSTITUTION:A detecting circuit part 40 is composed of a transistor(TR) for detection connected to the emitter of a TR Q1 for an external input emitter follower. The base of the TR Q1 is connected to an external input terminal IN and the output terminal of the TR for detection is connected to a control circuit 20. The use state of the circuit is determined depending upon whether or not an input signal source is connected to the external input terminal IN and the TR for detection receives variation of an emitter current based upon whether or not there is the base current of the TR Q1, detects whether or not the input signal source is connected to the external input terminal IN from an accompanying change in the operation state of the TR for detection, and outputs the detection output from the output terminal to a control circuit part 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having a power consumption reducing function. In recent years, there has been a demand for low power consumption in circuits with large power consumption, such as an interface section connecting a CPU (central processing unit) and an external storage device (for example, a disk system). Therefore, various methods are provided, but it detects the usage status of the circuit, lowers the bias voltage when the circuit is not in use to create a standby state, and reduces power consumption when the usage and non-use are integrated. One of the effective methods is Therefore, the use state of the logic circuit is detected by the detection circuit, and the bias voltage of the non-use circuit is set to a low potential to reduce the power consumption.
Miniaturization is demanded.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a semiconductor integrated circuit having a conventional detection circuit. As shown in the figure, the conventional semiconductor integrated circuit includes transistors Q1 and Q3.
To Q5, Q22, Q23, resistors R1, R2, R31, reference voltage generating circuit 50, external input terminal IN, logic circuit section 10, and control circuit section 20 including transistors Q6 to Q8, Q24 and resistors R4 to R6. , A sub-bias circuit section 31 including a transistor Q9 and resistors R7 and R8
And the main bias circuit section 32 including the transistors Q9 to Q14 and the resistors R9 to R13, and the detection circuit section 40 serving as an input buffer overlaps with a part of the logic circuit section 10, and the transistors Q1 and Q22 and the resistors are included. R31
And a reference voltage generating circuit 50. Vcc is a high potential power supply, Vee is a low potential power supply, Vcs is a bias voltage output from the sub bias circuit unit 31, and Vref is a reference voltage of the logic circuit unit 10. IN is an external input terminal, and the logic circuit unit 10 is connected to the external input terminal IN.
The input signal source, which is a logic signal having two different voltage levels, is connected and supplies the base current of the transistor Q1 only when the above operation is required. On the other hand, when the operation of the logic circuit unit 10 is not required, the external input terminal IN
The input signal source is not connected to and is open.

Further, the main bias circuit section 32 is
It is a bandgap circuit that can obtain a temperature-compensated output. The current source transistor Q3 in the logic circuit section 10 receives the Vcs as a base bias voltage and drives it as a current source of an ECL (Emitter Coupled Logic) circuit including a transistor Q4 and a transistor Q5.

Next, the operation will be described with reference to FIG. In this conventional semiconductor device, when the logic circuit section 10 is not used, that is, when the input signal source is not connected to the external input terminal IN, the transistor Q1 in the detection circuit section 40 is turned off and the transistor Q22 is turned off. Turns on. Therefore, the current i16 flows, and the control circuit unit 2
The potential at the point M, which is the base voltage of the transistor Q24 in 0, decreases. Then, since the potential at the point A, which is the base voltage of the pnp-type transistor Q6, decreases, the transistor Q6
6 is turned on, and the current i2 flowing through the transistor Q7 in the control circuit unit 20 increases. Since the transistors Q7 and Q8 are mirror circuits, the drive current increases, and the current i3 flowing through the transistor Q8 increases.

As the current i3 increases, the potential at the point B that determines the potential of the bias voltage Vcs decreases. Therefore, the current source transistor Q3 in the logic circuit unit 10 is
The electric potential of the base voltage is decreased, the current Ics flowing in the logic circuit unit 10 is decreased, and the power consumption is reduced. When the logic circuit unit 10 is used, that is, the input signal source is connected to the external input terminal IN, the transistor Q
When the base current of 1 is supplied, the transistor Q1 in the detection circuit unit 40 is turned on and the transistor Q22 is turned off. Therefore, the current i1
6 does not flow, and the potential at point M, which is the base voltage of the transistor Q24 in the control circuit section 20, rises. And pnp
Since the potential at the point A, which is the base voltage of the transistor Q6 of the mold, rises, the transistor Q6 is turned off, and the current i2 in the control circuit unit 20 decreases. Therefore, the mirror circuit including the transistor Q7 and the transistor Q8 does not operate, and the current i3 also decreases. Therefore, the potential at the point B, which determines the potential of the bias voltage Vcs, becomes the level at the time of normal operation, the current source transistor Q3 is turned on, and the logic circuit unit 10 performs normal operation.

[0006]

As described above, in the conventional example, when the logic circuit unit 10 is not used, the logic circuit unit 10 is not used.
Power consumption can be reduced. However, in the above-mentioned conventional example, the reference voltage generating circuit 50 is required because the ECL circuit is used in the detection circuit section 40. The reference voltage supplied by the reference voltage generation circuit 50 should not affect the input signal input to the external input terminal IN. That is, it is necessary to have a sufficient margin for the "Low" level signal of the logic signal input to the external input terminal IN, and also a sufficient margin with respect to Vcs. Therefore, a highly accurate bias circuit is required to provide the margin under all circuit use conditions.

In other words, the reference voltage generation circuit 50 requires a complicated circuit, which causes a problem that the circuit area becomes large. Further, since the reference voltage generation circuit 50 in the detection circuit unit 40 always consumes current, the detection circuit unit 40 always consumes power regardless of whether the circuit is used or not, which is wasteful. There is a problem that power consumption is increased.

The present invention provides a semiconductor integrated circuit in which power consumption is reduced by detecting a usage state of a logic circuit by a detection circuit having a small power consumption and a small circuit area and setting a bias voltage of an unused circuit to a low potential. The purpose is to provide.

[0009]

FIG. 1 is a principle configuration diagram of a semiconductor integrated circuit of the present invention. In the figure, 10 is a logic circuit section, 20 is a control circuit section, 30 is a bias circuit section,
40 is a detection circuit unit, IN is an external input terminal, Vcc
Is a high potential power source, Vee is a low potential power source, and Vcs is a bias voltage. Vref is a reference voltage of the ECL circuit including the transistor Q4 and the transistor Q5.

In the semiconductor integrated circuit of the present invention, a current source transistor Q3 connected to the emitter side of a transistor pair Q4 and Q5 having a common emitter, and an emitter connected to the base of one transistor of the transistor pair Q4 and Q5. Emitter follower transistor Q1
Of the detection circuit unit 40, the bias circuit unit 30 for applying the bias voltage Vcs to the base of the current source transistor Q3, the detection circuit unit 40 connected to the emitter of the emitter follower transistor Q1, and the detection circuit unit 40. A control circuit unit 2 that receives the detection output, determines the bias voltage Vcs, and controls the driving state of the current source transistor Q3.
It has 0 and.

To the base of the emitter follower transistor Q1, logic signals having two different voltage levels are input as input signals when the circuit is active. The base current of the emitter follower transistor Q1 changes depending on whether or not the external input terminal IN is connected to the input signal source, and thus the emitter current is controlled. The detection circuit unit 40 includes a detection transistor whose collector is connected to the emitter of the emitter follower transistor Q1. The detection transistor receives the change in the emitter current of the emitter follower transistor Q1 as a change in the collector current, and the detection transistor is detected. The presence / absence of the saturation state of (1) is used to detect the presence / absence of an input signal to the base of the emitter follower transistor Q1, and output the control signal to the control circuit unit 20 with a change in the base current of the detection transistor.

Alternatively, the emitter-follower transistor Q1 may include a detection transistor whose base is connected to the emitter, and the detection transistor receives a change in the emitter current of the emitter-follower transistor Q1 as a change in the base current, and the detection transistor accordingly. Whether the input signal is input to the base of the emitter follower transistor Q1 is detected by the on / off state of the transistor,
It is characterized in that the change in the collector current of the detection transistor is output to the control circuit unit 20.

Alternatively, in the detection circuit section 40 and the control circuit section 20, the collector is an emitter follower transistor Q.
1 and a detection transistor connected to the bias circuit section 30, and a control transistor whose base is connected to the base of the detection transistor and whose base and collector are common and through which a constant drive current flows. It is composed of a mirror circuit. The detection transistor in the mirror circuit detects whether or not an input signal is input to the base of the emitter follower transistor Q1 by the change in the collector current that accompanies the change in the emitter current of the emitter follower transistor Q1. The change in the emitter current of the emitter follower transistor Q1 is compensated by the current flowing from the bias circuit unit 30 so as to keep the flowing current constant, and the current flowing in the bias circuit unit 30 is controlled. It is characterized in that the drive state of the current source transistor Q3 is controlled by determining the potential of the point which becomes the potential of the bias voltage Vcs.

Another aspect of the present invention is that the bias circuit section 30 includes a main bias circuit section including a bandgap circuit for obtaining an output whose temperature is compensated, and a current source transistor with reference to the output of the main bias circuit section. The sub-bias circuit unit generates the bias voltage Vcs of Q3,
The semiconductor integrated circuit is characterized in that the control circuit unit 20 controls the sub-bias circuit unit to control the output bias voltage Vcs.

Further, the logic circuit section 10 and the detection circuit section 4
0, the control circuit section 20 and the sub-bias circuit section as a unit series, and a plurality of series circuit groups and one common main bias circuit section.
0 determines the output of the sub-bias circuit unit, and each sub-bias circuit unit is connected to the main bias circuit unit and outputs the bias voltage Vcs with reference to the output of the main bias circuit unit. It is an integrated circuit.

[0016]

According to the semiconductor integrated circuit of the present invention, the bias voltage Vcs can be set to a low potential when the circuit is not used, and power consumption can be reduced. Moreover, the use state of the logic circuit section 10 depends on whether the input signal source is connected to the external input terminal IN, that is, whether the external input emitter follower transistor Q1 is activated or not in the detection circuit section 40. The change is detected in the emitter current of the transistor Q1, and the detection output is output to the control circuit unit 20.

That is, when the logic circuit section 10 is not used, that is, when the input signal source is not connected to the external input terminal IN, the external input emitter follower transistor Q is used.
Since the base current is not supplied to 1, the emitter current of the emitter follower transistor Q1 stops flowing. Therefore, the collector current of the detection transistor also stops flowing, and the detection transistor is saturated and the base-emitter functions as a diode. for that reason,
The base current of the detection transistor increases, and the control circuit unit 20 operates to set the potential of the bias voltage Vcs to a low potential.

Alternatively, when the logic circuit section 10 is not used and the emitter current of the external input emitter follower transistor Q1 stops flowing, the base current of the detecting transistor also stops flowing, and the detecting transistor is turned off. Therefore, the collector current of the detection transistor stops flowing, and the control circuit unit 20 operates to set the potential of the bias voltage Vcs to a low potential.

Alternatively, when the logic circuit section 10 is not used and the emitter current of the external input emitter follower transistor Q1 stops flowing, the emitter follower is also applied to the collector of the detection transistor which is one of the transistor pairs forming the mirror circuit. The current from the use transistor Q1 stops flowing. However, the mirror circuit composed of the detection transistor and the other control transistor has a function that the drive current flowing through the control transistor is constant and the current flowing through the detection transistor is controlled to be constant. The control current component flowing from the bias circuit section 30 increases in the collector current of the transistor,
Therefore, the current flowing in the bias circuit unit 30 increases,
The potential at the point that determines the potential of the bias voltage Vcs in the bias circuit unit 30 is set to a low potential.

On the other hand, when the logic circuit section 10 is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the external input emitter follower transistor Q1 is supplied, the emitter follower The transistor Q1 is turned on and the emitter current flows. Therefore, since the collector current of the detection transistor Q2 also flows, the detection transistor Q2 is in a non-saturated state and operates normally as a transistor. Therefore, contrary to the case where the signal source is not connected to the external input terminal IN, the base current decreases, and the control circuit unit 20 does not operate and outputs the bias voltage Vcs as a predetermined potential.

Alternatively, when the logic circuit section 10 is used and the emitter current of the external input emitter follower transistor Q1 flows, the base current of the detection transistor flows, and the detection transistor is turned on. Therefore, contrary to the case where the signal source is not connected to the external input terminal IN, the collector current of the detection transistor flows,
The control circuit unit 20 does not operate and outputs the bias voltage Vcs as a predetermined potential.

Alternatively, when the emitter current of the external input emitter follower transistor Q1 flows when the logic circuit section 10 is used, the collector of the detection transistor, which is one of the pair of transistors forming the mirror circuit, is connected to the collector of the emitter follower. The current from the transistor Q1 flows in. Therefore, the control current component flowing from the bias circuit unit 30 in the collector current of the detection transistor decreases,
Therefore, the current flowing in the bias circuit unit 30 decreases,
The potential at the point that determines the potential of the bias voltage Vcs in the bias circuit unit 30 is output as a predetermined potential.

Therefore, since the detection circuit section 40 is composed only of the detection transistor for detecting the change in the emitter current of the external input emitter follower transistor Q1, it is necessary to provide the reference voltage generation circuit 50 in the detection circuit section 40. Absent. Therefore, the power consumption of the detection circuit unit 40 is reduced and the circuit area is also reduced. Further, the bias circuit unit 10 is composed of a main bias circuit unit and a sub-bias circuit unit, and the logic circuit unit 10, the detection circuit unit 40, the control circuit unit 20, and the sub-bias circuit unit are used as a unit series with the main bias circuit unit in common. In an integrated circuit having a plurality of series circuit groups, the detection circuit section 40 in each series detects the usage state of each series, and the control circuit section 20 controls the sub-bias circuit section only for the unused series. The bias voltage Vcs is controlled to a low potential.

Therefore, only one main bias circuit section consisting of the main bandgap circuit is required, and the power consumption of the detection circuit section 40 in each series is also reduced, so that the power consumption of the integrated circuit as a whole is reduced. It can be further reduced.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. FIG. 2 is a circuit diagram showing the first embodiment of the present invention.

In the figure, 10 is a logic circuit section,
It is composed of transistors Q1 to Q5, resistors R1 and R2, and an external input terminal IN. Reference numeral 20 denotes a control circuit unit, which includes transistors Q6 to Q8 and resistors R3 to R6. Reference numeral 31 is a sub-bias circuit section, which is composed of a transistor Q9 and resistors R7 and R8.
Reference numeral 32 denotes a main bias circuit section, which is a transistor Q1.
0 to Q14 and resistors R9 to R13 form a bandgap circuit. Then, Vcc is a high potential power source, Vee is a low potential power source, Vcs is a bias voltage, and Vr.
ef indicates the reference voltage, respectively.

The detection circuit section 40 partially overlaps with the logic circuit section 10, and is composed of an npn-type detection transistor Q2 whose collector is connected to the emitter of the npn-type external input emitter follower transistor Q1. The base of the emitter follower transistor Q1 is connected to the external input terminal IN, and the base of the detection transistor Q2 is connected to the control circuit unit 20. And
The input signal source, which is a logic signal having two different voltage levels, is connected to the external input terminal IN only when the operation of the logic circuit unit 10 is required, and the presence or absence of this connection is detected as the usage state of the circuit. .

In the semiconductor integrated circuit of this embodiment shown in FIG. 2, the circuit is not used, that is, the external input terminal IN.
When the input signal source is not connected to, the base current is not supplied to the external input emitter follower transistor Q1, so that the emitter current of the emitter follower transistor Q1 does not flow. Therefore, the collector current of the detection transistor Q2 in the detection circuit section 40 also stops flowing, so that the detection transistor Q2 is saturated and the base-emitter acts as a diode, and the base current of the detection transistor Q2 as shown in the figure. Current i1 is increased.

As the current i1 increases, the potential at the point A decreases by ΔV as shown below. ΔV = R3 × Δi1 Here, ΔV is the amount of change in the potential at the point A, and Δi1 is the amount of change in the current i1. Therefore, the pnp-type transistor Q6 in the control circuit unit 20 is turned on, and the current i2 flowing through the transistor Q7 in the control circuit unit 20 increases. Since the transistors Q7 and Q8 are mirror circuits, the drive current increases, and the current i3 flowing through the transistor Q8 increases.

As the current i3 increases, the potential at the point B that determines the potential of the bias voltage Vcs decreases. Therefore, the current source transistor Q3 in the logic circuit unit 10 is
Since the base voltage of the logic circuit 10 decreases and the current Ics flowing in the logic circuit section 10 decreases, the power consumption of the logic circuit section 10 is reduced. When the circuit is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the external input emitter follower transistor Q1 is supplied, the emitter follower transistor Q1 is turned on. An electric current flows. Therefore, since the collector current of the detection transistor Q2 in the detection circuit unit 40 also flows, the detection transistor Q2 is in a non-saturated state and the current i1 which is the base current.
Is reduced.

As the current i1 decreases, the potential at the point A in the control circuit section 20 rises, the pnp transistor Q6 is turned off, and the current i2 in the control circuit section 20 increases.
Decreases. Therefore, the current i3 flowing through the transistor Q8 of the mirror circuit also decreases. Therefore, the bias voltage V
The potential at the point B that determines the potential of cs becomes the level during normal operation, the current source transistor Q3 is turned on, and the logic circuit unit 10 performs normal operation.

In this embodiment, the use state of the logic circuit section 10 is detected by the presence / absence of saturation of the detection transistor Q2, and the reference voltage generation circuit 50 is unnecessary. Therefore, the power consumption is greatly reduced and the circuit area is also reduced. The above embodiment is particularly effective for a gate array type semiconductor device. In the case of a gate array type semiconductor device, in order to save power, it is conceivable that the power supply wiring is not connected to an unused logic circuit group (a logic circuit group to which no logic wiring is connected).

However, in order to prevent the power supply wiring from being connected to the unused logic circuit group, the logic design must be completed at the time of designing the power supply wiring pattern, and the power supply wiring that reflects this must be designed. Therefore, it is not possible to reduce the cost for each product type by increasing the number of design processes and using a common power supply pattern. In the circuit of the present embodiment, it is possible to select whether or not to supply power to the logic circuit group depending on whether or not the logic wiring is connected, so that the power supply pattern can be shared and the cost can be reduced.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In the figure, the series 1 is composed of the logic circuit section 10, the detection circuit section 40, the control circuit section 20 and the sub-bias circuit section 31 in the first embodiment, and the series 2
Has the same configuration as Series 1. Each of the series 1 and series 2 sub-bias circuit units 31 is connected to a single main bias circuit unit 32 at a point C.

The logic circuit section 10, the control circuit section 20,
The configuration and operation of each of the sub bias circuit unit 31, the main bias circuit unit 32, and the detection circuit unit 40 are the first.
It is similar to the embodiment of. For gate array integrated circuits,
A plurality of series of cells each including the integrated circuit described in the first embodiment as one block are required. In this case, if a bandgap circuit is provided for each cell, power consumption will increase.

This embodiment solves this problem. As shown in FIG. 3, in this embodiment, there is one main bias circuit section 32 common to each series, and each series has a logic circuit. It has a unit 10, a detection circuit unit 40, a control circuit unit 20, and a sub-bias circuit unit 31. Further, since each series is connected to the main bias circuit section 32 by the sub-bias circuit section 31 in the series, they are independent from each other. That is, the potential at the point B, which determines the potential of the bias voltage Vcs, is independent of each other and does not affect each other. Therefore, by detecting the use state of the logic circuit section 10 for each series and controlling the sub-bias circuit section 31, only the potential of the bias voltage Vcs of the unused circuit can be lowered without affecting other series. The power consumption can be reduced.

Further, in the present embodiment, the case where the number of sequences is two is shown, but the number of sequences is not limited to two, and any number of sequences may be used. Figure 4
[FIG. 8] is a circuit diagram showing a third embodiment of the present invention, which is a first modification of the first embodiment. In the present embodiment, the logic circuit unit 10, the control circuit unit 20, the sub-bias circuit unit 3
1. The respective configurations of the main bias circuit section 32 and the detection circuit section 40 are the same as those of the first embodiment, except that the connection point between the control circuit section 20 and the sub bias circuit section 31 is the first. In the embodiment of FIG.
In the embodiment of FIG.

In the semiconductor integrated circuit of this embodiment shown in FIG. 4, when the circuit is not used, that is, the external input terminal IN.
When the input signal source is not connected to, the base current is not supplied to the external input emitter follower transistor Q1, so that the emitter follower transistor Q1 is turned off and the emitter current does not flow. Therefore, since the collector current of the detection transistor Q2 in the detection circuit section 40 also stops flowing, the detection transistor Q2
Becomes saturated and acts as a diode between the base and emitter. Therefore, the current i1 which is the base current of the detection transistor Q2 as illustrated increases.

As the current i1 increases, the potential at the point A decreases by ΔV as shown below. ΔV = R3 × Δi1 Here, ΔV represents the amount of change in the potential at the point A, and Δi1 represents the amount of change in the current i1. Therefore, the pnp-type transistor Q6 in the control circuit unit 20 is turned on, and the current i2 flowing through the transistor Q7 in the control circuit unit 20 increases. Since the transistors Q7 and Q8 are mirror circuits, the drive current increases, and the current i4 flowing through the transistor Q8 increases.

Since the current i4 flows, the potential at the point D is lowered, and the bias voltage Vc in the sub bias circuit section 31 is reduced.
The potential at the point B that determines the potential of s decreases. For this reason,
Since the base voltage of the current source transistor Q3 in the logic circuit unit 10 decreases and the current Ics flowing in the logic circuit unit 10 decreases, the power consumption of the logic circuit unit 10 is reduced.

When the circuit is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the emitter follower transistor Q1 is supplied, the emitter follower transistor Q1 is turned on. Emitter current flows. Therefore, since the collector current of the detection transistor Q2 in the detection circuit unit 40 also flows, the detection transistor Q2 is in a non-saturated state, and the current i1 which is the base current decreases.

As the current i1 decreases, the potential at the point A in the control circuit section 20 rises, so that the pnp type transistor Q6 is turned off and the current i in the control circuit section 20 increases.
2 decreases. Therefore, the transistor Q8 of the mirror circuit
The current i4 that flows through is also reduced. Therefore, the potential at the point B, which determines the potential of the bias voltage Vcs, becomes the level at the time of normal operation, the current source transistor Q3 is turned on, and the logic circuit unit 10 performs normal operation.

In the present embodiment thus constructed, the first
It is possible to obtain the same effect as that of the embodiment. FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention, which is a second modification of the first embodiment. In the figure, reference numeral 20 denotes a control circuit unit, which includes transistors Q15 and Q16 and a resistor R1.
4 to R18, all transistors are np
It is an n-type transistor. Reference numeral 31 is a sub-bias circuit unit, which includes a transistor Q9 and resistors R19 and R19.
It is composed of 20.

In this embodiment, the respective configurations of the logic circuit section 10, the main bias circuit section 32, and the detection circuit section 40 are the same as those of the first embodiment, except that they are different.
The control circuit unit 20 is provided with n without using a pnp type transistor.
In the sub-bias circuit section 31 in that it is composed of only pn-type transistors, and in the first and third embodiments, the resistance R
7 is provided on the collector side of the transistor 9, the resistor R2 is provided on the base side of the transistor 9 in this embodiment.
It is set as 0.

In the semiconductor integrated circuit of this embodiment shown in FIG. 5, when the circuit is not used, that is, the external input terminal IN.
When the input signal source is not connected to, the base current is not supplied to the external input emitter follower transistor Q1, so that the emitter follower transistor Q1 is turned off and the emitter current does not flow. Therefore, since the collector current of the detection transistor Q2 in the detection circuit section 40 also stops flowing, the detection transistor Q2
Becomes saturated and acts as a diode between the base and emitter. Therefore, the current i6 which is the base current of the detection transistor Q2 as shown in the drawing increases.

As the current i6 increases, the potential at point E, which is the base voltage of the transistor Q15 in the control circuit section 20, decreases, so that the transistor Q15 is turned off and the current i7 decreases. Since the current i7 decreases, the potential at the point F, which is the base voltage of the transistor Q16, increases, so that the transistor Q16 is turned on and the current i8 increases.

As the current i8 increases, the potential at the point B, which determines the potential of the bias voltage Vcs in the sub bias circuit section 31, decreases. For this reason, the base voltage of the current source transistor Q3 in the logic circuit unit 10 decreases, and the current Ics flowing in the logic circuit unit 10 decreases, so that the power consumption of the logic circuit unit 10 is reduced. .

When the circuit is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the emitter follower transistor Q1 is supplied, the emitter follower transistor Q1 is turned on. Emitter current flows. Therefore, the detection transistor Q2 in the detection circuit unit 40 is in a non-saturated state and the base current i6 decreases.

As the current i6 decreases, the potential at point E, which is the base voltage of the transistor Q15 in the control circuit section 20, increases, so that the transistor Q15 is turned on and the current i7 increases. When the current i7 increases, the potential at the point F, which is the base voltage of the transistor Q16, decreases, so that the transistor Q16 is turned off and the current i8 decreases.

As the current i8 decreases, the potential at the point B that determines the potential of the bias voltage Vcs in the sub bias circuit section 31 becomes the level at the time of normal operation, and the current source transistor Q3 is turned on. 10 performs normal operation. In this embodiment configured as described above, the same effects as those of the first embodiment can be obtained, and
Since the circuit is configured only by the npn-type transistor instead of the pnp-type transistor in which stable characteristics are difficult to obtain, the power consumption can be reduced by the stable characteristics.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention. In the figure, the series 1 is composed of the logic circuit section 10, the detection circuit section 40, the control circuit section 20, and the sub-bias circuit section 31 in the fourth embodiment, and the series 2
Has the same configuration as Series 1. Each of the series 1 and series 2 sub-bias circuit units 31 is connected to a single main bias circuit unit 32 at a point C.

Further, the logic circuit section 10, the control circuit section 20,
The configuration and operation of each of the sub bias circuit section 31, the main bias circuit section 32, and the detection circuit section 40 are the fourth.
It is similar to the embodiment of. The present embodiment configured in this way has both the effects of the second embodiment and the effects of the third embodiment, and is effective in a gate array integrated circuit.

FIG. 7 is a circuit diagram showing a sixth embodiment of the present invention. In the figure, 10 is a logic circuit unit, which includes transistors Q1, Q3 to Q5 and resistors R1 and R21.
It is composed of R23. Reference numeral 20 denotes a control circuit section, which includes transistors Q18 and Q19 and resistors R24 to R26. Reference numeral 31 is a sub-bias circuit section, which includes a transistor Q9 and resistors R20 and R27. Reference numeral 32 denotes a main bias circuit section, which forms a bandgap circuit including transistors Q10 to Q14 and resistors R9 to R13.

The detection circuit section 40 partially overlaps with the logic circuit section 10, and is composed of an npn type detection transistor Q17 whose base is connected to the emitter of the npn type external input emitter follower transistor Q1. The collector of the detection transistor Q17 is connected to the control circuit section 20. In the semiconductor integrated circuit of this embodiment shown in FIG. 7, when the circuit is not used, that is, when the input signal source is not connected to the external input terminal IN, the base current is supplied to the external input emitter follower transistor Q1. Therefore, the emitter current of the emitter follower transistor Q1 does not flow. Therefore, the potential at the point G, which is the base voltage of the detection transistor Q17 in the detection circuit unit 40, decreases, so that the detection transistor Q17 is turned off and the current i9 decreases.

As the current i9 decreases, the potential at point H, which is the base voltage of the transistor Q18 in the control circuit section 20, rises and the transistor Q18 is turned on. Since the transistor Q18 is turned on, the potential at the point I which is the base voltage of the transistor Q19 rises,
The transistor Q19 is turned on and the current i8 increases.

As the current i8 increases, the potential at the point B that determines the potential of the bias voltage Vcs decreases. Therefore, the current source transistor Q3 in the logic circuit unit 10 is
Since the base voltage of the logic circuit 10 decreases and the current Ics flowing in the logic circuit section 10 decreases, the power consumption of the logic circuit section 10 is reduced. When the circuit is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the external input emitter follower transistor Q1 is supplied, the emitter follower transistor Q1 is turned on. An electric current flows. Therefore, the potential at the point G, which is the base voltage of the detection transistor Q17 in the detection circuit unit 40, decreases, so that the detection transistor Q17 is turned on.
9 increases.

As the current i9 increases, the potential at the point H, which is the base voltage of the transistor Q18 in the control circuit section 20, decreases, and the transistor Q18 is turned off. Since the transistor Q18 is turned off, the potential at the point I decreases, the transistor Q19 turns off, and the current i8 decreases. Therefore, the potential at the point B, which determines the potential of the bias voltage Vcs, becomes the level during normal operation,
The current source transistor Q3 is turned on, and the logic circuit unit 10 operates normally.

In this embodiment thus constructed, the same effect as that of the first embodiment can be obtained, and the logic circuit section 1 is also provided.
Since the use state of 0 is detected by the on / off state of the detection transistor Q17 without utilizing the saturation of the transistor, the operation speed can be further increased. FIG. 8 is a circuit diagram showing a seventh embodiment of the present invention.

In the figure, the series 1 is the logic circuit section 10, the detection circuit section 40, and the control circuit section 20 in the sixth embodiment.
And the sub-bias circuit unit 31, the series 2 has the same structure as the series 1. Series 1 and Series 2
Each sub bias circuit section 31 is connected to a single main bias circuit section 32 at a point C. Further, the logic circuit unit 10, the control circuit unit 20, the sub-bias circuit unit 3
1. The configurations and operations of the main bias circuit section 32 and the detection circuit section 40 are similar to those of the sixth embodiment.

The present embodiment thus constituted has both the effect of the second embodiment and the effect of the sixth embodiment, and is effective in a gate array integrated circuit. Figure 9
FIG. 11 is a circuit diagram showing an eighth embodiment of the present invention. In the figure, 10 is a logic circuit section, which includes transistors Q1 and
It is composed of Q3 to Q5, a resistor R1 and an external input terminal IN. Reference numeral 31 is a sub-bias circuit section, which is composed of a transistor Q9 and resistors R29 and R30.
Reference numeral 32 denotes a main bias circuit section, which is a transistor Q1.
0 to Q14 and resistors R9 to R13 form a bandgap circuit.

Further, the control circuit section 20 and the detection circuit section 40 overlap each other and are composed of a detection transistor Q20, a control transistor Q21, a resistor R28 and a Zener diode Di. The collector of the detection transistor Q20 is connected to the emitter of the emitter follower transistor Q1 and the sub-bias circuit section 31, the base of the control transistor Q21 is connected to the base of the detection transistor Q20, and the base and collector are common. . The detection transistor Q20 and the control transistor Q21 form a mirror circuit.

In the semiconductor integrated circuit of this embodiment shown in FIG. 9, when the circuit is not used, that is, the external input terminal IN
When the input signal source is not connected to, the base current is not supplied to the external input emitter follower transistor Q1, so that the emitter follower current of the emitter follower transistor Q1 does not flow. Therefore,
The current i10 from the emitter follower transistor Q1 does not flow into the collector of the detection transistor Q20.

Here, the detection transistor Q20 constitutes a mirror circuit together with the control transistor Q21, and the drive current i11 of the mirror circuit flowing through the control transistor Q21 is constant. Therefore, the currents flowing in the detection transistor Q20, that is, the current i10 and the current i11.
The sum of is also constant. Therefore, the detection transistor Q2
Among the components of the current flowing through 0, the sub bias circuit unit 3
The current i12 that is a component flowing from 1 increases.

As the current i12 increases, the potential at the point B that determines the potential of the bias voltage Vcs decreases.
Therefore, the current source transistor Q in the logic circuit unit 10 is
Since the base voltage of 3 decreases and the current Ics flowing in the logic circuit unit 10 decreases, the power consumption of the logic circuit unit 10 is reduced. When the circuit is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the external input emitter follower transistor Q1 is supplied, the emitter follower transistor Q1 is turned on. An electric current flows. Therefore, the current i1 from the emitter follower transistor Q1 is applied to the collector of the detection transistor Q20.
0 flows in.

Here, the detection transistor Q20 constitutes a mirror circuit together with the control transistor Q21, and the current flowing through the detection transistor Q20, that is, the current i.
Since the sum of 10 and the current i11 is constant, the current i12, which is a component of the current flowing through the detection transistor Q20 and flowing from the sub-bias circuit unit 31, decreases. Current i1
By decreasing 2, the potential at the point B, which determines the potential of the bias voltage Vcs, becomes the level at the time of normal operation, and the current source transistor Q3 is turned on, so that the logic circuit unit 10 performs normal operation.

In the present embodiment thus constructed, the fourth
It is possible to obtain the same effect as that of the embodiment described above, and since the number of elements used in the circuit can be reduced, it is possible to further reduce the circuit area. FIG. 10 is a circuit diagram showing a ninth embodiment of the present invention. In the figure, the series 1 is composed of the logic circuit section 10, the detection circuit section 40, the control circuit section 20 and the sub-bias circuit section 31 in the eighth embodiment, and the series 2 has the same construction as the series 1. ing. Series 1
Each sub-bias circuit unit 31 of the series 2 is connected to a single main bias circuit unit 32 at a point C.

Further, the logic circuit section 10, the control circuit section 20,
The configuration and operation of each of the sub bias circuit unit 31, the main bias circuit unit 32, and the detection circuit unit 40 are the eighth.
It is similar to the embodiment of. The present embodiment configured as described above has both the effects of the second embodiment and the effects of the eighth embodiment, and is effective in a gate array integrated circuit.

FIG. 11 is a circuit diagram showing a tenth embodiment of the present invention, which is a modification of the eighth embodiment. In the present embodiment, the respective configurations of the logic circuit unit 10, the control circuit unit 20, the sub bias circuit unit 31, the main bias circuit unit 32, and the detection circuit unit 40 are the same as those of the eighth embodiment, but different points. The control circuit unit 20 is connected to the main bias circuit unit 32 at a point J in the main bias circuit unit 32, and the control circuit unit 20 is connected to the main bias circuit unit 3.
2 is a structure for directly controlling.

In the semiconductor integrated circuit of this embodiment shown in FIG. 11, when the circuit is not used, that is, the external input terminal I
When the input signal source is not connected to N, the base current is not supplied to the external input emitter follower transistor Q1. Therefore, the emitter follower transistor Q1 is not supplied.
The emitter follower current will stop flowing. Therefore, the current i10 from the emitter follower transistor Q1 does not flow into the collector of the detection transistor Q20.

Here, the detection transistor Q20 constitutes a mirror circuit together with the control transistor Q21, and the drive current i11 of the mirror circuit flowing through the transistor Q21.
Is constant. Therefore, the detection transistor Q20
Also, the current flowing through, that is, the sum of the current i10 and the current i11 is constant. Therefore, the current i13, which is a component of the current flowing through the detection transistor Q20 and flows from the main bias circuit section 32, increases.

As the current i13 increases, the potential at point J in the main bias circuit section 32 decreases. Since the potential at the point J becomes the common base voltage of the mirror circuit composed of the transistor Q12 and the transistor Q13,
The current i14, which is the driving current of the mirror circuit, decreases due to the decrease in the potential at the point J, and the transistor Q13
The current flowing through is also reduced, and the potential at point K in the main bias circuit section 32 rises. Therefore, the transistor Q14
Is turned on, and the current i flowing through the transistor Q14
15 increases.

As the current i15 increases, the potential at point L in the main bias circuit section 32, which is the output to the sub bias circuit section 31, decreases, and B in the sub bias circuit section that determines the potential of the bias voltage Vcs. The potential at the point also drops. For this reason, the base voltage of the current source transistor Q3 in the logic circuit unit 10 decreases, and the current Ics flowing in the logic circuit unit 10 decreases, so that the power consumption of the logic circuit unit 10 is reduced. .

When the circuit is used, that is, when the input signal source is connected to the external input terminal IN and the base current of the external input emitter follower transistor Q1 is supplied, the emitter follower transistor Q1 is turned on. Then, the emitter current flows. Therefore, the current i10 from the emitter follower transistor Q1 flows into the collector of the detection transistor Q20.

Here, the detection transistor Q20 constitutes a mirror circuit together with the control transistor Q21, and the current flowing through the detection transistor Q20, that is, the current i.
Since the sum of 10 and the current i11 becomes constant, the main bias circuit unit 32 for the current flowing through the detection transistor Q20
The current i13, which is a component flowing in from, decreases. Current i
The decrease of 13 raises the potential at the j point. J
The potential at the point is transistor Q12 and transistor Q13.
Since it becomes a common base voltage of the mirror circuit constituted by, the current i14, which is the drive current of the mirror circuit, increases due to the rise of the potential at the point J, and accordingly the transistor Q
The current flowing through 13 also increases, and the potential at point K rises. Therefore, the transistor Q14 is turned off, and the current i15 flowing through the transistor Q14 decreases.

As the current i15 increases, the potential at the point L in the main bias circuit section 32, which is the output to the sub bias circuit section 31, decreases, and B in the sub bias circuit section that determines the potential of the bias voltage Vcs. The potential at the point also drops. For this reason, the base voltage of the current source transistor Q3 in the logic circuit unit 10 decreases, and the current Ics flowing in the logic circuit unit 10 decreases, so that the power consumption of the logic circuit unit 10 is reduced. .

As the current i15 decreases, the potential at the point L in the main bias circuit section 32, which is an output to the sub bias circuit section 31, rises, so that the bias voltage Vc
The potential at the point B, which determines the potential of s, becomes the level during normal operation. Therefore, the current source transistor Q3 is turned on, and the logic circuit unit 10 operates normally. In this embodiment having such a configuration, the same effect as that of the eighth embodiment can be obtained.

[0077]

As described above, according to the present invention, the detection circuit detects the operation of the emitter follower transistor which receives an external input, based on whether the detection transistor is saturated or on / off. Therefore, a complicated circuit is not required as the detection circuit, the power consumption of the detection circuit can be reduced, and the size can be reduced.

In particular, in the case of an integrated circuit which is independent of the main bias circuit and has a plurality of series logic circuit groups each having a sub bias circuit, only one main bias circuit is required, and each main series circuit Since the power consumption in the circuit can be reduced, the power consumption in the entire circuit can be significantly reduced. Further, since it is possible to select whether or not to supply power to the logic circuit group depending on whether or not the logic wiring is connected, power is not supplied to the unused logic circuit group even if the power wiring is connected. Therefore, the power supply wiring pattern can be shared in the designing / manufacturing process, and the versatility is enhanced.

Therefore, it greatly contributes to lower power consumption and higher integration of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a seventh embodiment of the present invention.

FIG. 9 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a ninth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a tenth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a semiconductor integrated circuit including a conventional detection circuit.

[Explanation of symbols]

 10 ... Logic circuit part 20 ... Control circuit part 30 ... Bias circuit part 31 ... Sub bias circuit part 32 ... Main bias circuit part 40 ... Detection circuit part 50 ... Reference voltage generation circuit Q1-Q5, Q7-Q24 ... npn-type transistor Q6 ... pnp type transistors R1 to R31 ... Resistors Di ... Zener diodes Vcc ... High potential power supply Vee ... Low potential power supply Vcs ... Bias voltage Vref ... Reference voltage

Claims (6)

[Claims] 1. A transistor pair (Q4, Q5) having a common emitter connected to a current source transistor (Q3), and an emitter connected to the base of one transistor of the transistor pair (Q4, Q5). A logic circuit unit including an emitter follower transistor (Q1) in which logic signals having different voltage levels are input to the base as input signals when the circuit is active, and the emitter current is controlled according to the presence or absence of the input of the input signal. (10) and a bias circuit section (30) for applying a bias voltage (Vcs) to the base of the current source transistor (Q3).
And an emitter follower transistor (Q1) connected to the emitter of the emitter follower transistor (Q1).
1) A detection circuit section (40) for detecting whether or not the input signal source input to the emitter follower transistor (Q1) is connected by a change in the emitter current, and a detection output of the detection circuit section (40). And a control circuit section (20) for determining the bias voltage (Vcs) and controlling the driving state of the current source transistor (Q3). 2. The detection circuit section (40) includes a detection transistor having a collector connected to the emitter of the emitter follower transistor (Q1), and the detection transistor section (40) is used for an emitter follower depending on whether the detection transistor is saturated or not. 2. The semiconductor integrated circuit according to claim 1, wherein the presence or absence of an input signal input to the base of the transistor (Q1) is detected. 3. The detection circuit section (40) includes a detection transistor whose base is connected to the emitter of the emitter follower transistor (Q1), and the emitter follower transistor is provided by changing the collector current of the detection transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the presence or absence of an input signal input to the base of the transistor (Q1) is detected. 4. The detection circuit section (40) and the control circuit section (20) have a collector whose collector is the emitter of the emitter follower transistor (Q1) and the bias circuit section (3).
0) and a control transistor whose base is connected to the base of the detection transistor and whose base and collector are common and through which a constant drive current flows, The detection transistor in the mirror circuit is configured so that an input signal to the base of the emitter follower transistor (Q1) is changed by a change in collector current accompanying a change in emitter current of the emitter follower transistor (Q1). The presence or absence of an input is detected, and the emitter follower transistor (Q
The change in the emitter current of 1) is calculated by the bias circuit (3
0), the current flowing in the bias circuit section (30) is controlled so as to be compensated by the current flowing in, and the potential at the point at which the bias voltage (Vcs) becomes the potential is determined by the change in the current, and the current source The semiconductor integrated circuit according to claim 1, wherein the driving state of the transistor (Q3) is controlled. 5. The main bias circuit section (32), wherein the bias circuit section (30) includes a bandgap circuit for obtaining a temperature-compensated output, and the output of the main bias circuit section (32) is referred to. The sub-bias circuit unit (31) generates a bias voltage (Vcs) of the current source transistor (Q3), and the control circuit unit (20) includes the sub-bias circuit unit (3).
1) is controlled to output the bias voltage (Vc
s) is controlled, Claim 1 thru | or Claim 4 characterized by the above-mentioned.
The semiconductor integrated circuit described. 6. A plurality of series circuit groups having the logic circuit section (10), the detection circuit section (40), the control circuit section (20), and the sub-bias circuit section (31) as a unit series, and one common circuit group. A main bias circuit section (32) is provided, and within each unit series, the control circuit section (20) determines the output of the sub bias circuit section (31), and the sub bias circuit section (31) is configured to The semiconductor integrated circuit according to claim 5, wherein the semiconductor integrated circuit is connected to a main bias circuit section (32) and outputs a bias voltage (Vcs) referring to the output of the main bias circuit section (32).