JPH0685159A - Semiconductor memory device and memory device using same - Google Patents

Abstract

PURPOSE:To provide a new semiconductor memory device having a temperature limiting function and an easy to handle memory device which maintains a specified operation speed as well, embodying a higher density assembly. CONSTITUTION:A step-down circuit is installed on a memory circuit whose operation speed is virtually rated in conformity with the electric current flowing in an MOSFET where the step-down circuit is designed to switch over operating voltage to a small voltage in terms of an absolute value based on a temperature detection circuit and a control signal transmitted from the detection output or outside. These semiconductor memory device are laminated and assembled while the step-down circuit is controlled by means of temperature detection signals of the circuit itself and temperature detection signals formed with other laminated memory devices, thereby reducing the operating voltage in terms of an absolute value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a memory device using the same, and more particularly to a technique effective when used in a stacked structure for high-density mounting.

[0002]

2. Description of the Related Art As a memory module having a high packaging density, there is a memory module in which another memory device of approximately the same size as the EPROM is stacked and mounted so that the ultraviolet ray transmitting window of the EPROM is exposed to the outside. As an example of such a memory module, there is JP-A-61-63048.

[0003]

In the memory module described above, semiconductor memory devices having substantially the same package size are simply stacked for high-density mounting. When the semiconductor memory device is accessed, a current flows and the semiconductor memory device inevitably generates heat. If the chips are simply stacked as described above, heat is not sufficiently dissipated and the chip temperature rises. In a semiconductor memory device mainly composed of a MOSFET (insulated gate type field effect transistor), since the MOSFET has a positive temperature characteristic, the operating current decreases as the temperature rises, and finally about 12
It will settle down to a high temperature such as 0 ° C.

When the temperature rises as described above, the operating current of the semiconductor memory device decreases, so that the operating speed is inevitably slowed down. Therefore, the memory access time must be set in consideration of the worst case in the case of adopting the mounting method in which the heat dissipation is bad as described above. However, since the standard upper limit temperature of the semiconductor memory device is usually about 80 ° C., if the temperature exceeds the standard upper limit value, the access time cannot be satisfied, and the memory access time is measured under the high temperature condition. Then, there is a problem that the usability becomes extremely poor such as determining the memory access time, and the semiconductor memory device must be used in the region having the worst characteristics.

An object of the present invention is to provide a novel semiconductor memory device having a temperature limiting function. Another object of the present invention is to provide a memory device which is easy to use and maintains its operation speed while achieving high-density mounting. The above and other objects and novel features of the present invention are
It will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the operating voltage is made small in absolute value by the temperature detecting circuit and its detection output or the control signal input from the outside in the memory circuit having a circuit form in which the operating speed is substantially regulated corresponding to the current flowing in the MOSFET. A step-down circuit that switches to voltage is provided. These semiconductor memory devices are mounted in a stack, and the step-down circuit is controlled by its own temperature detection signal or a temperature detection signal formed by another semiconductor memory device stacked to reduce the operating voltage in absolute value.

[0007]

According to the above-mentioned means, the step-down circuit operates at a high temperature close to the standard upper limit value to reduce the operating voltage in absolute value, so that the operating current is reduced by that amount and heat generation is suppressed. It becomes a heat saturation state at a low temperature and a predetermined operation speed can be secured. By stacking and mounting the semiconductor memory devices having such a function, it is possible to obtain a memory device capable of high-density mounting and maintaining an operation speed.

[0008]

1 is a schematic side view of an embodiment of a memory device using a semiconductor memory device according to the present invention. The memory device of this embodiment has a high-density mounting,
Semiconductor memory devices are stacked and configured. A cold plate is provided on a base substrate serving as a base, and the lowest semiconductor memory device is mounted on the cold plate. To increase the packaging density, a plurality of semiconductor memory devices are stacked and provided on the semiconductor memory device.

A circuit board having electrodes (through holes) provided corresponding to the leads of the semiconductor memory device is attached to the base substrate. The mounting surface of this circuit board is arranged in the vertical direction along the stacking direction of the semiconductor memory devices. The leads of the semiconductor memory device are inserted into through holes provided on the mounting surface and electrically connected by soldering or the like. This circuit board is provided with printed wiring for connecting a plurality of semiconductor memory devices mounted thereon to each other, and for example, in order to connect to other similar stacked semiconductor memory devices, Although omitted, an electrode is provided on the lower side and is connected to a printed wiring provided on the base substrate.

FIG. 8 shows a plan view of one memory module. A plurality of columns of circuit boards are provided on the base substrate in a plurality of rows, and in the figure, two semiconductor memory device ICs are stacked and provided in one row. In the case where the M rows of circuit boards are provided on the base board and the semiconductor memory devices are mounted by stacking them in N stages respectively,
It is possible to provide M × 2 × N semiconductor memory devices.

In FIG. 1, although not particularly limited, in order to facilitate the assembly of the memory module as described above, for example, a lead of a semiconductor memory device is inserted into a through hole of one circuit board and electrically connected by soldering or the like. connection,
The other lead of the stacked semiconductor memory device is inserted into the through hole of the other circuit board and electrically connected by soldering or the like as described above. After forming such a memory unit, the memory unit may be mounted so that the cold storage plate is provided on the base substrate and the semiconductor memory device at the lowermost stage is mounted thereon.

The cold plate is not particularly limited, but has a cooling effect by a pipe through which cold water flows or a pipe through which another refrigerant flows inside the metal plate which is a heat conductor.

In the memory module as described above, since the semiconductor memory devices are stacked and mounted in a plurality of stages, there is a problem that heat dissipation efficiency is deteriorated. In particular,
Since the internal semiconductor memory device is structured to be sandwiched between the upper and lower semiconductor memory devices, heat dissipation is performed through the semiconductor memory device above or below these semiconductor memory devices.
On the other hand, on the contrary, it receives heat from the adjacent semiconductor memory device, so that it is substantially difficult to guarantee the temperature of the internal semiconductor chip within the standard value.

Therefore, in the present application, each semiconductor memory device is provided with a temperature detecting circuit and a step-down circuit, and when the chip temperature reaches a certain high temperature, the operating voltage of the semiconductor memory device itself or another semiconductor memory device adjacent thereto is lowered to reduce the current. The amount of consumption is limited to suppress heat generation.

FIG. 2 is a schematic block diagram of an embodiment of the semiconductor memory device according to the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor technique.

The memory circuit comprises memory cells arranged in a matrix, an address selection circuit for selecting the cells, an input buffer for inputting address signals, write data and control signals, and an output buffer for outputting read signals. Although not particularly limited, the memory circuit is configured by a static RAM (random access memory) of an ECL interface in which a memory cell is composed of a CMOS circuit and its peripheral circuit is a combination of a CMOS circuit and a bipolar transistor as described later. Composed.

A temperature detecting circuit, a control circuit and a step-down power supply circuit are provided on a semiconductor chip on which the static RAM as described above is formed. The control circuit may be configured in combination with a control circuit incorporated in the memory circuit as described below.
In this embodiment, the temperature detection circuit has a chip temperature of about 8
When the standard upper limit value such as 0 ° C is reached, a detection signal is formed and the step-down power supply circuit is controlled through the control circuit.
Try to reduce the operating voltage to a small voltage in absolute value.
Such a reduction in the operating voltage inevitably reduces the operating current, so that the heat generation of the semiconductor chip is suppressed and the temperature rise is prevented.

Without such temperature detection and power down function, the temperature of the semiconductor chip rises and eventually reaches about 120.
It will settle to a saturation temperature such as ° C. That is, in the circuit mainly composed of the MOSFET as described above,
Since the MOSFET has a positive temperature coefficient, the operating current decreases as the temperature rises, so that the above-mentioned saturation temperature at which the balance is taken is the upper limit. However, since the current flowing through the MOSFET at such a high temperature is greatly reduced, the operating speed becomes extremely slow.

On the other hand, if the temperature detection and power down function as described above is added, the operating power supply is lowered to suppress heat generation and a constant operating current is secured before reaching the above high temperature. You can When the semiconductor memory devices are stacked and mounted as described above, such reduction of heat generation suppresses the heat generation of the semiconductor memory devices themselves, and also limits the temperature rise of other adjacent semiconductor memory devices. Therefore, the heat generation amount of the memory module as a whole can be limited, so that the temperature can be suppressed to a low level as a whole, and an operation current sufficient to maintain a desired operation speed can be secured.

The limitation of the temperature of the semiconductor memory device as described above is useful for effectively using the standard value. That is, if the semiconductor memory device can be limited within the upper limit temperature as in this embodiment, the operating current can be guaranteed by the step-down voltage at that time, so that the memory access time can be determined without measuring the memory access time one by one. Therefore, it is easy for the user to use.

FIG. 3 is a schematic block diagram of another embodiment of the semiconductor memory device according to the present invention. In this embodiment, the detection signal of the temperature detection circuit provided in the semiconductor memory device is output to the outside through the driver. Further, the step-down power supply circuit provided inside switches the power supply voltage to the step-down voltage by a control signal input from the outside. In this embodiment, two semiconductor integrated circuit devices 1 and 2 having a function of outputting such a high temperature detection signal and switching the power supply voltage to a voltage stepped down by a control signal input from the outside are most used. A simple combination example is shown, in which the other step-down power supply circuits are controlled by the temperature detection signal.

In this configuration, for example, when the semiconductor memory device 1 is repeatedly accessed and the temperature of the chip rises due to the consumption current, the temperature detecting circuit detects this and the step-down power supply circuit of another semiconductor memory device 2 through the driver. Is operated to switch the operating voltage of the memory circuit to a reduced one. As a result, as the operating voltage of the semiconductor memory device 2 adjacent to the semiconductor memory device 1 that has reached the high temperature becomes a reduced small voltage, its current consumption is reduced and the amount of heat generation is suppressed. As a result, the heat dissipation efficiency of the semiconductor memory device 1 that is indirectly accessed is improved, and the temperature rise is suppressed.

In the memory module as described above, a large number of semiconductor memory devices of three or more are stacked and mounted. Therefore, in actuality, among the semiconductor memory devices having the stacked structure, the step-down power supply circuits of all the semiconductor memory devices other than the semiconductor memory device are controlled to reduce the operating voltage to the stepped-down one. In this case, the external terminal is configured to have a wired OR configuration, or is connected to the OR configuration by a logic using a diode.

For example, when the semiconductor memory devices are formed by stacking in N stages, the high temperature detection signal of one semiconductor memory device is passed through the diode to the control input terminal of the other semiconductor memory device except itself, which is high level or low level. It suffices to input the control signal of. In this configuration, when one of N stacked semiconductor integrated circuit devices is repeatedly accessed, and the temperature of the chip rises due to the current consumption, the temperature detection circuit detects this and the other remaining N- By operating the step-down power supply circuit of one semiconductor memory device 2 to reduce the current consumption of each semiconductor memory device and suppress the heat generation all at once, the heat dissipation efficiency of the semiconductor memory device to which memory access is performed is improved correspondingly, and its temperature The rise is suppressed.

Open drain output M as a driver
The OSFET may be used, and the temperature detection outputs of the semiconductor memory devices stacked in N stages may be connected in common and supplied to all control inputs to control the step-down power supply circuits all at once. At this time, since the semiconductor memory device provided on the cold plate efficiently releases heat, even if the semiconductor memory device without the temperature detection circuit or the step-down power supply circuit is used, the semiconductor memory device is practically used. Does not matter.

The memory module identifies the address assigned to the memory module, sends a chip select signal to the semiconductor memory device corresponding to the designated address, and sends an address signal on the system to each memory module. A memory control circuit such as an address conversion circuit for converting an address signal corresponding to the semiconductor memory device is provided. When such a memory control circuit is provided, the high temperature detection signal of each semiconductor memory device is supplied to the memory control circuit, the high temperature detection signal is analyzed here, and the step-down power supply circuit for any semiconductor memory device is analyzed. It is also possible to determine whether or not to activate the above, and to make the heat generation of the memory module as a whole uniform. In this case, the memory control circuit forms a control signal for the step-down power supply circuit provided in each semiconductor memory device.

FIG. 4 shows a circuit diagram of an embodiment of the temperature detecting circuit. In this embodiment, as will be described later, E
It is directed to a static RAM having a Bi-CMOS structure that employs a CL interface. Therefore, the operating voltage is the negative voltage VEE and VCC is brought to the ground potential of the circuit, such as 0V of the circuit.

Diodes (or diode-type transistors in which the base and collector are connected) D1 and D2
Are connected in series. An operating current is made to flow through these diodes D1 and D2 through a resistor R1.
The cathode side of the diode D2 is connected to the power supply voltage VEE. The forward voltage of these diodes D1 and D2 is
It is supplied to the base of the transistor Q1. The emitter of the transistor Q1 is connected to the power supply voltage line VEE via the emitter resistor R2, and the collector is the ground line VC of the circuit.
Connected to C.

Since the forward voltage of the two diodes D1 and D2 is output via the base and emitter of the transistor Q1, the voltage between the base and emitter of the diode D1 and the transistor Q1 cancels each other. Is a voltage signal V corresponding to the forward voltage of the diode D1.
T is formed. As is well known, the forward voltage of a diode has a negative temperature dependence of decreasing with increasing temperature. Therefore, the voltage signal VT has a temperature characteristic that it decreases as the temperature rises,
It is supplied to C and compared with a reference voltage VREF corresponding to the temperature to be detected. For example, the reference voltage VREF is set according to the forward voltage of the diode when the temperature is 80 ° C. It goes without saying that the reference voltage VREF is a temperature-compensated and highly accurate reference voltage.

The voltage comparison circuit VC detects the detection signal S which changes from low level to high level when the voltage signal VT which decreases with the rise of temperature becomes equal to or lower than the reference voltage VREF.
W is formed. The signal SW is output to the outside through the built-in step-down power supply circuit or driver, and the step-down power supply circuit provided in another semiconductor memory device is operated to control so as to reduce current consumption.

In order to detect the temperature with higher accuracy, the voltage signal VT may correspond to the forward voltage of the N diodes. That is, if N + 1 diodes are connected in series and output through the emitter follower transistor, the voltage signal VT that is N times larger can be obtained. Alternatively, the reference voltage VR
Conversely, the EF may have a positive temperature characteristic. As a result, when the temperature is about 80 ° C, the voltages VT and VRE are
The level of F should be reversed. For example, the threshold voltage of MOSFET can be used as the one having a positive temperature characteristic.

FIG. 5 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.
Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor technique.

The X address buffer takes in the X address signal AX consisting of a plurality of bits and transmits it to the X decoder. The X decoder shown by a plurality of lines in the figure decodes the address signal to form one word line selection signal. This word line selection signal is transmitted to the word line through the X driver.

The Y address buffer takes in the Y address signal AY consisting of a plurality of bits and transmits it to the Y decoder. The Y decoder shown by a plurality of lines in the figure decodes an address signal to form a selection signal for a pair of complementary data lines DT and DB. This selection signal is Y
It is transmitted to the Y switch through the driver. The Y switch selects a pair of complementary data lines from a plurality of pairs of complementary data lines and connects them to the common data line. The write data formed by the write amplifier is transmitted to the common data line. The Y switch is a switch MOS that selects a preamplifier provided corresponding to the complementary data line.
An FET is also provided. Although the preamplifier is shown as a separate circuit block in the figure, the preamplifier provided corresponding to each complementary data line is
The one corresponding to the complementary data line selected by the switch is selected.

The input buffer takes in the write data and transmits it to the write amplifier in the write mode. The output signal of this write amplifier is Y through the common data line.
Is transmitted to the complementary data line selected by the switch,
The data is written in the memory cell that is in the selected state by the word line selection operation. The read signal amplified by the free-amplifier in the read mode is input to the sense amplifier through the common collector line, sensed therein, and transmitted from the external terminal Dout through the output buffer.

In this embodiment, a temperature detecting circuit and a step-down circuit are provided, and the output signal of the temperature detecting circuit is controlled by the control circuit. The step-down circuit receives the power supply voltages VCC and VEE, forms a voltage VDD equal to the power supply voltage VEE in a normal state, and outputs the voltage VDD as each operating voltage of the internal circuit. When the high temperature detection signal is formed by the temperature detection circuit, a voltage obtained by stepping down the power supply voltage VEE as described above is formed and output as the operating voltage VDD.

FIG. 6 shows a circuit diagram of an embodiment related to one complementary data line in the static RAM. In the figure, one word line, one word line selection circuit, one memory cell, a pair of common data lines and their load circuits, column selection circuit, column switch circuit, write recovery circuit, preamplifier, sense amplifier and A write amplifier is shown as an example.

The memory cell is a P-channel type MOSFE.
A CMOS latch circuit in which the input and output of a CMOS inverter circuit composed of T and N-channel MOSFETs are cross-connected, and its input / output node and complementary data lines DT and D
A transmission gate MO for address selection provided between B and B
It is composed of SFET. The operating voltage on the high level side of the memory cell is set to the ground potential of the circuit, and the operating voltage on the low level side is not particularly limited, but the constant voltage VEM formed by the voltage generating circuit is used.

The memory cell of this embodiment is a complete CMOS.
Although the memory cell having the structure is used, a high resistance load made of a polysilicon layer or the like may be used instead of the P-channel MOSFET. This high resistance load is set to a high resistance value such that the memory level accumulated in the gate of the N-channel MOSFET passes a minute current that is not lost by the drain leak current. Therefore, the high resistance load has a significantly different meaning from the load in the normal ratio type inverter circuit. When such a high resistance load is used, the size (occupied area) of the memory cell can be significantly reduced. However, if the operating voltage on the low level side of the memory cell is set to a value such as -3.2V to -3.3V, the operation of the memory cell may become unstable. Use is preferable.

The gate of the transmission gate MOSFET of the memory cell is connected to the corresponding word line. This word line is driven by a word line selection circuit NOR1 composed of a level conversion circuit having a logical function as described later. In the figure, the decoder unit and the word driver as described above are integrally shown.

The complementary data lines DT and DB are provided with data line load means composed of P-channel MOSFETs MP1 and MP2. These MOSFET MP1, MP
2 has its conductance formed relatively small in consideration of the write characteristic, and the constant voltage VEM is constantly supplied to its gate. These MOSFET MP1, MP
P channel type MOSFET with a relatively large conductance in the source and drain paths of 2.
Source and drain paths of MP3 and MP4 are provided in parallel.

By supplying the write control signal WE1 to the gates of the MOSFETs MP3 and MP4, the MOSFETs MP3 and MP4 are turned on at the time other than the write operation. In other words, the MOSFETs MP3 and MP4 are
Together with the MOSFETs MP1 and MP2, they form a data line load during a read operation. That is, at the time of read operation, the signal amplitude of the complementary data line is limited to realize high speed read. On the other hand, during the write operation, the control signals WE1 turn off the MOSFETs MP3 and MP4 having the relatively large conductances, and the loads on the complementary data lines DT and DB have only a small conductance and the MOSFETs MP1 and MP2.
With the above configuration, the high-speed writing is performed by increasing the signal amplitude of the write data transmitted to the complementary data line.

A bias voltage level-shifted by the diode-connected transistors Q3 and Q4 is applied to the load circuit. That is, the complementary data lines DT,
The high level of the signal amplitude of DB is set to a low potential such as -2VBE. As a result, the signal amplitudes of the complementary data lines DT and DB at the time of the write operation are limited to a small value, which enables high-speed writing. Since writing to the memory cell is predominantly performed by the low level transmitted to the complementary data line DT or DB, there is no problem even if the high level is lowered to -2VBE as in this embodiment. That is, the gate potential of the storage MOSFET in the ON state of the memory cell is pulled out by the potential of the complementary data line set to the low level via the transmission gate MOSFET and switched to the OFF state, and as a result, it is in the OFF state. This is because the storage MOSFET is turned on and information is inverted and written.

The complementary data lines DT and DB are connected to a pair of common data lines via N-channel type MOSFETs MN3 and MN4 for column switches. An output terminal of a write amplifier that forms write data is connected to the common data line. MOSF of the above column switch
The gates of ETMN3 and MN4 are supplied with a column selection signal YS formed by a NOR gate circuit NOR2 which also functions as a decoder and a Y driver.

The complementary data lines DT and DB are connected to the bases of differential transistors Q5 and Q6 which form a preamplifier. That is, this memory is of the column sense type. The common emitter of these differential transistors Q5 and Q6 has a switch MOS that receives the column selection signal YS.
It is connected to the constant current MOSFET MN2 via the FET MN1. At the gate of this constant current MOSFET MN2,
The constant voltage VIE is supplied to form a constant current. This constant current MOSFET MN2 corresponds to the column address when performing memory access in units of multiple bits.
It is commonly provided for a plurality of constant current MOSFETs for a preamplifier in one memory block.

The collectors of the differential transistors Q5 and Q6 are input to a sense amplifier which performs a current / voltage conversion operation via a common collector line. That is, the collectors of the transistors Q5 and Q6 have a resistor R2 in which a constant current formed by a MOSFET that receives a constant voltage VIE flows.
The bias voltage formed in (3) is connected to the emitters of the transistors Q7 and Q8 supplied to the bases. Constant current MOSFETs MN5 and MN7 for receiving a constant voltage VIE are provided at the emitters of these transistors Q7 and Q8,
The collector is provided with resistors R1 and R3 for current / voltage conversion.

A high level / low level corresponding to the storage information of the selected memory cell is output to the complementary data lines DT and DB. Receiving this high level / low level, the differential transistors Q5 and Q6 forming the sense amplifier are turned on / off. A constant current flows through the resistor R1 or R3 corresponding to the ON / OFF state of the differential transistor via the MOSFET MN1 and the like that are turned on by the column selection signal YS. The read signal converted into a voltage signal by the resistors R1 and R3 is output through an emitter follower circuit including transistors Q9 and Q10 and emitter resistors R4 and R5.

The transistors Q1 and Q2 constitute a write recovery circuit, which is turned on by a recovery signal WRC generated after the writing is completed, and the write signal is transmitted, so that the transistors Q1 and Q2 have a relatively large level difference. The complementary data lines DT and DB are reset at high speed. The recovery signal WRC is output via the emitter follower output transistor. Therefore, in the complementary data lines DT and DB, the transistors Q1 and Q2 are connected to the output transistor that forms the recovery signal WRC in the Darlington form, so that the bias level corresponding to the bias circuit (transistors Q3 and Q4) circuit is set. -2
Brought to a level equal to VBE.

In such a semiconductor memory device, a MOSFET as a current source is provided, and constant current consumption is performed even when memory access is not performed. Therefore, as in the embodiment of FIG. 3, it is possible to lower the operating voltage of the semiconductor memory device in which the memory is not accessed, reduce the amount of heat generation thereof, and lower the overall temperature. is there.

FIG. 7 shows a circuit diagram of an embodiment of the step-down power supply circuit. The circuit symbols given to the circuit elements in the figure overlap with those in FIGS. 3 and 6, but it should be understood that each has a separate circuit function. In this embodiment, P-channel type differential MOSFETs Q1 and Q
N-channel MOSFETs Q3 and Q are connected to the drain of 2.
4 is provided as a load in the form of a current mirror. The sources of the differential MOSFETs Q1 and Q2 and the ground potential VC of the circuit
A P-channel MOSFET Q5 is provided as a constant power source between C and C.

The output signal of the differential amplifier circuit as described above is supplied to the output MOSFET Q of the N-channel type MOSFET.
It is transmitted to the gate of 6 and the output voltage VD from its drain
D is output. A P-channel MOSFET Q7 as a constant current load is provided at the drain of the output MOSFET Q6. The output signal VDD of such a differential amplifier circuit
Is fed back to the gate of the MOSFET Q1 which is an inverting input to form a voltage follower, and the MO which is a non-inverting input.
Reference voltage V corresponding to the step-down voltage at the gate of SFETQ2
Supply L. With this configuration, the constant current MOSFET Q
When a constant voltage VD that allows a constant current to flow is supplied to 5 and Q7 to activate the amplifier circuit, the output voltage VDD is reduced to a step-down voltage corresponding to the reference voltage VL.

When the temperature of the semiconductor chip is low, it is necessary to set the output voltage VDD to a voltage corresponding to the power supply voltage VEE. Such a voltage switching function is provided by the output MOSF.
It is performed by the switch control of ETQ6. That is,
Output MOSFET Q6 gate and circuit ground potential VCC
A P-channel MOSFET Q8 is provided between them. The switching signal V is applied to the gate of this MOSFET Q8.
H is supplied.

Although not particularly limited, when the high voltage detection signal is not formed, the control signal VH is generated by the detection signal.
Is set to a low level corresponding to the power supply voltage VDD. As a result, the P-channel MOSFET Q8 is turned on and a high level such as the ground potential of the circuit is supplied to the gate of the output MOSFET Q6, so that it is turned on and the power supply voltage VEE is output as the output voltage VDD. At this time, the constant voltage VD is set to the high level to turn off the P-channel MOSFETs Q5 and Q7 to stop the operation of the amplifier circuit. Since the signals VH and VD only need to have a complementary relationship, the control signal VH may be inverted by an inverter circuit to form the voltage VD.

In the amplifier circuit as described above, the output MO
A capacitor for phase compensation may be inserted between the gate that is the input of the SFET Q6 and the output terminal. Further, a time constant circuit consisting of a capacitor C and a resistor R is provided at the output terminal to stabilize the output voltage VDD.

The step-down power supply circuit is formed based on the high temperature detection signal, in addition to the output MOSFET of the amplifier circuit having the switch function, as well as the step-down circuit and the switch circuit for outputting the power supply voltage VEE as it is. A circuit that complementarily operates according to the control signal to switch the power supply voltage VEE or the stepped-down voltage and output it may be used.

The operation and effect obtained from the above embodiment are as follows. That is, (1) the operating voltage is absolute value by the temperature detection circuit and its detection output or the control signal input from the outside to the memory circuit which has a circuit form in which the operation speed is substantially regulated in accordance with the current flowing in the MOSFET. By providing a step-down circuit that switches to a small voltage, the step-down circuit operates at a high temperature close to the standard upper limit value to reduce the operating voltage and suppress heat generation. The effect that the operation speed can be secured is obtained.

(2) As a step-down power supply circuit, an operational amplifier circuit including a differential amplifier circuit and an output MOSFET is made into a voltage follower form to output a reference voltage corresponding to a voltage whose absolute value is small. By turning on the output MOSFET of the operational amplifier circuit and outputting the power supply voltage as it is, it is possible to obtain two types of operating voltages with a simple circuit.

(3) By stacking and mounting the semiconductor memory devices having the function as described in (1) above, it is possible to obtain the effect that a memory device can be obtained in which the operation speed is maintained while achieving high density mounting. .

(4) The semiconductor memory devices of (1) above are stacked and mounted, and the step-down power supply circuit is controlled by the temperature detection signal of itself or a temperature detection signal formed by another semiconductor memory device stacked. By switching the operating voltage to a voltage that is small in absolute value,
The effect that the temperature rise of the entire memory module can be suppressed and the operation speed can be maintained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
In the above, a plate having the same function as the cold plate may be provided on the upper surface of the semiconductor memory device provided at the uppermost stage. In this case, since the stacked semiconductor memory devices are cooled from above and below, the number of stackable semiconductor memory devices can be increased. Also,
It is also possible to sandwich a metal plate having a large heat conductivity between the semiconductor memory devices in the intermediate stage and connect it to the cold plate to enhance the cooling efficiency. Also in this case, the number of stackable semiconductor memory devices can be increased.

The method of connecting the leads of the stacked semiconductor memory devices to the electrodes of the circuit board includes the method of inserting the leads into the through holes of the circuit board as described above, and the leads bent along the surface of the circuit board. Various embodiments can be adopted, such as forming a solder layer on the substrate, contacting it with the solder layer provided on the printed wiring of the circuit board, and performing soldering by heat treatment. As the mounting method of the semiconductor memory device, any method other than the stacking method as described above may be used as long as it is used under the condition that heat dissipation is bad.

The static RAM may have a TTL interface as well as an ELC interface. In this case, since the positive power supply voltage VDD is used as the operating voltage, the step-down circuit of FIG. 7 may be formed by reversing the conductivity type of the MOSFET.

The temperature control in the semiconductor memory device is necessary for maintaining the operation speed in the static RAM or the like, and the stored information is lost in the nonvolatile memory device such as the EEPROM in which the erasing operation is electrically performed. It is necessary to prevent the accident. Therefore, the semiconductor memory device such as an EEPROM can be used in the same manner even when it is used under the condition that heat dissipation is bad such as stacking and mounting as described above.

The present invention can be widely used for a semiconductor memory device whose operation speed is regulated by a current flowing in a MOSFET and a memory device using the semiconductor memory device.

[0065]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the operating voltage is made small in absolute value by the temperature detecting circuit and its detection output or the control signal input from the outside in the memory circuit having a circuit form in which the operating speed is substantially regulated corresponding to the current flowing in the MOSFET. By providing a step-down circuit that switches to voltage, the operating current at high temperature can be reduced by that amount and heat generation can be suppressed, so that it is possible to enter a heat saturation state at an apparently low temperature.
A predetermined operation speed can be secured. By stacking and mounting the semiconductor memory devices having such a function, it is possible to obtain a memory device capable of high-density mounting and maintaining an operation speed.

[Brief description of drawings]

FIG. 1 is a schematic side view showing an embodiment of a memory device using a semiconductor memory device according to the present invention.

FIG. 2 is a schematic block diagram showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 3 is a schematic block diagram showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 4 is a circuit diagram showing an embodiment of a temperature detection circuit.

FIG. 5 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

FIG. 6 is a circuit diagram showing an embodiment related to one complementary data line in the static RAM shown in FIG.

FIG. 7 is a circuit diagram showing an example of a step-down power supply circuit.

FIG. 8 is a plan view showing an embodiment of a memory module according to the present invention.

[Explanation of symbols]

 VC ... Voltage comparison circuit, IC ... Semiconductor memory device.

Claims (7)

[Claims] 1. A memory circuit having a circuit form in which an operating speed is substantially regulated corresponding to a current flowing through a MOSFET, a temperature detection circuit, and an output signal of the temperature detection circuit or a control signal input from the outside. A semiconductor memory device comprising: a step-down power supply circuit that switches an operating voltage applied to the memory circuit to a voltage whose absolute value is small. 2. The temperature detecting circuit detects a high temperature corresponding to a standard upper limit value by utilizing temperature dependence of a forward voltage of a diode type transistor or a PN junction diode. The semiconductor memory device according to claim 1. 3. The step-down power supply circuit uses an operational amplifier circuit including a differential amplifier circuit and an output MOSFET as a voltage follower to output a reference voltage corresponding to a voltage having a small absolute value, and a low voltage according to a control signal. 3. The semiconductor memory device according to claim 1, which has a function of turning on the output MOSFET of the operational amplifier circuit at the time of temperature and outputting the power supply voltage as it is. 4. The semiconductor memory device according to claim 1, wherein the memory array portion is composed of a CMOS circuit, and the peripheral circuit thereof is a CMO.
3. A composite circuit composed of an S circuit and a bipolar transistor, wherein an operating current is formed by a MOSFET.
Alternatively, the semiconductor memory device according to claim 3. 5. A memory circuit having a circuit form in which an operating speed is substantially regulated corresponding to a current flowing through a MOSFET, a temperature detection circuit, and an output signal of the temperature detection circuit or a control signal input from the outside. A semiconductor memory device including a step-down power supply circuit that switches an operating voltage applied to the memory circuit to a voltage whose absolute value is small is stacked and mounted, and the temperature detection signal of the semiconductor memory device itself or another stacked semiconductor memory device. A memory device characterized in that the operating voltage is switched to a voltage whose absolute value is small by controlling the step-down power supply circuit by the temperature detection signal formed by. 6. The memory according to claim 5, wherein the lowest semiconductor memory device among the plurality of stacked semiconductor memory devices is mounted on a plate having a cooling function. apparatus. 7. The semiconductor memory device to be stacked has a lead connected to an electrode provided on a circuit board having a mounting surface along the stacking direction. 6 memory devices.