JP3091545B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a TTL (Complementary MOS) level compatible with a CMOS (complementary MOS) level of about 3 V, which is mounted on a semiconductor integrated circuit device operated by a 5 V power supply voltage. The present invention relates to a technique which is effective when used for forming an output signal.

[0002]

2. Description of the Related Art An international interface specification of a CMOS circuit considering a low voltage operation is described in 1984 JE.
LVCMOS described in DEC STANDARD No.8
(LowVoltage CMOS) and LVBO (Low Voltage Battery)
Operated CMOS).

[0003]

The inventor of the present application has developed a conventional 5 V type semiconductor integrated circuit for the time being, even if a semiconductor integrated circuit device operating at a low voltage as described above has been developed. Considering that one digital information processing system is configured by mixing the device and the above-mentioned semiconductor integrated circuit device operating at a low voltage such as about 3 V system, the low voltage of the low voltage is provided by a 5 V system TTL output interface. It has been considered to add a function of forming an output signal corresponding to a semiconductor integrated circuit device. An object of the present invention is to provide a semiconductor integrated circuit device having a TTL interface output circuit having a desired level limiter function. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0004]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, the comparator compares a reference voltage corresponding to the signal level of the low-voltage circuit, which is lower than the operating voltage of the TTL interface output circuit, with the output signal of the output circuit, and the output signal of the comparator compares the output signal. The variable impedance element is controlled so that the signal has a desired level corresponding to the reference voltage.

[0005]

According to the above-mentioned means, it is possible to form a signal corresponding to a low-voltage circuit whose level is arbitrarily limited by setting a reference voltage.

[0006]

FIG. 1 is a circuit diagram showing one embodiment of a TTL interface output circuit according to the present invention. Each circuit element shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a Bi-CMOS circuit manufacturing technique.

[0007] Signals A and B formed by a TTL circuit or a Bi-CMOS circuit in which a CMOS circuit and a TTL output circuit are combined, switch the emitter follower output transistor T1 and MOSFET Q1 in a complementary manner. The emitter of the transistor T1 and the MOSFE
Between the drain of TQ1, a transistor T2 in the form of a diode by connecting the base and the collector in common is provided as a level shift means. The level shift transistor T2 and MOSFET Q1
Are connected to an external terminal OUT, and an output signal is transmitted from the external terminal OUT.

In this embodiment, the operating voltage VCC of the TTL output circuit is a voltage such as 5V. On the other hand, a semiconductor integrated circuit device such as a 3.3 V memory or a microprocessor is connected to the external terminal OUT. In the output circuit using the TTL interface, the high-level output signal VOH is determined by about VCC-2VBE. Here, VBE is the transistor T1,
This is the base-emitter voltage of T2. Therefore, the output signal VOH increases with an increase in the power supply voltage VCC, and becomes higher than a low operation voltage such as 3.3V. When a signal higher than the operating voltage is supplied from the outside in this manner, latch-up or the like due to the supply of a voltage higher than the internal voltage to a semiconductor region such as a drain or a source of a MOSFET connected thereto is likely to occur. There is a problem that the risk increases.

In this embodiment, a potential setting circuit having the following level limiter function is added to the TTL output circuit as described above, and a high-level output limited to a desired level independently of the power supply voltage VCC is provided. This is to obtain the signal VOH. That is, N of the TTL output circuit
The channel type MOSFET Q1 is provided with a transistor T3 for a level limiter in a parallel form, and the base thereof has a comparator C receiving a reference voltage Vx and a TTL output signal.
P is provided. The reference voltage Vx is determined according to the input signal level of the semiconductor integrated circuit device that receives the TTL output signal. For example, in the case of operating at a low voltage of 3.3 V, the reference voltage Vx is set to 3.3 V.

The operation of the circuit of this embodiment will now be described with reference to the operation waveform diagram of FIG. When the output signal changes from the low level to the high level and the power supply voltage VCC at that time is made relatively high, when the output signal exceeds the reference voltage Vx corresponding to about 3.3 V, the output signal of the comparator CP changes from the low level to the high level. Level and the transistor T3 is turned on. The ON state of the transistor T3 limits the rise of the output signal level to a voltage corresponding to the reference voltage Vx. That is, the transistor T3 acts as a variable impedance element, and stabilizes the TTL output signal in accordance with the reference voltage Vx by the feedback path including the comparator CP and the transistor T3.

FIG. 2 is a circuit diagram showing one embodiment of the comparator CP. In this embodiment, a transistor T4 is used, a TTL output signal is supplied to its base, and a reference voltage is supplied to its emitter. In this case, the reference voltage is not the voltage level itself to be limited, but
This voltage is lower than the output voltage to be limited by the voltage VBE between the base and the emitter of the transistor T4.

The reference voltage is formed by the following circuit.
A transistor T6, a resistor R5 provided at its base and emitter, and a resistor R4 provided at its base and collector
Constitutes a first constant voltage circuit. The transistor T5 and the resistors R2 and R3 having the same configuration constitute a second constant voltage circuit. The constant current I (= VBE / R5) is applied to the resistor R5 by the base and emitter constant voltages of the transistor T6.
And flowing this constant current I through the resistor R4,
V is applied between the collector and the emitter of the transistor T6.
A constant voltage such as BE (1 + R4 / R5) is formed. Similarly, a constant voltage VBE (1 + R2 / R3) is formed by the transistor T5 and the resistors R2 and R3. These constant voltages are added and supplied to the emitter of the transistor T4 acting as a comparator. The TTL output signal is supplied to the base of the transistor T4 via the resistor R1.

The transistor T3, which operates as a level limiter provided between the output terminal of the TTL output circuit and the ground potential point of the circuit, has an emitter resistor R6 for limiting current when a high voltage is supplied due to aging, etc. A transistor T7 is provided in which a voltage generated by the resistor R6 is supplied to a base and an emitter. This transistor T
The collector of the transistor 7 is connected to the base of the transistor T3.

The operation of the comparator and the current limiting circuit of this embodiment is as follows. When the TTL output signal is equal to or lower than the reference voltage + VBE, the transistor T4 is off, and accordingly, the base current is not supplied to the transistor T3, so that the transistor T4 is off. TTL
When the output signal is made higher than the reference voltage + VBE,
The transistor T4 is turned on, and supplies a current necessary for the constant voltage operation of the constant voltage circuit and a base current to the transistor T3. As a result, the transistor T3 is turned on, and the level limiting operation starts.

[0015] In response to the TTL output circuit VCC is relatively high by aging or the like, Utosuru by relatively large current flows through the transistor T3. However, at this time, the transistor T7 is turned on, the level limiting operation is released by the transistor T3, and the TTL output signal is raised corresponding to the power supply voltage VCC.

FIG. 4 is a circuit diagram showing another embodiment of the TTL interface output circuit according to the present invention. In this embodiment, the above-described level limiting circuit is provided on the base side of the emitter follower output transistor T1. At this time, assuming that the output level to be limited is VOH ', the reference voltage Vx is VOH + 2VB
A voltage such as E is set. That is, the power supply voltage VC
When the base potential of the output transistor T1 is to be increased by increasing C, the level is changed to the power supply voltage V
A desired output voltage VOH 'can be obtained by limiting the voltage to VOH' + 2VBE regardless of the rise of CC. Also in this embodiment, a comparator using a constant voltage circuit as shown in FIG. 2 can be used.

FIG. 5 is a block diagram showing one embodiment of a microcomputer system to which the present invention is applied. The memory device MEC is an external memory device such as a memory card, for example, and among the circuit blocks included in the memory card, each of the circuit blocks except for the battery is configured by a CMOS integrated circuit device including one chip. Although not particularly limited, the plurality of semiconductor chips are integrally housed together with the battery in a card-shaped package.

The semiconductor memory RAM is composed of a plurality of 1 to N, each of which is
It has a control terminal CT, a data terminal DT, and an address terminal AT. Each of the control buses CB2 and CB3, the data bus DB2 and the address bus AB2 is composed of a plurality of signals. Each control terminal CT, the data terminal DT, address terminals AT and the terminal T C 5~T C 8 are provided corresponding to the number of signal lines of the control bus CB, a data bus DB and an address bus AB. By using the N semiconductor memory RAMs, the storage capacity of the memory card is set to N times the storage capacity of one RAM.

Although not particularly limited, a semiconductor memory RAM
Is a pseudo-static RAM (hereinafter simply referred to as PSRAM) in which an input / output interface is made compatible with a static RAM while using a dynamic memory cell including an address selection MOSFET and an information storage capacitor. .).
By using a dynamic memory cell as a memory cell as described above, a relatively large storage capacity can be realized even in a limited mounting space such as a memory card. Instead of this configuration, a static RAM
May be used.

The control circuit CONT selects one or a plurality of the semiconductor memory RAMs and controls the operation mode. That is, the control circuit CONT
Is connected to a terminal T C1 of the microcomputer system MCS via a control signal dedicated terminal T C5 . The control circuit CONT receives the control signal output from the microprocessor MPU via the control bus CB1 and the terminal T C1 , decodes the upper bit system address, and stores one of the N semiconductor memory RAMs. A chip enable signal to be selected, a write enable signal for read / write control, an output enable signal, and the like are generated.

The data terminal DT of the semiconductor memory RAM
Data bus DB2 connected to the data-only terminal T C
6 is connected. An address bus AB2 connected to an address terminal AT of the semiconductor memory RAM is connected to an address dedicated terminal T C7 .

The power supply control circuit PWR includes a memory card ME
Receiving a battery voltage of the battery (lithium or the like) mounted in the interior of the C, and a power supply voltage supplied from the power supply circuit PCKT microcomputer system MCS via the supply voltage terminals T C 8, depending on the operating mode To switch the voltage and supply it to the internal semiconductor memory RAM and control circuit CONT. For example, when the semiconductor memory RAM is in a data holding state, the power supply control circuit PWR supplies a voltage of a battery mounted inside the memory card MEC. On the other hand, when the memory card MEC of this embodiment is connected to the microcomputer system MCS and a read / write operation is performed, the memory card MEC is switched to a power supply voltage for operating the microcomputer system MCS. In this case, the microcomputer system MCS constitutes a portable microcomputer system such as a laptop type, a notebook type or a palmtop type, and various personal computers, although not particularly limited.

Each circuit block of the microcomputer system MCS (excluding the battery and the display mounted on the power supply circuit) is constituted by a semiconductor integrated circuit consisting of one chip. Microcomputer system M
The CS has a program memory PMEM in which instructions to be executed by the microprocessor MPU are written, and a data memory DMEM in which data to be processed by the microprocessor MPU according to instructions from the program memory PMEM or data processed is stored. . The level conversion circuit LC converts the signal level of the data stored in the data memory DMEM for display display, for example.

The microprocessor MPU, the program memory PMEM, the data memory DMEM, and the level conversion circuit LC include a control bus CB1, a data bus DB1.
And an address bus AB1. Also,
Microprocessor MPU, program memory PME
M, each circuit of the data memory DMEM is a power supply circuit PCK
A power supply voltage for operation is supplied from T.

For example, as the semiconductor memory RAM, 1
A memory card MEC is configured by using four pieces each having a data retention current of 5 μA per unit, and has a nominal capacity of 250 mAh and a CR24 only in the data retention state.
If 30 types of lithium batteries are used, the batteries need not be replaced for as long as about 520 days.

In the microcomputer system as described above, if the external memory device MEC operates at a low voltage such as 3.3 V to reduce power consumption, the microcomputer MPU, the data memory DMEM, and the microprocessor memory PMEM Is necessary to perform data transfer with the signal level of about 3V system in accordance with it.
Although the power supply voltage VCC is relatively high, such as about 5 V, the above-described level limiter function is added to the output circuit using the TTL interface.

The microprocessor MPU is 3.3
It operates at a low voltage, such as V, and the data memory DM E M and program memory PMEM existing 5V system power supply voltage VC
In the case of operation by C, a TTL output circuit having the above-mentioned level limiting function is used as an output circuit of these memories DMEM and PMEM.

A TTL output circuit provided with a potential setting circuit having a level limiting function as in this embodiment can be used as it is as an input signal of a 5-V semiconductor integrated circuit device. Therefore, the semiconductor integrated circuit device according to the present invention can be connected to a 5 V system semiconductor integrated circuit device in addition to a 3 V system low voltage semiconductor integrated circuit device.

The functions and effects obtained from the above embodiment are as follows. That is, (1) a comparator compares a reference voltage corresponding to a signal level of a low-voltage circuit, which is lower than an operation voltage of a TTL interface output circuit, with an output signal of the output circuit, and outputs an output signal of the comparator. By controlling the variable impedance element so that the output signal has a desired level corresponding to the reference voltage, an output signal corresponding to an arbitrary level-limited low-voltage circuit can be formed. Is obtained. (2) By using a transistor as a comparator and connecting a constant voltage circuit including a transistor and a resistance element to the emitter, a simple and accurate voltage control operation can be performed. (3) By controlling the TTL output signal, it is possible to obtain an effect that a latch-up phenomenon of a semiconductor element connected to the periphery can be prevented.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, TT
The L output circuit may use a transistor instead of the MOSFET Q1. As the variable impedance element, a MOSFET can be used in addition to the transistor. The semiconductor integrated circuit device is B
others are constituted by i-CMOS circuit may consist TTL circuit of bipolar transistors. The present invention constitutes a digital processing system.
It can be widely used for various semiconductor integrated circuit devices having a TL interface output circuit.

[0031]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the comparator compares a reference voltage corresponding to the signal level of the low-voltage circuit, which is lower than the operating voltage of the TTL interface output circuit, with the output signal of the output circuit, and the output signal of the comparator compares the output signal. By controlling the variable impedance element so that the signal has a desired level corresponding to the reference voltage, an output signal corresponding to an arbitrary level-limited low-voltage circuit can be formed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a TTL interface output circuit according to the present invention.

FIG. 2 is a circuit diagram showing a specific embodiment of a TTL interface output circuit according to the present invention.

FIG. 3 is a waveform chart for explaining an example of the operation.

FIG. 4 is a circuit diagram showing another embodiment of the TTL interface output circuit according to the present invention.

FIG. 5 is a block diagram showing an embodiment of a microcomputer system to which the present invention is applied.

[Explanation of symbols]

T1: emitter follower output transistor, T2: level shift transistor, Q1: output MOSFET, T
3 ... Level limiting transistor (variable impedance), CP ... Comparator, T4 ... Comparator transistor, T5, T6 ... Constant voltage transistor, R1 ...
Base resistors, R2 to R5: constant voltage resistors, MEC: memory card (memory device), MCS: microcomputer system, MPU: microprocessor, PMEM ...
Program memory, DMEM… Data memory, CB1
CB3: Control bus, AB1, AB2: Address bus, DB1, DB2: Data bus, PCKT: Power circuit, CONT: Control circuit, PWR: Power control circuit, BAT: Battery.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Akioka 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research Laboratory (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175

Claims (3)

(57) [Claims] An output circuit of a TTL interface,
A comparator for comparing the output signal with a reference voltage corresponding to the signal level of the low-voltage circuit which is lower than the operating voltage of the TTL interface output circuit, and a desired signal corresponding to the reference voltage based on the output signal of the comparator. And a variable impedance element controlled to attain an output level of the semiconductor integrated circuit device. 2. The comparator according to claim 1, wherein a resistor is provided between a collector and a base of the transistor and between the base and the emitter, and a constant voltage is obtained between the emitter and the collector.
Two level shift circuits are connected in series and connected to the emitter, and the base is made up of a transistor whose output circuit is supplied. The variable impedance element is made up of a transistor whose base is connected to a connection point of the two level shift circuits. 2. The semiconductor integrated circuit device according to claim 1, wherein: 3. The TTL interface output circuit comprises: an emitter follower output transistor and an output MOSFE connected to the emitter via a level shift diode.
3. The semiconductor device according to claim 1, wherein T is connected to the semiconductor integrated circuit device, and the output signal is supplied to a 3V system circuit. Integrated circuit device.