JPH04211512A - Bias circuit - Google Patents

Abstract

PURPOSE:To reduce the area posessed by the bias circuit in a LSI tip as much as possible, to supply stable bias voltage and to set the temperature dependence of the bias voltage to an appropriate value by controlling the constant current by means of the voltage between the base emitters of a transistor as to the bias circuit applying direct voltage to a controlling electrode of the transistor. CONSTITUTION:Based on the voltage between the control terminal of a transistor T and the terminal on the second potential power supply side, the voltage obtained by adding the applicable voltage between the terminals to the dropped voltage of a first load element is outputted as the bias voltage. Since the voltage between the terminals is kept at a prescribed value because of the structure of the transistor T, the bias voltage outputted based on the applicable voltage between the terminals is stably supplied while reducing the area posessed by the bias circuit as much as possible. The temperature dependency appropriate for that of the circuit to be connected to an output terminal Dout is set at random corresponding to the current density of a transistor T and the partial pressure of first and second load elements.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a bias circuit that applies a DC voltage to a control electrode of a transistor in order to provide a predetermined operating point, and more particularly to a bias circuit that can stably supply a DC voltage to be applied to the control electrode. Regarding. In recent years, various logic circuits using transistors have been developed, and in order for these logic circuits to perform calculation operations accurately, it is necessary to stably supply a bias voltage to the control electrode of the transistor.

In particular, ECL logic circuits (emitter coupled logic) constituting bipolar digital integrated circuits installed in ultra-large electronic computers, etc.
etc., standard voltages (VR1, VR2) or constant current bias voltages are input, and they operate based on these respective inputs. This ECL logic circuit is a CM with a large margin.
Logic amplitude is approximately 600mV for OS interface
Since it has the smallest interface, an extremely stable constant current bias voltage is required. Additionally, a clamp voltage for CDOT (collector dot) may also be required. As described above, bias circuits connected to various logic circuits are required to supply stable voltages.

0003

[Prior Art] Conventionally, this type of bias circuit is shown in FIG.
There was something shown in 3. FIG. 13 shows a circuit configuration diagram in which a conventional bias circuit is connected to an ECL. In the figure, the conventional bias circuit includes a constant current source circuit 4 that controls the current flowing between the power supplies VCC and VEE to be constant based on the potential difference determined from the difference in base-emitter voltage VBE between the transistors T5 and T6; A voltage output circuit 5 that outputs standard voltages VR1 and VR2 that are voltage-dropped by a predetermined value from the high potential power supply VCC and a constant current bias voltage VCS based on the constant current of the constant current source circuit 4, and the temperature of the ECL side. This configuration includes a temperature compensation circuit 6 that compensates for dependence.

Next, the operation of the conventional bias circuit based on the above configuration will be explained. The transistors T5 and T6 in the constant current source circuit 4 constitute a current mirror circuit, and the base-emitter voltages VBE5 and VB are inversely proportional to the emitter area of each transistor T5 and T6.
Since E6 is generated, an emitter current corresponding to the current flowing between the power supplies VCC and VEE flows. This emitter current is defined by resistor R10.

[0005] Each base-emitter voltage VBE5
, VBE6 as a reference voltage, each standard voltage VR1, VR is lowered in potential from the higher side power supply VCC by the forward voltage between the base and emitter of the transistor T1, and further by the forward voltage of the diode D.
2 is output from the voltage output circuit 5. In addition, the constant current bias voltage VCS whose potential is lowered by the forward voltage between the base and emitter of the transistor T3 is applied to the voltage output circuit 5.
Output from.

[0006]The temperature compensation circuit 6 is connected to the voltage output circuit 5.
In order to compensate for the temperature dependence of ECL transistors driven based on bias voltages such as standard voltages output from the ECL transistor, the temperature dependence is compensated by a voltage drop corresponding to the base-emitter voltage VBE7 of the transistor T7, etc. ing.

[0007]

Problem to be Solved by the Invention Since the conventional bias circuit is configured as described above, the transistor T
5, each base-emitter voltage VBE5 of T6,
In order to create a difference in VBE6, each transistor T5
, T6 must be made different in emitter area, or the current of transistor T5 must be made smaller.

When providing a difference in the emitter area of each of the transistors T5 and T6, the emitter area is made small in order to make the transistor T6 with a large base-emitter voltage VBE6, and the emitter area is made small in order to make the transistor T6 with a large base-emitter voltage VBE5. To make T5, the emitter area must be increased. When the transistor T6 having a small emitter area is manufactured, a large manufacturing error occurs in the emitter area, and the value of the base-emitter voltage VBE6 becomes non-uniform. Furthermore, when the transistor T5 with a large emitter area is manufactured, the area occupied by the transistor increases, and even if the area is twice as large as that of the transistor T6 with a small emitter area, a difference of only about 20 mV can be generated. ,1
When the area is set to 0 times, only a very small voltage of about 60 mV can be obtained (see FIG. 14).

[0009] From the above, conventional bias circuits have the problem that the bias voltage becomes non-uniform due to manufacturing errors that occur during manufacturing, is not stabilized, and temperature dependence is disturbed, and the chip area of the LSI increases. We had the challenge of doing so. In addition, the base temperature dependence is small to begin with.
Since the bias voltages (VR1, VR2, VCS) are generated based on the potential difference of the emitter voltage VBE,
It has been difficult to set the temperature dependence of the bias voltage to match the temperature dependence of the ECL side to which the bias voltage is applied. Therefore, at high temperatures, the power supply current increases and the noise margin decreases, resulting in increased heat generation and malfunctions.

Furthermore, when the potentials of the power supplies VCC and VEE fluctuate, the output bias voltage also changes and becomes unstable. The present invention has been made to solve the above problems, and by controlling a constant current source using the voltage between the base and emitter of the transistor itself, the area occupied by the bias circuit in the LSI chip can be reduced as much as possible, and a stable bias voltage can be maintained. It is an object of the present invention to provide a bias circuit that can supply a bias voltage and set the temperature dependence of a bias voltage to an appropriate value.

[0011]

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the first invention. In the figure, the bias circuit according to the first invention is
A transistor (T4) connected between the first and second potential power sources having a potential difference, an output terminal (Dout) that outputs a bias voltage to other circuits, and a control terminal and output terminal of the transistor (T4). (Dout) and the transistor (T4
) and a second load element connected between the control terminal of the transistor (T4) and the second potential power supply side;
The voltage between the control terminal of the first
A voltage obtained by adding a voltage corresponding to the voltage drop due to the load element is output from the output terminal (Dout) as a bias voltage.

Further, FIG. 2 shows a diagram explaining the principle of the second invention. In the figure, the bias circuit according to the second invention is
In addition to the configuration of the invention described in claim 1, in the bias circuit according to claim 1, based on the bias voltage connected between the first and second potential power supplies and output from the output terminal (Dout), a constant current source section (2) that controls the current flowing between the first and second potential power sources to be constant; and a constant current source section (2) connected between the constant current source section (2) and the first potential power source, and The bias voltage of output terminals (Dout1~Dou
tn).

Further, FIG. 3 shows a diagram explaining the principle of the third invention. In the figure, the bias circuit according to the third aspect of the present invention includes two transistors (T4
), (T7), and multiple output terminals (Dout, Dout1 to Dout) that output multiple bias voltages to other circuits.
n) and a first transistor connected between the control terminal of the one transistor (T4) and the one output terminal (Dout).
a second load element connected between the control terminal of the first transistor (T4) and the second potential power source, and a second load element connected between the first and second potential power sources. ,
a constant current source section (2) that controls a current flowing between the first and second potential power sources to be constant based on a bias voltage output from the first output terminal (Dout); and the constant current source section. (2) and the first potential power supply, and supplies another bias voltage to the other output terminals (Dout1 to Doutn
) and a voltage output section (3) for outputting another bias voltage to the control terminal of the other transistor (T7).

[0014]

[Operation] As shown in FIG. 1 above, in the first invention,
Based on the inter-terminal voltage between the control terminal of the transistor T4 and the second potential power supply side terminal, a voltage obtained by adding the voltage corresponding to the voltage drop of the first load element to the inter-terminal voltage is output as a bias voltage. . Since the voltage between the terminals is a constant value determined by the structure of the transistor T4, the bias voltage output based on the voltage between the terminals is controlled while minimizing the area occupied by the bias circuit. Provide stable supply. Also, depending on the current density of the transistor T1 and the voltage division ratio of each of the first and second load elements, the output terminal Do
Temperature dependence suitable for the temperature dependence of the circuit connected to ut is arbitrarily set.

Further, in the second invention shown in FIG. 2, a bias voltage is output based on the voltage between the control terminal of the transistor T1 and the second potential power supply side terminal, and the bias voltage is The constant current source unit (2) is controlled based on the constant current source to form a constant current source, and the voltage output unit (3) outputs another bias voltage based on the constant current of the constant current source. Since the terminal voltage has a constant value in this way, the bias voltage and other bias voltages having different potential levels from the bias voltage are controlled based on this constant terminal voltage, so that the area occupied by the bias circuit is minimized. Stable supply in the same condition. Also, the current density of the transistor T1, the first
- The output terminals Dout, Dout1 to Doutn are adjusted by the voltage division ratio of each second load element and the potential adjustment of the voltage output circuit.
The temperature dependence is arbitrarily set to suit the temperature dependence of the circuit connected to the circuit.

Further, in the third aspect of the present invention shown in FIG. 3, a constant current is output from the constant current source section (2) based on a bias voltage of a constant value specified by the structure of the transistor T4, Based on the constant current, other bias voltages are stably output from the voltage output section (3). Another transistor T7 having a different conductivity type from the one transistor T4 is input with another bias voltage as a control voltage, and the voltage between the control terminal and the first potential power supply side terminal is specified by the structure of the transistor itself. is maintained at a constant value. The voltage between the terminals of the other transistor T7 is held constant, and the current flowing through the two transistors T4 and T7 connected in series is a constant current, and the potential level of each of the first or second potential power sources fluctuates. A constant current is supplied to one transistor T4.

[0017]

【Example】

(a) An embodiment of the first invention Hereinafter, an embodiment of the first invention will be described based on FIG. 4. FIG. 4 shows a configuration diagram of this embodiment. In the same figure, the bias circuit according to this embodiment has a high potential power supply VCC (GN
D), a transistor T4 connected between the other end of the resistor R3 and the low potential power supply VEE, and one end connected to the connection point between the transistor T4 and the resistor R3. In addition, the transistor T4
a resistor R4 whose other end is connected to the base terminal of the resistor R4, a resistor R5 which is connected between the other end of the resistor R4 and the low potential power supply VEE, and a resistor R5 which is connected to the connection point between the transistor T4 and the resistor R4. This configuration includes an output terminal Dout.

Next, the operation of the circuit of this embodiment based on the above configuration will be explained. First, a current from the high potential power supply VCC is supplied to the collector terminal of the transistor T4 and the resistors R4 and R5 via the resistor R3. The base-emitter voltage VBE4 of the transistor T4 is a value determined structurally at the time of manufacture, and is constant at about 0.8V. This constant base-emitter voltage of 0.8V is applied across the resistor R5, and the current flowing through the resistor R5 becomes a constant current. The constant current flows through a resistor R4 connected in series with a resistor R5.
produces a constant voltage drop (V4 - V5). The relationship between the voltages corresponding to the respective voltage drops of the resistors R4 and R5 is expressed by the following equation. In addition, in this formula, V4 and V5 are V
The EE potential is used as a reference (0V).

[0019] V4 /V5 = (R4 +R5)/R5 where V
Since 5 = VBE4, V4 /VBE4
=(R4 +R5)/R5 V4 =VBE4 ×(
R4 + R5 )/R5...Equation-1 From this equation-1, the constant current bias voltage VCS is output from the output terminal Dout as VBE4 x (R4 + R5)/R5.

Since the constant current bias voltage VCS is a value obtained by multiplying the base-emitter voltage VBE4 of the transistor T4 by (R4 + R5)/R5,
Even if some error occurs in the emitter area during transistor manufacturing, the influence on the base-emitter voltage VBE4 is extremely small, and a stable voltage value can be achieved. That is, since the base-emitter voltage VBE4 of the transistor T4 is approximately 0.8V (=800mV), even if VBE4 fluctuates by 10mV due to manufacturing error in the emitter area, the error is only 1.25% of the total. First, an extremely stable bias voltage can be obtained.

In this way, the conventional bias circuit (FIG.
3) is the difference in voltage between each base and emitter (VBE5
-VBE6), the bias voltage is output based on VBE5 -VBE6 = 60mV.
If mV were to fluctuate, this would result in a large error of about 17%, but in this embodiment, the error can be kept to 1.25%. (b) An embodiment of the second invention Hereinafter, an embodiment of the second invention will be described based on FIG. 5. FIG. 5 shows a circuit configuration diagram in which this embodiment is connected to an ECL.

In the figure, the bias circuit according to the present embodiment is constructed in the same manner as the first embodiment of the present invention (described in FIG. 4), and the bias circuit according to the present embodiment is configured based on the base-emitter voltage VBE4 of the transistor T4. A reference voltage generation circuit 1 that generates a bias voltage VCS as a voltage, and a constant voltage regulator that controls the current between the high potential side and low potential side power supplies VCC and VEE to be constant based on the bias voltage VCS of the reference voltage generation circuit 1. The configuration includes a current source circuit 2 and a voltage output circuit 3 that generates standard voltages VR1 and VR2 that are voltage-dropped by a predetermined value from a high potential power supply VCC based on a constant current controlled by the constant current source circuit 2.

The constant current circuit 2 includes a series circuit of a transistor T2 and a resistor R6, a transistor T3 and a resistor R6, and a series circuit of a transistor T2 and a resistor R6.
7 series circuit and each high potential/low potential power supply VCC-V.
The transistors T2 and T3 are connected in parallel between EE and the transistors T2 and T3.
The bias VC of the reference voltage generation circuit 1 is connected to the base terminal of
S is applied to supply a constant current specified by the bias voltage VCS. The voltage output circuit 3 is connected to a high potential power supply VC.
a series circuit of a transistor T1 and a diode D connected between C and the collector terminal of the transistor T3; and a resistor connected between the high potential power supply VCC and the collector terminal of the transistor T2 and the base terminal of the transistor T1. R1, and the transistor T1 and diode D generate reference voltages VR1 and VR2 whose potentials are lowered by their respective forward voltages.

Next, the operation of the circuit of this embodiment based on the above configuration will be explained. First, in the same manner as in the first embodiment of the present invention (shown in FIG. 4), a stable constant current bias voltage VCS is generated from the reference voltage generation circuit 1 while minimizing the area occupied by the circuit. do. The transistors T2 and T3 are driven based on this bias voltage VCS, and the respective VBE2 and VB of the transistors T2 and T3 are driven.
Since E3 is fixed, transistor T2
and a series circuit of resistor 6, transistor T3, and resistor R
The current flowing through each of the 7 series circuits is a constant current.

The constant current flows through the resistor R1 to cause a voltage drop, and this dropped voltage is applied to the base terminal of the transistor T1, which corresponds to the voltage drop from the high potential power supply VCC to the resistor R1 and the VBE of the transistor T1. The potential lowered by the voltage drop is output as the standard voltage VR1. Further, a potential lowered by the forward voltage of the diode D from the standard voltage VR1 is output as the standard voltage VR2.

As described above, the bias voltage VCS and the standard voltages VR1 and VR2 are all generated and outputted via the respective VBE2 and VBE3 of the transistors T2 and T3 using the VBE4 of the transistor T4 as a reference. That is, since the emitter areas of VBE2, VBE3, and VBE4 of the transistors T2, T3, and T4 have small variations due to manufacturing errors, the bias voltage V
Both CS and standard voltages VR1 and VR2 will be output extremely stably.

Next, the temperature dependence in this embodiment is determined by the voltage division ratio of resistors R4 and R5 and the transistors T1 to T4.
By adjusting the current density of the diode D and the current density of the diode D, the temperature dependence can be controlled to match the temperature dependence of the gate circuit (ECL). (c) Other embodiments of the second invention Another embodiment of the second invention will be described with reference to FIG. 5, which shows the embodiment.

The bias circuit according to this other embodiment has the same circuit connection configuration as the embodiment shown in FIG. Transistor T2
, T3. The relationship between the current densities is as follows.

[0029]

[Math 1]

By setting each current density in this manner, the temperature dependence of the circuit itself can be eliminated. (d) Other Embodiments of the First and Second Inventions FIGS. 6 to 10 show embodiments in which the connection point of the resistor R3 in the reference voltage generation circuit 1 has various configurations. Also, Figure 1
1 is an embodiment in which the diode D provided in the voltage output circuit 3 of each of the embodiments described above is omitted.

In the embodiment shown in FIG. 6, the resistor R3
One end of is connected to the output end of diode D,
Standard voltages VR1, VR2 and bias voltage VCS determined based on the forward voltages of transistor 1 and diode D can be output. The embodiment shown in FIG. 7 has a configuration in which one end of the resistor R3 is connected to the connection point between the transistor 1 and the diode D.
The standard voltage VR1, V determined based on the forward voltage of
R2 and bias voltage VCS can be output.

In the embodiment shown in FIG. 8, the resistor R3
One end is connected between the resistor R2 and the collector terminal of the transistor T2, and the standard voltages VR1 and VR are determined based on the forward voltage of the transistor T1.
2 and a bias voltage VCS. In the embodiment shown in FIG. 9, one end of the resistor R3 is connected to a resistor R.
1 and a resistor R2, and can output standard voltages VR1, VR2 and bias voltage VCS determined based on the forward voltage of the transistor T1.

In the embodiment shown in FIG. 10, the resistor R3
A configuration in which one end of the is directly connected to the high potential power supply VCC,
The voltage output circuit 3 can output standard voltages VR1, VR2 and bias voltage VCS with appropriate temperature dependence. The embodiment shown in FIG. 11 has a configuration in which the diode D is removed from the structure of the embodiment in FIG. 6, and can output a single standard voltage VR1 and bias voltage VCS.

In the embodiments of the first and second inventions, the reference voltage generating circuit 1 is a bipolar transistor.
transistor T4 and resistors R4 and R5 for pure resistance
However, it is also possible to use a MOSTr other than a bipolar Tr, and any load element that produces a voltage division ratio, such as a load MOS or a varistor (varrable resistor) other than a pure resistance component, can also be used. .

Further, in the embodiments of the first and second aspects of the invention, the resistor 4 is connected between the collector and the base of the transistor T4, but one end of the resistor 4 is connected only to the base of the transistor, It is also possible to configure the other end of the resistor 4 to be the output end (Dout). Further, in the embodiments of the first and second inventions, the voltage output section 3 is configured to output one or two standard voltages VR1, VR2, but it may be configured to output three or more standard voltages VR1...VRn. You can also.

Furthermore, in the embodiments of the first and second inventions, both transistors are bipolar transistors.
However, it is also possible to use a bi-MOS circuit in which a MOS and a bipolar are integrated on a chip. (e) An embodiment of the third invention An embodiment of the third invention will be described based on FIG. 12.

FIG. 12 shows a circuit configuration diagram in which this embodiment is connected to an ECL. In the same figure, the bias circuit according to this embodiment is an embodiment of the second invention (described in FIG. 5).
Similarly, it includes a reference voltage generation circuit 1, a constant current power supply circuit 2, and a voltage output circuit 3, but the configuration of the reference voltage generation circuit 1 is different. The reference voltage generation circuit 1 has a high potential power supply VC.
a resistor R14 whose one end is connected to C (GND); and a resistor R14 whose emitter terminal is connected to the other end of the resistor R14, and whose base terminal is connected to the output terminal of the voltage output circuit 3.
np transistor T7 and pnp transistor T7
an npn transistor T4 whose collector terminal is connected to the collector terminal of the transistor T4 and whose emitter terminal is connected to the low potential power supply VEE; a resistor R4 connected between the collector terminal and the base terminal of the transistor T4; The configuration includes a resistor R5 connected between the other end of R4 and the low potential power supply VEE, and an output terminal Dout connected to the connection point between the transistor T4 and the resistor R4.

Next, the operation of the circuit of this embodiment based on the above configuration will be explained. First, in a stable state of the power supplies VCC and VEE, the base-emitter voltage VB is a constant value specified by the semiconductor structure of the npn transistor T4.
E4 is applied across resistor R5. Therefore, the current flowing through the resistor R5 and the resistor R4 connected in series with the resistor R5 becomes a constant current. Thereafter, a stable bias voltage VCS and a stable standard voltage VR based on this bias voltage VCS are output in the same manner as in the embodiment shown in FIG.

[0039] Here, a case will be described in which the power supply voltages of the power supplies VCC and VEE fluctuate and the potential becomes unstable. The standard voltage VR having the constant value is the pnp transistor T.
7 and is input to the base terminal of the pnp transistor T
The base-emitter voltage VBE7 of 7 is maintained at a constant value specified on the semiconductor structure. Since the base-emitter voltage VBE7 is constant, the resistor R1
A constant voltage is applied to the resistor R14-p.
A constant current is supplied to a series circuit of np transistor T7-npn transistor T4.

In this way, even when the power supply voltage fluctuates or the temperature rises, the bias voltage VCS and the standard voltage VR can be maintained constant and supplied. Further, even if the ECL logic circuit to which the bias voltage VCS and the standard voltage VR are supplied becomes high temperature, power increase and malfunction can be prevented, and a highly reliable LSI can be obtained.

[0041]

As explained above, in the first aspect of the present invention, based on the inter-terminal voltage between the control terminal of the transistor T1 and the second potential power supply side terminal, the first Since the configuration is configured to output the voltage obtained by adding the voltage equivalent to the voltage drop of the load element as the bias voltage, the bias voltage output based on the voltage between the terminals can be outputted while minimizing the area occupied by the bias circuit. It has the effect of being able to supply stably. Further, it has the effect that the temperature dependence suitable for the temperature dependence of the circuit connected to the output terminal Dout can be arbitrarily set by the current density of the transistor T1 and the voltage division ratio of each of the first and second load elements. .

Further, in the second aspect of the present invention, a bias voltage is output based on the voltage between the control terminal of the transistor T1 and the second potential power supply side terminal, and
A constant current source is configured by controlling the constant current source section based on the bias voltage, and another bias voltage is output from the voltage output based on the constant current of the constant current source.
In the same way as the invention of 2007, it is possible to stably supply a bias voltage and other bias voltages having different potential levels from the bias voltage, and the current density of the transistor T1, the voltage division ratio of each of the first and second load elements, and the voltage output section can be stably supplied. By adjusting the potential, it is possible to arbitrarily set the temperature dependence suitable for the temperature dependence of the circuit connected to the output terminals Dout and Dout1 to Doutn.

Further, in the third aspect of the present invention, in addition to the configuration of the second aspect, transistors of different conductivity types are connected in series between the first and second potential power sources, and a control terminal of the transistor is connected in series. By applying a bias voltage from the voltage output section, a constant current can be supplied to two series-connected transistors with different conductivity types, making it stable even when the power supply voltage fluctuates or other high temperatures occur. This has the effect of outputting a highly sensitive bias voltage and ensuring appropriate temperature dependence.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the first invention.

FIG. 2 is a diagram explaining the principle of the second invention.

FIG. 3 is a diagram illustrating the principle of the third invention.

FIG. 4 is a configuration diagram of an embodiment of the first invention.

FIG. 5 is a circuit configuration diagram in which an embodiment of the second invention is connected to an ECL.

FIG. 6 is a circuit configuration diagram of another embodiment.

FIG. 7 is a circuit configuration diagram of another embodiment.

FIG. 8 is a circuit configuration diagram of another embodiment.

FIG. 9 is a circuit configuration diagram of another embodiment.

FIG. 10 is a circuit configuration diagram of another embodiment.

FIG. 11 is a circuit configuration diagram of another embodiment.

FIG. 12 is a circuit configuration diagram in which an embodiment of the third invention is connected to an ECL.

FIG. 13 is a circuit configuration diagram in which a conventional bias circuit is connected to an ECL.

FIG. 14 is a diagram showing the relationship between current density and base-emitter voltage of a transistor.

[Explanation of symbols]

1...Reference voltage generation circuit 2... Constant current source circuit 3...Voltage output circuit T1 to T7...Transistor R1 ~ R7...Resistance D...Diode VCC…High potential power supply VEE…Low potential power supply

Claims (4)

[Claims] 1. A transistor (T4) connected between first and second potential power sources having a potential difference, an output terminal (Dout) that outputs a bias voltage to another circuit,
The control terminal and output terminal (Do) of the transistor (T4)
a first load element connected between the transistor (T4) and a second load element connected between the control terminal of the transistor (T4) and a second potential power supply side; The output terminal (
A bias circuit characterized in that it outputs an output from (Dout). 2. The bias circuit according to claim 1, wherein the bias voltage is connected between the first and second potential power supplies and is output from the output terminal (Dout). A constant current source section (2) that controls the current flowing between each potential power supply to a constant value;
) and a first potential power source, and a voltage output section (3) that outputs another bias voltage from output terminals (Dout1 to Doutn). 3. The bias circuit according to claim 2, wherein the constant current source section (2) is composed of a transistor (T2) to which a bias voltage outputted from an output terminal (Dout) is applied as a control voltage; Transistor (T2
), the current density of the forward current in the transistor (T4) is set to be smaller than the current density of the forward current in the transistor (T4). 4. Two transistors (T4) and (T7) of different conductivity types connected in series between the first and second potential power sources having a potential difference, and outputting a plurality of bias voltages to other circuits. Multiple output terminals (Dout, Dou
t1 to Doutn) and the first transistor (T4
a first load element connected between a control terminal of the transistor (Dout) and the first output terminal (Dout);
A second load element connected between the control terminal of T4) and the second potential power supply side, and a second load element connected between the first and second potential power supplies, and from the first output terminal (Dout). a constant current source section (2) that controls the current flowing between the first and second potential power sources to be constant based on the output bias voltage
) is connected between the constant current source section (2) and the first potential power source, and supplies another bias voltage to the other output terminal (Dout
1 to Dout2) and a voltage output section (3) that outputs another bias voltage to the control terminal of the other transistor (T7).