JPH06161927A - Data communication system - Google Patents

Abstract

PURPOSE:To provide the transfer of data even between the adaptors under the different input/output control functions in a data communication system which performs the communication of data among the adaptors. CONSTITUTION:The input/output control mechanisms 2 which control the input/ output of data are provided together with the adaptors 5 which perform various types of processing under the control of the mechanisms 2, and a common memory 4 to which the adaptors 5 can have the common accesses. A certain mechanism 2 writes a processing request into the memory 4 to the adaptor 5 under control, and this adaptor 5 takes out the requested processing contents and decides that this request is given to another adaptor 5. Under such conditions, the processing request is informed the corresponding mechanism 2. Thus the mechanism 2 received the request writes a processing request into the memory 4 to its adaptor 5 under control. Then the corresponding adaptor 5 takes out the processing request contents and carries out the processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system for data communication between adapters.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, an SPU (system process unit) and an IOP (IO processor) are used.
In this system, each SPU and IOP has a plurality of adapters under the control of each SP.
U or IOP requested the respective adapters to perform processing via CH (channel). The SPU or IOP did not request processing to the adapters under the control of other SPUs or IOPs. The configuration and operation of FIG. 5 will be briefly described below.

In FIG. 5, an SPU is a system process unit, and here, makes a processing request (for example, a processing request for data communication or the like) to a corresponding adapter under its control based on an instruction from a host. is there.

The IOP is an IO processor, which is a processor for controlling input / output, and requests processing to a corresponding adapter under its control based on an instruction from a host (for example, calling a specified telephone number). Processing request).

CH is a channel for transferring data to the adapter designated by the SPU or IOP. Adapter is SPU or IOP
Is performed (for example, processing such as calling a designated telephone number or performing data communication through a connected line).

Next, the operation will be described. (1) SPU or IO that received a processing request from the host
P analyzes the processing contents and instructs CH to notify the processing request to the corresponding adapter.

(2) Upon receipt of the instruction, the CH notifies the destination adapter of the processing request content in accordance with the instructed content (content of CCW instructed by CAW). (3) The corresponding adapter that has received the processing request content notification in (2) performs processing according to the processing content. For example, a call is made to a designated telephone number to establish a line connection with a destination computer system or to perform data communication via the connected line.

[0008]

As described above, the conventional SPU or IOP responds to the processing request from the host,
A subordinate adapter, for example, an adapter connected to the same bus is notified of a processing request via the CH, and the adapter performs processing corresponding to the processing request. Therefore, there is no particular problem when the SPU and IOP each have an adapter required under their control. However, if you do not have the required adapter under your control, there was a problem that you could not request processing. In order to solve this, it is possible to transfer data between adapters by software or by linking a plurality of adapters.

However, there is a problem that the online processing performance is deteriorated via the software depending on the processing performance of the CPU and the operating condition of each input / output device (I / O). When a plurality of adapters are linked, the processing within the own SPU can be controlled relatively easily, as shown in FIG.
In many cases, the SPU and IOP, or the IOP and another IOP are not particularly connected on the same bus, and there is a problem that cooperation is extremely difficult. At present, a CPU composed of an SPU and a plurality of IOPs is common, and it is strongly desired to perform data transfer to an adapter between the SPU and the IOP and between the IOP and the IOP.

The present invention solves these problems.
When an input / output control mechanism such as SPU or IOP writes a processing request in a common memory that the subordinate adapter can access, and when the subordinate adapter seeing this writes a processing request to another adapter, it notifies the corresponding input / output control mechanism. Then, the input / output control mechanism writes a processing request in a common memory accessible by the subordinate adapter, and the subordinate adapter seeing this performs processing, and data transfer is performed even between subordinate adapters with different input / output control functions. The purpose is to realize.

[0011]

FIG. 1 shows a block diagram of the principle of the present invention. In FIG. 1, the input / output control mechanism 2 is
It controls data input / output.

The adapter 5 performs various processes under the control of the input / output control mechanism 2. The common memory 4 is a memory that the adapter 5 can commonly access.

[0013]

According to the present invention, as shown in FIG. 1, a certain input / output control mechanism 2 writes a processing request to the subordinate adapter 5 in the common memory 4, and the corresponding adapter 5 seeing this writes the processing request content. When it is determined that the processing request is sent to another adapter 5, the corresponding input / output control mechanism 2 is notified of the processing request,
Upon receipt of this processing request, the other input / output control mechanism 2 writes a processing request to the subordinate adapter 5 in the common memory 4, and the corresponding adapter 5 seeing this writes the processing request content and processes it. .

At this time, regardless of whether the adapter 5 is connected to the same bus or another bus, the adapter 5
Data communication is performed between them. Therefore, the SPU
The I / O control mechanism 2 such as IOP writes a processing request in the common memory 4 accessible by the subordinate adapter 5, and notifies the corresponding I / O control mechanism 2 when requesting the processing to another adapter 5 5 writes a processing request in the accessible common memory 4 and requests the processing, and the subordinate adapter 5 which has seen this performs the processing, thereby transferring data even between the subordinate adapters 5 of the input / output control mechanism 2. Can be realized.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is a block diagram showing the principle of the present invention.
In FIG. 1, a CPU 1 performs various processes according to a program, and here, an input / output mechanism 2, a CH
3, a common memory 4, an adapter 5 and the like.

The input / output control mechanism 2 controls the input / output of data. Here, a processing request from a host is received, this is analyzed, and the corresponding adapter 5 is processed via CH3. For example, the request is notified.
Here, there are an input / output control mechanism (# 1) 3 and an input / output control mechanism (# 2) 3, and the input / output control mechanism (# 1) 2 is subordinate to the adapter (# 1) 5 and the adapter (# 2) 5. Have a
The input / output control mechanism (# 2) 2 is subordinate to the adapter (# 3) 5
have. A processing request is issued to the subordinate adapters 5 via CH3.

The CH 3 performs data transfer processing. Here, in response to a transfer request from the input / output control mechanism 2, the processing content is written in the common memory 4 and notified to the corresponding adapter 5. It is something to do.

The common memory 4 is a memory which the adapter 5 can commonly access. Via this common memory 4, the input / output control mechanism 2 requests the adapter 5 for processing,
The adapter 5 is for transferring a processing request to itself or another input / output control mechanism 2.

The adapter 5 executes the processing request from the input / output control mechanism 2, and for example, calls the instructed telephone number to connect the line, or performs data communication through the connected line. It is a thing.

Next, the operation of the configuration shown in FIG. 1 will be described. (1) Input / output control mechanism (#
1) 2 requests, for example, CH (# 1), writes the request content in the common memory 4, and notifies the subordinate adapter (# 1) 5 of the request.

(2) The subordinate adapter (# 1) 5 which received the processing request in (1) sees the processing contents, and here it is determined that the processing contents should be requested to the adapter of the other input / output control mechanism 2. To do.

(3) The adapter (# 1) 5 receives the input / output control mechanism (#
1) Notify the processing contents to 2. This input / output control mechanism (# 1) 2 notifies the other input / output control mechanism (# 2) 2,
The other input / output control mechanism (# 2) 2 requests the CH (# 2) 3 to write the request content in the common memory 4 and notify the subordinate adapter (# 3) 5.

(4) The subordinate adapter (# 3) 5 receiving the processing request in (3) executes the processing content. By the above, the adapter (# 1) 5 to the adapter (#
3) Data transfer to 5 has been performed.

FIG. 2 shows a block diagram of an embodiment of the present invention.
This shows the specific configuration diagram of FIG. Where 1, 3,
Since 4, 5 correspond respectively to 1, 3, 4, 5 in FIG.

In FIG. 2, the SPU 21 is a system process unit, which analyzes the processing request from the host and notifies the adapter 5 of the processing request. An SPU-IOP information area # 1 is provided in the SPU 21 and is used for communication between the SPU 21 and the IOP 22.

The IOP 22, which is an IO processor, analyzes the processing request from the host and notifies the adapter 5 of the processing request, like the SPU 21. IO
In P22, SPU-IOP information area # 2 is provided and SP
It is used for communication between U21 and IOP22.

In the common memory 4, an adapter (#
1) Adapter control area # 1 for 5 and adapter (#
3) An adapter control area # 2 is provided for 5 and a data transfer area is provided.

Next, the operation of the configuration of FIG. 2 will be described in detail according to the flow of FIG. In FIG. 3, in S1, the host notifies the SPU 21 of the communication request. S2 responds to the notification request of S1 by sending the CH (#
1) 3 writes the request content in the adapter control area # 1 of the common memory 4 as shown in FIG.

0100: activation machine number 0081: processing code indicating command activation. CAW: A channel address word in which the address of CCW (channel command word) storing the processing content is stored.

In S4, CH (# 1) 4 is an adapter (#
1) Notify 5 by interrupt. In S5, the adapter (# 1) 5 notified by the interrupt in S4 fetches the illustrated information from the adapter control area # 1 in the common memory 4 in S3.

In step S6, the contents of the CCW are read from the CCW address of the CAW of the information fetched by the adapter (# 1) 5, and the contents of the communication request are analyzed. Here, S7 is S
As a result of reading and analyzing the contents of the CCW 6 of FIG. 6, it was found that the call was sent in S8, so YES is given and a call request to the adapter (# 3) (Dch) is made from the above information.

In S9, the adapter (# 1) 5 writes the processing request content in the adapter control area # 1 of the common memory 4 as shown in the drawing, as shown in S10. -0100: Requested machine number for communication between adapters-0090: Processing code, which indicates communication between adapters.

1108: Represents the partner machine number of communication between adapters. Address: The start address of the data transfer area. -Data: Content of transmission request.

In S11, the adapter (# 1) 5 notifies the CH (# 1) 3 by an interrupt. In S12, the CH (# 1) 3 notified by the interrupt in S11 determines the partner adapter from the adapter control area # 1. And SP of SPU21
Write in the U-IOP information area.

S13 is the contents written in the SPU-IOP information area. • 0001: partner SPU number • 4141: channel ID • 0090: processing code, which represents communication between adapters.

1108: partner machine number of adapter communication ・ 0091: type code of inter-adapter communication In S14, the SPU 21 writes in the SPU-IOP information area in the IOP 22 of the partner as shown in the figure. .

In S16, CH (# 2) 3 is SPU-IO.
Determine the control adapter from the P information. S17 is S16
Adapter control area # 2 of adapter (# 3) 5 determined in
, As shown in S18.

1108: Activation machine number. 0090: Processing code, which represents communication between adapters. In S19, the CH (# 2) 3 notifies the adapter (# 3) 5 by interruption.

In S20, the adapter (# 3) 5 notified by the interrupt in S19 is the adapter control area # 2 of the common memory 4.
Take in as shown. In S21, the dial number is read from the data address of the information fetched in S20.

In S22, the dial number read in S21 is called. As described above, the SPU 21, which has received the communication request from the host, notifies the adapter (# 1) 5 of the processing content. However, since it is a communication request of the H0 channel, the adapter (# 1) 5 issues the request. It is possible to make a call request to the adapter (# 3) 5 which is the D channel to make a call. The case of this example will be described below.

(1) When a data communication request is made to the H0 channel, a data communication request for the H0 channel is sent from the host through the SPU 21, CH (# 1), and common memory 4 to the adapter (# 1) 3 To notify.

(2) The adapter (# 1) 5 decides to request call control (request via inter-adapter communication) to the D-channel adapter (# 3) 5, and requests it in the following procedure. (2-1) The adapter (# 1) 5 writes the call control data C in the data transfer area in the common memory 4. After that, the data transfer request information A is written in the adapter control area # 1 in the common memory 4, and the interrupt to CH (# 1) 3 is raised. CH
When (# 1) 3 receives the interrupt, it analyzes the contents of A, and when it judges that it is a data transfer request, it sends to SPU 21
S that the data transfer request to the IOP 22 is generated
Write the data transfer request D to the PU-IOP information area # 1,
Request activation. When the SPU 21 receives the activation request,
Set the activation flag of the SPU-IOP register and
Notify P22 that a processing request has occurred.

(2-2) When the activation flag is turned on, the IOP 22 makes the SPU-IOP information areas # 1 to D SP
While copying to the U-IOP information area # 2, the fact that the data transfer has occurred is notified to the CH (# 2) 3. CH (#
2) 3 receives the activation of data transfer, receives D, writes it as B of the adapter control area # 2 of the common memory 4, and activates the adapter (# 3) 5 by interruption. When the adapter (# 3) 5 receives the activation by the interrupt, it analyzes the content B of the adapter control area # 2 in the common memory 4, and according to the address in the B, the processing request content is stored in its own memory C
To transfer as. Then, the adapter (# 3) 5 analyzes the content of this C, determines that it is a call origination here, and originates a call to the designated dial number.

When data communication of the H0 channel occurs as described above, the adapter (# 1) 5 has the common memory 4, CH (# 1) 3, SPU 21, IOP 22, CH.
(# 3) 3, via the common memory 4, the adapter (# 3)
5 is requested to make a call by the D channel through inter-adapter communication, and the adapter (# 3) 5 makes a call.

FIG. 4 shows an example of transfer information according to the present invention. Figure 4
11A shows an example of the data transfer request information (A) from the ADP (adapter). This is S10 of FIG.
Information stored in the adapter control area # 1 of the above, and corresponds to A stored in the adapter control area # 1 in the common memory 3 of FIG.

FIG. 4B shows an example of data transfer start information (B) to the ADP (adapter). This is the information stored in the adapter control area # 2 of S18 of FIG. 3 described above, and corresponds to B stored in the adapter control area # 2 of the common memory 3 of FIG. 2 described above.

FIG. 4C shows an example of the data transfer request data (D). This is S of S13 of FIG. 3 described above.
This is information to be stored in the PU-IOP information area, and the SPU-IOP information areas # 1 and # 2 in the common memory 3 shown in FIG.
Corresponds to D stored in.

[0049]

As described above, according to the present invention,
The input / output control mechanism 2 such as SPU or IOP writes a processing request in the common memory 4 accessible by the subordinate adapter 5, and notifies the corresponding input / output control mechanism 2 when a processing request to another adapter 5 is made. Since a configuration is adopted in which a processing request is written in the common memory 4 accessible by the adapter 5 and the processing is performed by the subordinate adapter 5 that sees the processing request, the subordinate adapters 5 of different input / output control mechanisms 2 are used.
Data transfer can be realized even in the interim. By these, the processing request is transferred between the adapters 5 under the input / output control mechanism 2 such as SPU or IOP to perform the processing. For example, in response to a request for data communication on the H0 channel, the adapter 5 for the H0 channel requests the D channel adapter 5 for call control through inter-adapter communication and connects the line, and then the adapter for the H0 channel 5 Data communication becomes possible.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is an operation explanatory diagram of the present invention.

FIG. 4 is an example of transfer information according to the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: CPU 2: Input / output control mechanism 21: SPU 22: IOP 3: CH 4: Common memory 5: Adapter

Claims (2)

[Claims] 1. In a data communication system for data communication between adapters, an input / output control mechanism (2) for controlling data input / output, and an adapter (5) for performing various processes under the control of the input / output control mechanism (2). ) And a common memory (4) that the adapter (5) can access in common, and an input / output control mechanism (2) writes a processing request to the subordinate adapter (5) in the common memory (4), When the corresponding adapter (5) that has seen the processing request content is extracted and is found to be a processing request to another adapter (5), the corresponding input / output control mechanism (2) is notified of the processing request, and this processing request is issued. The other input / output control mechanism (2) that received the request writes the processing request to the subordinate adapter (5) in the common memory (4), and the corresponding adapter (5) seeing this takes out the processing request content and processes it. Configured to Data communication method according to claim. 2. The data communication is performed between the adapters (5) regardless of whether the adapters (5) are connected on the same bus or on another bus. Described data communication method.