JPH0615874A - Recording device - Google Patents

Abstract

PURPOSE:To enhance resolution capacity in a subscan direction without increasing the number of units of frame memory and thereby improve print quality by providing a means for making time for activating a recording head variable based on recorded print information, and differentiating the density of dot record in a subscan direction from the density of dots of print information. CONSTITUTION:A correction circuit 37 as a means for changing an activation time selects 3X3 dot data from video signals of three lines, and corrects the video signal positioned in the center. Next, three lines of data consisting of continuous video data stored in frame memory are stored in three line buffers selected from among four line buffers 33 to 36. Consequently, while the transfer process of video data to the remaining one line buffer is underway, three appropriate sets of dot data stored in three line buffers are output to a correction circuit 37 to correct a set of data in the center of the 3X3 dot data sets which are output to the correction circuit 37. Thus it is possible to enhance print quality without increasing the number of units of frame memory.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LED printer, LC
The present invention relates to a recording device having an array-shaped head in the main scanning direction such as an S printer.

[0002]

2. Description of the Related Art For example, an LED printer or an LCS printer is known as a recording device for performing a printing process on a recording sheet based on print information output from a computer which is a host device.

FIG. 15A shows a conventional recording apparatus,
For example, the basic configuration of an LED printer connected to a host computer is shown. In the figure, the LED printer 1 includes a printer controller 1a and an engine controller 1
b, the PPC engine 1c, the printer controller 1a has a CPU, a ROM, a RAM, a character generator, a frame memory and the like (not shown) built therein, and print information output from the host computer 2 is sent via, for example, a Centronics interface. input. The printer controller 1a analyzes the print information output from the host computer 2, converts the character code into corresponding pattern data with a character generator, and executes corresponding processing for various commands. By repeating the above-described processing in this way, the pattern data (dot data) for one page of the paper is stored in the frame memory. The engine controller 1b outputs the dot data stored in the frame memory to a print head forming a part of the PPC engine 1c, and prints on a recording sheet by a PPC mechanism (not shown). In addition, the PPC engine 1 is shown in FIG.
Reference character c denotes the entire image forming mechanism of the LED printer 1 including the print head.

FIG. 15B shows the video signal stored in the frame memory in the printer controller 1a as LE.
FIG. 6 is a diagram illustrating a printing process when outputting to a D head 1c ′. 16 shows a time chart at this time.
In both figures, the engine controller 1b outputs the horizontal synchronization signal 1 to the printer controller 1a.

[0005]

[Outer 1]

Then, the printer controller 1a outputs an effective signal outside 2 indicating data for one line in the video signal stored in the frame memory described above to the engine controller 1a.

[0007]

[Outside 2]

It is output to b and thereafter stored in the frame memory in synchronization with clock signal 3 outside.

[0009]

[Outside 3]

The dot data outside 4 is output to the engine controller 1b. That is,

[0011]

[Outside 4]

If the uppermost dot data stored in the memory is, for example, the A line, first the dot data of the A line is sequentially synchronized with the clock signal 5 and the engine controller.

[0013]

[Outside 5]

Output to the tracker 1b. After that, the dot data of the A line supplied to the engine controller 1b is output as exposure data to the latch in the LED head 1c 'in synchronization with the clock signal (DCLK), and once in the LED head 1C' by the latch signal (LAT). After being latched in the latch of

[0015]

[Outside 6]

The photosensitive surface of the above-mentioned photosensitive drum 2 is exposed in accordance with the aiming. After that, printing is performed on the recording paper according to the PPC process as described above. FIG. 17 is a diagram showing a printing process of, for example, 1 dot at this time. That is, with respect to the photoconductor moving in the sub-scanning direction, the LED elements arranged in the main-scanning direction are exposed only for a period of, for example, 1/4 of the writing cycle TW (output cycle of the horizontal synchronizing signal 7).

[0017]

[Outside 7]

Light is applied to form an electrostatic latent image of dots on the pre-charged photosensitive surface. Here, A indicates a dot position at the start of exposure, and B indicates a dot position at the end of exposure, which means that the dots have moved by 1/1 DOP (dot of pitch). Then, one dot is visualized on the recording paper (photosensitive surface) by a developing device to which an appropriate developing bias is applied. The developing bias level is set so that the width of one dot formed in the main scanning direction (1 DOP) is the same in the sub scanning direction. As a result, it is possible to perform printing with a predetermined resolution stored in the frame memory in both the main scanning direction and the sub scanning direction.

[0019]

2. Description of the Related Art The resolution, which is a factor that determines the printing quality of a recording apparatus, is determined by the writing cycle TW and the dot shape of the light emitting element in the sub-scanning direction. Since the conventional recording apparatus performs only one light emission within the writing cycle TW as described above, the size determined by the cycle TW and the moving speed V of the photosensitive member, that is, the dots in the sub-scanning direction are TW × V. It was decided. Therefore, in order to increase the resolution by the conventional storage device, it is necessary to reduce the size of each light emitting dot. Therefore, in order to increase the resolution, the print density should be increased from 240 DPI to 3
It is necessary to increase from 00 DPI and 300 DPI to 400 DPI, and accordingly the capacity of the frame memory also increases. Further, in order to achieve the same printing speed, it is necessary to shorten the above-mentioned writing cycle TW, which requires a high-density writing head. Therefore, it also causes an increase in the cost of the device.

[0020]

SUMMARY OF THE INVENTION In view of the above problems of the prior art, it is an object of the present invention to provide a recording apparatus capable of improving the resolution in the sub-scanning direction and improving the printing quality without increasing the capacity of the frame memory. To aim.

[0021]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention stores a receiving means for receiving print information having a predetermined dot density and the print information received by the receiving means for each line in the main scanning direction. A plurality of storage means, a recording head having a predetermined dot shape and arranged in an array in the main scanning direction to give dot information to the opposing recording means, and the recording based on the print information stored in the storage means A recording apparatus, comprising: an operation time changing means for changing a time for operating a head, and making a dot recording density in a sub-scanning direction different from a dot density of the print information.

[0022]

EXAMPLES An example of the present invention will be described below with reference to the drawings. This embodiment uses LE as a recording device.
2 illustrates an example of a D printer, and FIG. 2 illustrates the entire configuration of the LED printer. In the figure, the LED printer 3 includes a so-called image forming unit 6 including a photosensitive drum 4, an LED head 5, and the like, a paper transport mechanism 8 including a paper feed roller 7 ′, a printer controller, an engine controller, and the like, which will be described later. It is composed of a control circuit housing 9 which houses each circuit.

The image forming unit 6 is a photosensitive drum 4 as a recording means which is rotatable in the direction of arrow a, a charger 10 which is sequentially arranged near the peripheral surface of the photosensitive drum 4, and a recording head. LED head 5, developing device 11, transfer device 1
2 and cleaner 13. Further, the paper transport mechanism 8 includes a paper feed cassette 7 that stores a predetermined amount of paper P, a paper feed roller 7 ′ that carries out the paper P from the paper feed cassette 7,
The standby roll 14 and the like are provided for temporarily holding the sheet P and re-feeding the sheet P at the timing matching the toner image formed on the photosensitive drum 4. Also, the fixing roll 1
Reference numeral 5 denotes a sheet for conveying the sheet P and fixing a toner image, which has been subjected to a transfer process described later by the transfer device 12, onto the sheet P. The sheet conveying direction switching plate 17 is a sheet when the sheet P is in a solid line position in FIG. This is a switching plate for sending P to the so-called face-up paper discharge tray 18 and discharging the paper P to the so-called face-down paper discharge unit 21 via the guide plate 19 and the paper discharge roll 20 when it is at the dotted line position.

On the other hand, the control circuit housing 9 is provided with a printer controller connected to the host computer and an engine controller connected to the printer controller. The configurations of these printer controller, engine controller, and PPC engine unit are the same as those of the conventional FIG. 3 is a diagram for explaining the system configuration. The printer controller 23 as a receiving means has a CPU, ROM, RAM, character generator, frame memory and the like (not shown) built therein, and the engine controller 24 outputs from the printer controller 23. A circuit for performing a correction to be described later is incorporated in the video data to be generated, and the correction data is output to the LED head 5 described above. In addition, the horizontal sync signal shown in the figure 8
Outside 9,

[0025]

[Outside 8]

[0026]

[Outside 9]

Clock signal outside 10, video signal outside 11, latch signal (LAT), strike

[0028]

[Outside 10]

[0029]

[Outside 11]

The lobe signal outside 12 has the same meaning as the signal described with reference to FIG.

[0031]

[Outside 12]

[0032] FIG. 1 shows the engine controller 2 described above.
4 is a diagram illustrating a detailed circuit configuration of FIG. As shown in the drawing, the engine controller 24 is selected by the divider 30, the selector 31, the four line buffers 33 to 36 as the storage means to which the video data distributed by the divider 30 is supplied, and the selector 31. A correction circuit 37 that outputs video data from three of the line buffers 33 to 36, a selector 32 to which the video data corrected by the correction circuit 37 is supplied, line buffers 38 and 39, and the above-described divider. 30, selector 3
1, 32, and a control circuit 40 that outputs a control signal to the correction circuit 37.

The line buffers 33 to 36 are buffers having the same capacity, and are capable of sequentially shifting the serially input video data and holding a video signal for one line. Further, the configurations of the line buffers 38 and 39 are the same as those of the line buffers 33 to 36.

On the other hand, the correction circuit 37 as the operation time changing means uses the video signal for three lines by the method described later to
This is a circuit that selects dot data of × 3 and corrects the video signal located in the middle. For example, (a) in FIG.
When 3 × 3 9 dot data a to i shown in (3) are selected, the data of the dot e located in the middle is corrected. Then, this correction value is supplied to the correction circuit 37.
It is determined by the specific pattern of × 3 dot data. (B) to (e) of FIG. 5 and (f) to (ri) of FIG.
It shows a correction value for a specific pattern detected by referring to a predetermined dot of the dot data a to i. Here, the left of (b) to (b) is the detected pattern,
The center shows the correction value based on the detected pattern, and the left shows the correction result of the detected pattern. For example, (b) in FIG.
In the case of the example, a, b, and f are white data (data “0”).
Means white data), and d, e, i
Is black data (data “1” means black data), the dot e in the middle is 3 in the sub-scanning direction.
The divided data e1 to e3 are white, black, and black (“0,
1, 1 "). At this time, the data of c, g, h surrounded by the broken line is ignored. In the case of (d), a, b, f are black data. , D, e, i are white data, the dot e in the middle is black, white, white (“1, 0,
It is shown that the data is corrected to the data of 0 ″). In this case as well, similarly to (b), c, g and h surrounded by broken lines are ignored.
Similarly in other cases, the data surrounded by the broken line means the data to be ignored.

6 and 7 are concrete circuit diagrams of the correction circuit 37 for performing the above-mentioned correction. FIG. 6 shows three 3-stage D-type flip-flops (hereinafter simply referred to as FF) connected in parallel.
The line buffers 33 to 36 are circuit configured circuits.
The video data output from the following (hereinafter, the video data output to this circuit is referred to as video data 1 to video data 3) is held for 3 dots for each line. That is,
F. F41-1 to F.F. F41-3 and F.I. F42-1
F. F42-3 and F.F. F43-1 to F.F. 3 circuits of F43-3 are arranged in parallel. F41-
3, F. F42-3, F.F. Video data output from three consecutive line buffers in the line buffers 33 to 36 are input to F43-3, and the leading data of each is shifted to the next stage and held by three dots. For example, F.I. F
41-1 to F.F. For example, when 3 dots in the video data of the A line output from the line buffer 33 are held in the F 41-3, F42-1 to F.F. In F42-3, the corresponding 3 dots of the B line video data output from the line buffer 34 are stored. F43-1
F. C output from the line buffer 35 to F43-3
The corresponding 3 dots of the video data of the line are stored.

F. Output A of F41-1, outside 13,
F. Output B of F41-2, outside 14

[0037]

[Outside 13]

[0038]

[Outside 14]

.., F. Output I of F43-3, outside 1
5 corresponds to the gate circuit 44 of FIG.

[0040]

[Outside 15]

Is output to the input. Gate circuit 44
Is an AND gate (hereinafter referred to as an AND gate) 45 to 4
8 and 49 to 52 and an OR gate to which outputs of the AND gates 45 to 48 are supplied (hereinafter referred to as an OR gate)
53, OR supplied with outputs of AND gates 49 to 52
Gate 54 and exclusive OR gate (hereinafter referred to as E
It is composed of OR gates) 55 and 56. still,
The output of the gate circuit 44 is used as the data e1 to e3 (correction signals 1 to 3) corrected by the selector 32,
It is output to the line buffers 38 and 39. The correction value for the specific pattern of 3 × 3 dots shown in FIGS. 4 and 5 is created by the correction circuit 37 shown in FIGS. 6 and 7, and a specific example of the circuit operation will be described later. .

In the LED printer 3 having the above configuration,
The printing operation will be described below. FIG. 8 is a time chart for explaining the operation when the printing process is performed by the printer device of this embodiment. In the figure, first, the horizontal synchronization signal
The outer 16 is as described above.

[0043]

[Outside 16]

When output from the engine controller 24 to the printer controller 23, the printer controller 2
3 is a valid signal from the outside 17 is the engine controller 24
Output to

[0045]

[Outside 17]

At the same time that the engine controller 2
4 to the clock signal outside 18

[0047]

[Outside 18]

From the frame memory in the printer controller 23, 1 line (first A line) of video data
The output 19 is output to the engine controller 24. Divider

[0049]

[Outside 19]

At this time, 30 selects the line buffer 33 according to the control signal output from the control circuit 40. Therefore, the outside video data 20 supplied to the engine controller 24 is first input into the line buffer 33. Bidet to line buffer 33

[0051]

[Outside 20]

The o signal is serially supplied in sequence, all the video data for one line is stored in the line buffer 33, and when a predetermined time elapses (write cycle TW
Later), the next horizontal sync signal signal 21 is output.

[0053]

[Outside 21]

When the next horizontal synchronizing signal is output to the printer controller 23, the printer controller 23 outputs the valid signal outside 22 in the same manner as described above, and the clock signal is output.

[0055]

[Outside 22]

The next one line (B
Line) video data

[0057]

[Outside 23]

Output to the controller 24. At this time, the divider 30 selects the line buffer 34 by the control signal from the control circuit 40, and the video data of the B line is supplied to the line buffer 34. After that, the same processing is sequentially repeated, and the printer controller 23
Each time the line data is output, the divider 30 selects the line buffer to be selected from 34 → 35 → 36 → 33 → 34.
.. and line buffers 33 to 36 selected by switching
The video data of each continuous line is held.

Thereafter, the above-described processing is repeated, for example, as shown in I of FIG. 8, the video data of the line n is held in the line buffer 36, and then the video data of the line n is a new video of the line n + 4. When the data is rewritten, the line buffer 33 holds the video data of the line n + 1, and the line buffer 34 stores the video data of the line n + 1.
+2 video data is held, and the line buffer 35 holds line n + 3 video data.

In this state, the selector 31 sets the video data of the line n + 1 held in the line buffer 33 as the video data 1 in the F.D. of the correction circuit 37. The video data of the line n + 2 output to the F41-3 and held in the line buffer 34 is set as the video data 2 in the F. The line n + 3 output to F42-3 and held in the line buffer 35
The video data of F. F43-3
The line buffers 33 to 35 are selected to be output to. The area II shown in FIG. 8 shows the line data held in the respective line buffers 33 to 36 for each TW. Then, in the above state II, the area III is selected by the selector 31.
3 indicates that three line buffers for which the rewriting process has not been performed are selected, and the video data held in the three line buffers are output to the correction circuit 37 as the video data 1 to 3 described above.

The correction circuit 37, as described above, is shown in FIGS.
3 × 3 held in the correction circuit 37 according to the correction value shown in
The data e in the middle of the dot is corrected. FIG. 9 is a diagram for explaining the correction by the correction circuit 37 using a specific printing example. This figure shows a correction process of, for example, the character "chi" when a font composed of 24 × 24 characters is used. Incidentally, (a) of the figure shows the dot pattern in the state before being stored in the frame memory, and (b) of the figure shows the dot pattern after the correction. Since the dot data in the frame memory stores data for one page of the paper, the correction process is started for this character “H” only when the dot data of 3 × 3 dots indicated by the diagonal lines is corrected by the correction circuit 37. It is time to be held in. At this time, F. F41-1
~ F. The data of “0, 0, 0” is held in the F41-3, and the F. F42-1 to F.F. F42-3, and F.I. F43
-1 to F. The data “0, 0, 0” is also held in the F43-3. Therefore, at this time, the F. F41-1 to F.F. F4
The outputs A to I from the terminal Q of 3-3 are all "0",
The outputs A to I from the terminal Q'are all "1". Therefore, in this state, the input circuit 24 of the gate circuit 44 of FIG.

[0062]

[Outside 24]

Data “0” is input to the outer 25 and data “0” is input to the outer 26 to the outer 27.

[0064]

[Outside 25]

[0065]

[Outside 26]

[0066]

[Outside 27]

Since 1 "is input, AND gates 45 to 5
All outputs of 2 become "0", and NOR gates 53, 5
The output of 4 and the outputs of the EXOR gates 55 and 56 are also "0". That is, at this time, all of the correction signals 1 to 3 indicating the correction data output from the gate circuit 44 (correction circuit 37) are “0”, and the result 3 ×
This is the same data as the middle dot (dot e) of the pattern data of No. 3. That is, in FIG. 4 and FIG.
Since it is a dot pattern other than the specific pattern shown as (ri), no correction is performed. Therefore, in this case, the correction signals 1 to 3 are all set to "0" and the corresponding selector 3
2. Output to the line buffers 38 and 39.

Next, when the data of 3 × 3 dots indicated by the diagonal line which is shifted to the right by one dot from the above is supplied to the correction circuit 37, the same operation as described above is performed, and the selector 32 and the line buffers 38 and 39 are respectively provided. Data “0” is output. After that, similarly, 3 × 3 data, which is shifted by 1 dot to the right, is output to the correction circuit 37, and the correction process is sequentially performed, and when all the processes in the main scanning direction are completed, 1 dot is shifted in the sub scanning direction.

After that, for example, when 3 × 3 dot data indicated by diagonal lines is supplied to the correction circuit 37, the F. F
41-1 to F.F. The data “0, 0, 0” is held in the F41-3, and the F. F42-1 to F.F. The data “0, 0, 1” is held in the F42-3, and the F. F43-1 to F.F. F4
The data “1, 1, 1” is held in 3-3. Therefore, in this state, it is the state of the specific pattern (i) shown in FIG. (At this time, the data I of F.F43-3 is the data "1", but in the pattern (i), the data is within the broken line and is ignored.) At this time, the inputs C, D, and E of the gate circuit 44 , And outer 28, outer 29
, Data “0” is input to outside 30, and input

[0070]

[Outside 28]

[0071]

[Outside 29]

[0072]

[Outside 30]

Data “1” is input to the outer 31, outer 32, outer 33, and F, G, and H.

[0074]

[Outside 31]

[0075]

[Outside 32]

[0076]

[Outside 33]

It is. Therefore, the outputs of the AND gates 45 to 51 are "0", and only the output of the AND gate 52 is "1".
Becomes Therefore, at this time, the output of the OR gate 53 is "0" and the data "0" is supplied to the input E, so that the correction signal 1 which is the output of the EXOR gate 55 becomes "0". The correction signal 2 also becomes "0" because the data "0" is supplied to the input E as described above. On the other hand, since the AND gate 52 outputs the data "1", the output of the OR gate 54 is the data "1", and therefore the EXOR gate 56.
The correction signal 3 which is the output of the above outputs the data "1". From the above, the output of the correction signals 1 to 3 (e1 to e3) is “00,
1 ”, the correction signal 1 is directly output to the LED head 5 through the selector 32 and used as exposure data for the photosensitive drum 4. The correction signal 2 is held in the line buffer 38 and the correction signal 3 is stored. Is line buffer 3
Held at 9.

Next, when the data of 3 × 3 dots is supplied to the correction circuit 37 as shown by the slanted line by shifting further to the right by one dot from the above-mentioned slanted line state, the F. F41-
1-F. The data “0, 0, 0” is held in the F41-3, and the F. F42-1 to F.F. Data “0,
1, 1 "are held, and F.F43-1 to F.F43-3
The data "1, 1, 1" is held in the. (At this time, both H of F.F43-2 and I of F.F43-3 are data "1", but h and i are the data within the broken line as in the case of (i) and are ignored.) The state is the state of the specific pattern (C) shown in FIG. At this time, the inputs B, C and D of the gate circuit 44 and the outside 34

[0079]

[Outside 34]

Data “0” is stored in the outer layers 35 and 36.
Input, input outside 37, outside 38

[0081]

[Outside 35]

[0082]

[Outside 36]

[0083]

[Outside 37]

[0084]

[Outside 38]

Data “1” is input to the outside 39 and E, F, and G. For this reason, AND

[0086]

[Outside 39]

The outputs of the gates 45 and 47 to 52 are "0", and only the output of the AND gate 46 is "1". Therefore, in this case, the output of the OR gate 53 is "1" and the data "1" is supplied to the input E, so the correction signal 1 output from the EXOR gate 55 is "0", and the correction signal 2 is As described above, since the data "1" is supplied to the input E, it becomes "1". On the other hand, since all the AND gates 49 to 52 output data "0", the output of the OR gate 54 is also "0", and therefore the correction signal 3 which is the output of the EXOR gate 56 outputs data "1". From the above, the output of the correction signals 1 to 3 (e1 to e3) becomes "0, 1, 1", and the correction signal 1 is directly output to the LED head 5 via the selector 2 as exposure data for the photoconductor drum 4. used. Further, the correction signal 2 is sent to the line buffer 38.
The correction signal 3 is held in the line buffer 39.

Based on the correction signals 1 to 3 output from the correction circuit 37 in this way, for example, the correction state is shown as ',' shown in FIG. 9B. Thereafter, the correction processing is performed in the same manner as described above, and the correction signal 1 output to the selector 32 is directly used as the exposure data by the LED head 5 as described above, and the line buffer 38,
After one line of print data is output to each 39, the print data held in the order of the line buffers 38 → 39 is output to the LED head 5 by the selection of the selector 32, and the exposure process for the photosensitive drum 4 is performed. Here, the print timing of the correction data 2 is the first TW / 3 obtained by dividing TW by 1/3.
Correction data 2 stored in the line buffer 38
Is performed at the next TW / 3, and the correction data 3 in the line buffer 39 is printed at the last TW / 3. In this way, the printing state when the printing process of the entire character “H” shown in FIG. 9 is completed is improved to the state of FIG.

FIG. 10 is a diagram showing the relationship between the exposure amount and the dot size when the printing process is performed by the LED head 5 based on the correction data 1 to 3 described above. In the present embodiment, unlike the case of the conventional example, the conventional 1-dot forming process is divided into 1/3 corresponding to the sub-scanning direction, and therefore the exposure from the LED head 5 is also divided into 1/3. To do. That is, as shown in FIG. 11, the conventional write cycle TW is divided into ⅓, and the first ¼ period of each period (that is, 1/12 of the write cycle TW) is converted into correction signals 1 to 3. Perform the exposure process according to the following. Note that this 1/12 period tON is LE
It can be varied from 0 <tON ≦ 4/12 depending on the brightness of the D head. The example of FIG. 10 is an example in the case where all the correction data 1 to 3 are “1”. In this case, for the photosensitive drum 4 moving from the LED head 5 in the sub-scanning direction, FIG.
Exposure is performed three times at a time of TW / 12 at the timing shown in. Each time the photosensitive drum 4 is exposed, precharged charges are removed, electrostatic latent images with different charge levels are formed, and a developing device applies a predetermined developing bias to visualize one dot. To do. At this time, dots having the same width as the main scanning direction can be formed by appropriately setting the developing bias level.

On the other hand, FIGS. 12B and 12C show an example in which one dot is not printed according to the correction data 1 to 3, and FIG. 12B shows an example in which 2/3 dots are printed. Yes,
(C) of the figure is an example in the case of printing 1/3 dot. It should be noted that (a) in the same figure is an example in which the process of printing all one dot continues twice. Here, as can be seen from the correction values in FIGS. 4 and 5 described above, the feature of this embodiment is 1 /
This means that there is always black printing on the side that corrects black printing (“1”) of 3 dots or 2/3 dots (on the side that performs exposure). That is, 1/3 dot or 2 /
It is impossible to correct 3-dot black printing ("1"). Therefore, for example, when correcting black printing (“1”) of 2/3 dots, the LED head 5 (T
W / 12) × 3 times of exposure processing is performed, and then two more times of exposure processing become continuous processing. Therefore,
When the developing process is performed at the above-described developing bias level and the transfer process is performed on the sheet P, dot printing with a size of 5/3 dots can be performed as shown in FIG. Further, when correcting 1/3 dot black printing (“1”), as shown in (c) of the figure, following the printing processing (TW / 12) of the preceding line × 3 times, and then further The exposure process is performed once, and then, as shown in FIG.
Printing with a dot size of / 3 will be performed.

As described above, according to the present embodiment, the data of three consecutive lines of the video data stored in the frame memory is stored in the selected three of the four line buffers 33 to 36.
Stored in one line buffer and rewriting the video data to the remaining one line buffer, 3
The corresponding three dot data stored in each line buffer are output to the correction circuit 37, and the middle data of the 3 × 3 dot data output to the correction circuit 37 is corrected. As a result, the print quality of the recording device is improved without increasing the capacity of the frame memory.

Although the correction circuit 37 shown in FIGS. 6 and 7 is used in this embodiment, the present invention is not limited to this circuit, and the circuit configurations shown in FIGS. 13 and 14, for example, may be used. That is, the video data 1 to 3 output from the line buffers 33 to 36 are the F.D. F57
-3, F.I. F58-3, F.I. After outputting each to F59-3, the F.F. F57-2, F.I. After shifting to F57-1, etc., outputs A to I based on the video data 1 to 3 are output to the ROM 60 shown in FIG. Depending on the data of A to I input to the ROM 60, the above-mentioned FIG. 4 and FIG.
As shown in (b) to (b) of FIG. 3, correction data for outputting preset correction data 1 to 3 when a predetermined specific pattern is stored is stored. The data e in the middle of the 3 × 3 dot data output to the circuit can be corrected, and the print quality of the recording device can be improved without increasing the capacity of the frame memory.

Further, in this embodiment, black printing is performed with data "1".
And white printing is data “0”, and when data is “1” L
The printing process by the so-called reversal development method, which is performed by exposing with the ED head 5, has been described.
The printing process may be performed by a so-called positive development method in which exposure is performed at the time.

In this embodiment, the line buffers 33-
The configuration is such that four line buffers are used as 36, and one dot is divided into three in the sub-scanning direction for print processing.
The number of divisions may be increased by using more line buffers. With this configuration, the print quality can be further improved.

Further, although the LED printer has been described in the present embodiment, the printing process is performed at a time in the main scanning direction.
The same can be applied to a recording device such as a CS printer or a multi-stylus printer.

[0096]

As described in detail above, according to the present invention, the resolution of the print head in the sub-scanning direction can be substantially improved without increasing the storage capacity of the frame memory, and the cost of the apparatus is increased. It is possible to improve the print quality of the storage device without doing so.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a correction circuit of a recording apparatus according to an embodiment.

FIG. 2 is an overall configuration diagram of a recording apparatus according to an embodiment.

FIG. 3 is a diagram illustrating a state in which a host computer is connected to the recording apparatus according to the embodiment.

FIG. 4 is a diagram showing an example of a correction value for a specific pattern.

FIG. 5 is a diagram showing an example of correction values for a specific pattern.

FIG. 6 is a circuit diagram of a correction circuit.

FIG. 7 is a circuit diagram of a correction circuit.

FIG. 8 is a time chart illustrating the operation of the recording apparatus according to the embodiment.

FIG. 9 is a diagram showing an example in which a specific character is corrected.

FIG. 10 is a diagram illustrating an example of 1-dot printing processing by the recording apparatus according to the embodiment.

FIG. 11 is a diagram illustrating print timing of the recording apparatus according to the embodiment.

FIG. 12 is a diagram showing an example when a printing process of 2 dots, a printing process of 5/3 dots, and a printing process of 4/3 dots are performed by the recording apparatus of the embodiment.

FIG. 13 is a circuit diagram showing a modification of the correction circuit.

FIG. 14 is a circuit diagram showing a modification of the correction circuit.

FIG. 15 is a diagram illustrating a configuration of a recording device.

FIG. 16 is a time chart explaining the operation of the conventional recording apparatus.

FIG. 17 is a diagram illustrating a process of printing one dot by a conventional recording device.

[Explanation of symbols]

3 LED Printer 4 Photosensitive Drum 5 LED Head 6 Image Forming Section 8 Paper Conveying Mechanism 23 Printer Controller 24 Engine Controller 30 Divider 31, 32 Selector 33-36, 38, 39 Line Buffer 40 Control Circuit 41-1 to 43-3, 57-1 to F.I. F59-3 F.
F 45-52 AND gate 53, 54 OR gate 55, 56 EXOR gate 60 ROM

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location B41J 2/515 2/485 5/30 Z 8907-2C 8804-2C B41J 3/12 G (72) Inventor Minoru Kurata, 2-229 Sakuragaoka, Higashiyamato-shi, Tokyo Casio Electronics Co., Ltd.

Claims (1)

[Claims] 1. A receiving means for receiving print information having a predetermined dot density, a plurality of storing means for storing the print information received by the receiving means for each line in the main scanning direction, and a predetermined dot shape. A recording head which is arranged in an array in the main scanning direction and which gives dot information to the recording means facing each other; and an operation which varies the time for operating the recording head based on the print information stored in the storage means. A recording apparatus, comprising: a time varying unit, wherein the dot recording density in the sub-scanning direction is different from the dot density of the print information.