JP3853970B2 - Image data processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides an image for performing various image processing on image data read by an electrophotographic image forming apparatus using digital image data such as an optical printer such as a laser printer, a digital copying machine, or a plain paper fax machine. The present invention relates to a data processing apparatus, and in particular, corrects jaggies of contour lines for image data expanded in a bitmap shape to improve image quality, and at the same time whites in the black dot area of the image data expanded in a bitmap shape. By making it possible to share the recognition pattern of the line segment shape at the boundary with the dot area, the time required to create correction data used for jaggy correction will be reduced, and the data setting time during actual use will be minimized. The present invention relates to an image data processing apparatus that can
[0002]
[Prior art]
In general, in an electrophotographic image forming apparatus using digital image data such as an optical printer such as a laser printer, a digital copying machine, and a plain paper fax machine, an image for performing various image processing on the read image data A data processing device is provided.
In Japanese Patent Application No. 4-301395, in order to improve image quality by correcting contour line jaggies for image data developed in the form of a bitmap as one of the above image processes, it is stored in a memory in advance. The data that needs to be reduced is reduced as much as possible, and the determination of the dot that needs correction in the image data and the determination of the correction data for the dot that needs correction are extremely short by simple determination and calculation by a microprocessor or the like. What is done in time is achieved by the method described below.
That is, the image data processing method for achieving the above contents recognizes the line segment shape of the black dot area and the white dot area of the image data developed in the form of a bitmap, and assigns it to each required dot. The feature of the line segment shape recognized is replaced with multi-bit code information, and at least a part of the code information is used to determine whether the dot needs to be corrected. In this case, correction according to the code information is performed.
[0003]
On the other hand, an image data processing apparatus according to this image data processing method has a window for extracting data of each dot in a predetermined area centered on a target dot of image data expanded in a bitmap shape, and extracts through the window. A plurality of bits representing the feature of the line segment shape recognized for the target dot, by recognizing the line segment shape of the boundary between the black dot region and the white dot region of the image data. A pattern recognition unit that generates code information, a determination unit that determines whether or not a dot needs to be corrected using at least part of the code information, and a dot that is determined to be corrected by the determination unit Thus, the correction data stored in advance with the code information generated by the pattern recognition means as an address is read and output. It was equipped with a data memory.
Here, the pattern recognition means includes code information indicating whether the dot to be recognized is a black dot or a white dot as code information representing the feature of the line segment shape recognized for each required dot. Code information including the code information indicating the inclination direction of the line segment, the code information indicating the degree of inclination, and the code indicating the position from the dot at the end of the line segment continuous in the horizontal or vertical direction of the target dot Was generated.
[0004]
Then, according to the image data processing method and apparatus described above, the line segment shape of the boundary portion (contour line of characters, etc.) between the black dot region and the white dot region of the image data expanded in a bitmap shape is recognized. Then, replace each required dot with multi-bit code information, determine whether or not the dot needs to be corrected using at least a part of the code information, and for the dot that needs correction Since correction is performed according to the above code information, it is not necessary to create and store in advance all the feature patterns that need correction as templates, and correction data for the dots that need correction and the dots that need correction It has been possible to easily determine this in a short time using the code information.
However, in the prior art, it is not necessary to create and store as a template all the feature patterns that need to be corrected in advance, and to determine the correction data for the dots that need to be corrected and the dots that need to be corrected. Although it has become possible to easily perform this in a short time using information, the multi-bit code information representing the feature of the line segment shape recognized for each dot is, for example, a 12-bit configuration. Although it is possible to express a maximum of 4096 different patterns (the number of patterns that can be represented by 12 bits), the number of patterns actually required for correction may be less than the above numerical value depending on the combination of each bit.
In addition, with respect to a pattern in which the pattern of image data developed in a bitmap shape is axisymmetric with respect to a horizontal line or a vertical line, common data may be used for correction data.
[0005]
[Problems to be solved by the invention]
However, when image quality is improved by correcting contour line jaggies for image data developed in the form of a bitmap according to the prior art, all feature patterns that require correction are created and stored in advance as templates. This makes it possible to determine the dot that needs to be corrected and determine the correction data for the dot that needs to be corrected in a short time using the above-mentioned code information. Storage of correction data in the memory for the dots determined to require correction as the boundary between the black dot area and the white dot area is a redundant number with respect to the number of memories, and the actual usage efficiency is Unfortunately, there is a drawback that the circuit configuration becomes large.
In addition, depending on the image that is subject to the jaggy correction of the contour line, it is not necessary to correct with the accurate jaggy correction data based on the more accurate pattern recognition result, and the number of correction data stored in the memory is minimized. In some cases, we could be satisfied with the image with jaggy correction based on pattern recognition that uses a common recognition pattern.
[0006]
The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to improve image quality by correcting contour line jaggies for image data developed in a bitmap shape. At the same time, when creating correction data used for jaggy correction by enabling the sharing of the line segment shape recognition pattern between the black dot area and the white dot area of the image data developed in bitmap form It is an object of the present invention to provide an image data processing apparatus that can reduce the time required for data setting and minimize the data setting time during actual use.
Another object of the present invention is to recognize the line segment shape of the boundary between the black dot region and the white dot region of the image data developed in a bitmap shape, and recognize the line segment recognized for the target dot. Providing an image data processing device that can reduce the cost of the device by reducing the total capacity of the memory block that reads out and outputs correction data stored in advance using multiple bits of code information representing the shape features as addresses It is to be.
Another object of the present invention is to reduce the time required for storing correction data required for image correction in a memory block, and to improve the use efficiency of software or hardware during actual use. Is to provide.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is a window for extracting data of each dot in a predetermined area centered on a target dot of image data developed in a bitmap shape, and the window A plurality of bits representing the feature of the line shape recognized for the target dot by recognizing the line shape of the boundary between the black dot area and the white dot area of the image data from the image data extracted through Pattern recognition means for generating the code information, determination means for determining whether or not the dot needs to be corrected using at least a part of the code information, and dots determined to be corrected by the determination means On the other hand, a memory block for reading out and outputting correction data stored in advance using the code information generated by the pattern recognition means as an address In the image data processing apparatus having the above, among the plurality of bits representing the feature of the line segment shape recognized for each dot, the bit indicating whether the slope of the line segment is upper right or lower right is valid Inclined bit switching means for setting whether to invalidate or invalidate is provided.
According to the image data processing device of the first aspect, the recognition pattern of the line segment shape of the boundary portion between the black dot region and the white dot region of the image data developed in a bitmap shape by the image data processing device. By enabling common use, it is possible to shorten the time for creating correction data used for jaggy correction using the image data processing apparatus and to minimize the data setting time during actual use.
[0008]
According to a second aspect of the present invention, the code information of a plurality of bits representing the feature of the line segment shape recognized for each dot of the image data expanded in the form of a bitmap output from the pattern recognition means, For the dots determined to be unnecessary for correction by the determination means, code information conversion means for converting into black and white one-bit code information each indicating only whether the target dot is a black dot or a white dot And a plurality of bits of code information generated by the code information conversion means together with a plurality of bits of code information for the dots determined to be corrected by the determination means. It functions as an address of the memory block to be performed.
According to the image data processing apparatus of claim 2, the line segment shape of the boundary portion between the black dot region and the white dot region of the image data expanded in a bitmap shape is recognized, and the target dot The cost of the device can be reduced by reducing the total capacity of the memory block that reads out and outputs the correction data stored in advance using the multi-bit code information representing the feature of the line segment shape recognized as an address. can do.
According to a third aspect of the present invention, there is provided code information aggregating means for sending an array of code information sent to the memory block to the memory block as a continuous address.
According to the image data processing apparatus of the third aspect, the time required for storing correction data necessary for image correction in the memory block is shortened, and the use efficiency of software or hardware during actual use is reduced. Improvements can be made.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 2 is a block diagram showing the configuration of a laser printer which is an image forming apparatus embodying the present invention.
In FIG. 2, the laser printer 2 includes a controller 3, an engine driver 4, a printer engine 5, and an internal interface 6.
The laser printer 2 receives the print data transferred from the host computer 1, develops it into bit map data for each page by the controller 3, and converts it into video data that is dot information for driving the laser. The image is sent to the engine driver 4 through the internal interface 6 and the printer engine 5 is sequence-controlled to form a visible image on the paper.
The internal interface 6 is provided with a dot correction unit 7 which is an image data processing apparatus according to the present invention, and the video data sent from the controller 3 is subjected to dot correction by the image data processing method of the present invention to improve the image quality. It is measuring.
The controller 3 stores a main microcomputer 31 (hereinafter referred to as “MPU”), a ROM 32 storing programs / constant data and character fonts required by the MPU 31, and general data, dot patterns, and the like. The RAM 33 is composed of 1/034 for controlling data input / output and an operation panel 35 connected to the MPU 31 via the 1/34, and is mutually connected by a data bus, an address bus, a control bus, and the like. .
An internal interface 6 including the host computer 1 and the dot correction unit 7 is also connected to the MPU 31 via 1/034.
[0010]
The engine driver 4 includes a sub-microcomputer (hereinafter referred to as “CPU”) 41, a ROM 42 storing programs and constant data required by the CPU 41, a RAM 43 storing temporary data, and data input. 1/044 for controlling the output, and are connected to each other by a data bus, an address bus, a control bus, or the like.
The 1/044 is connected to the internal interface 6 and inputs video data from the controller 3 and states of various switches on the operation panel 35, and status signals such as an image clock (WCLK) and a paper end to the controller 3. Output.
The 1/044 is also connected to the writing unit 26 and other sequence device group 27 constituting the printer engine 5 and various sensors 28 including a synchronization sensor described later.
The controller 3 receives a command such as a print command and print data such as character data / image data from the host computer 1 and edits them, and if it is a character code, it is necessary to write an image using a character font stored in the ROM 32. The data is converted into a dot pattern, and the bitmap data of those characters and images (hereinafter collectively referred to as “images”) is developed in a video RAM area in the RAM 33 in units of pages.
[0011]
When the image clock WCLK is input together with the ready signal from the engine driver 4, the controller 3 converts the bitmap data (dot pattern) developed in the video RAM area in the RAM 33 as video data synchronized with the image clock WCLK. And output to the engine driver 4 via the internal interface 6. The dot correction unit 7 in the internal interface 6 performs dot correction according to the present invention on the video data as will be described later.
On the operation panel 35, there are a switch and a display (not shown), which controls data according to an instruction from the operator, transmits the information to the engine driver 4, and displays the status of the printer on the display.
The engine driver 4 controls the writing unit 26 of the printer engine 5 and a sequence device group 27 such as a charge charger / development unit, which will be described later, based on the video data input after dot correction via the internal I / F 6 from the controller 3. Video data necessary for control and image writing is input via the internal I / F 6 and output to the writing unit 26, and signals indicating the state of each part of the engine are input from the synchronization sensor and other sensors 28. Or a status signal of necessary information or an error situation (for example, a paper end) is output to the controller 3 via the internal I / F 6.
[0012]
FIG. 3 is a schematic configuration diagram showing the mechanism of the printer engine 5 in the laser printer 2.
According to the laser printer 2, the paper 11 is fed from one of the upper and lower two-stage paper feeding cassettes 10a and 10b, for example, from the paper stack 11a of the upper paper feeding cassette 10a by the paper feeding roller 12, and the paper 11 is After being timed by the registration roller pair 13, it is conveyed to the transfer position of the photosensitive drum 15.
The surface of the photosensitive drum 15 that is rotationally driven in the direction of the arrow by the main motor 14 is charged by the charging charger 16 and scanned with a PWM-modulated spot from the writing unit 26 to form an electrostatic latent image on the surface. Is done.
This latent image is visualized by attaching toner by the developing unit 17, and the toner image is transferred onto the paper 11 conveyed by the registration roller pair 13 by the action of the transfer charger 18 and transferred to the paper. Is separated from the photosensitive drum 15, sent to the fixing unit 20 by the conveyance belt 19, pressed against the fixing roller 20 b by the pressure roller 20 a, and fixed by the pressure and the temperature of the fixing roller 20 b.
The sheet exiting the fixing unit 20 is discharged to a discharge tray 22 provided on the side surface by a discharge roller 21.
On the other hand, the toner remaining on the photosensitive drum 15 is removed and collected by the cleaning unit 23.
A plurality of printed circuit boards 24 constituting the controller 3, the engine driver 4, and the internal I / F 6 are mounted above the laser printer 2.
[0013]
FIG. 4 is a perspective view of a principal part showing a configuration example of the writing unit 26 shown in FIG.
The writing unit 26 includes an LD (laser diode) unit 50, a first cylinder lens 51, a first mirror 52, an imaging lens 53, a disk-type motor 54, and a polygon mirror rotated thereby in the direction of arrow A. 55, a second deflector 57, a second cylinder lens 58 and a third mirror 60, a condensing lens 61 composed of a cylinder lens, and a synchronization sensor 62 composed of a light receiving element.
The LD unit 50 incorporates therein a laser diode (hereinafter referred to as “LD”) and a collimator lens that converts a divergent beam emitted from the LD into a parallel light beam.
The first cylinder lens 51 functions to shape the parallel light beam emitted from the LD unit 50 on the photosensitive drum 15 in the sub-scanning direction, and the imaging lens 53 reflects the parallel light reflected by the first mirror 52. The beam is converted into a convergent beam and is incident on the mirror surface 55 a of the polygon mirror 55.
The polygon mirror 55 is an R polygon mirror formed by curving each mirror surface 55a, and is a post-object type that does not use an fθ lens that is conventionally disposed between the second mirror 57 (after the light beam is converged light). This is a rotary deflector 56 of a type in which a deflector is disposed.
The second mirror 57 reflects the beam (scanning beam) reflected and deflected by the rotary deflector 56 toward the photosensitive drum 15. The scanning beam reflected by the second mirror 57 passes through the second cylinder lens 58 and forms an image as a sharp spot on the main scanning line 15 a on the photosensitive drum 15.
The third mirror 60 is disposed outside the scanning area on the photosensitive drum 15 by the light beam reflected by the rotary deflector 56 and reflects the incident light beam toward the synchronization sensor 62 side. The light beam reflected by the third mirror 60 and collected by the condenser lens 61 is converted into a synchronization signal for keeping the scanning start position constant by a light receiving element such as a photodiode constituting the synchronization sensor 62. .
[0014]
FIG. 1 is a block diagram showing a schematic configuration of the dot correction unit 7 (first embodiment) in FIG. 2, and FIG. 6 is a diagram showing a specific configuration example of the main parts (FIFO memory 72 and window 73). is there.
As shown in FIG. 1, the dot correction unit 7 has a basic configuration of a parallel / serial converter (hereinafter referred to as “P / S converter”) 71, a FIFO memory 72, a window 73, a pattern recognition unit 74, a memory block 75, and video data. The output unit 76 and a timing control unit 77 that controls these synchronously are configured.
When the video data transferred from the controller 3 shown in FIG. 2 is parallel (8 bits) data, the P / S converter 71 is provided to convert the video data into serial (1 bit) data and send it to the FIFO memory 72. It is basically not involved in dot correction. When the video data transferred from the controller 3 is serial data, the P / S converter 71 is not necessary.
The FIFO memory 72 is a first-in first-out memory, and stores lines of video data for a plurality of lines (for this example, 6 lines) sent from the controller 3 as shown in FIG. Buffers 72a to 72f are serially connected.
[0015]
As shown in FIG. 6, the window 73 includes one line of serial video data sent from the controller 3 via the P / S converter 71 and six lines output from the line buffers 72 a to 72 f of the FIFO memory 72. 11-bit shift registers 73a to 73g are serially connected to a total of 7 lines of data and constitute a pattern detection window (sample window: an example of its shape is shown in FIG. 7). is doing.
The middle bit of the shift register 73d at the center (indicated by a cross in FIG. 6) is the storage position of the target dot. Of the shift registers 73a to 73g constituting the window 73, 7 bits are sufficient for the shift registers 73a and 73g, and 8 bits are sufficient for the shift registers 73b and 73f, and the portion indicated by the broken line in FIG.
As the video data is sequentially shifted one bit at a time in the line buffers 72a to 72f constituting the FIFO memory 72 and the shift registers 73a to 73g constituting the window 73, the noticed dots are sequentially changed. The video data of the window 73 as the center can be extracted continuously.
Based on the dot information extracted from the window 73, the pattern recognition unit 74 has a target dot (notice dot) and its surrounding information, in particular, the line segment shape of the boundary between the black dot and the white dot of the image data. The feature is recognized, and the recognition result is output as code information in a predetermined format. This code information becomes the address code of the memory block 75.
[0016]
FIG. 5 is a block diagram showing the internal configuration of the pattern recognition unit 74 and the relationship with the window 73.
The window 73 as a sample window is divided into a central 3 × 3 bit core area (Core) 73C, an upper area (Lower) 73D, a left area (left) 73L, and a right area (Right) 73R. (Refer to FIG. 7 for details.) However, since the details are the same as those described in Japanese Patent Application Nos. 3-314928 and 4-301395, they are omitted here.
Furthermore, the pattern recognition unit 74 includes a core region recognition unit 741, a peripheral region recognition unit 742, multiplexers 743 and 744, a gradient calculation unit 745, a position calculation unit 746, a determination unit 747, and a gate 748. The peripheral region recognition unit 742 is further configured by an upper region recognition unit 742U, a right region recognition unit 742R, a lower region recognition unit 742D, and a left region recognition unit 742L. The actions of these parts are also the same as those described in Japanese Patent Application No. 3-314828 and Japanese Patent Application No. 4-301395, and are therefore omitted here.
A specific configuration example and operation of the memory block 75 will be described with reference to FIG.
[0017]
FIG. 8 is the same as the contents described in Japanese Patent Application Nos. 3-314928 and 4-301395, and the memory block 75 is configured as a pattern memory and is output from the pattern recognition unit 74. Using the information (12 bits) as an address, correction data (10 bits) stored in advance is read out, and video data for laser driving is output, which becomes a corrected dot pattern.
The correction data output from the embodiment of the memory block 75 shown above is an integral multiple (10 times the value obtained by dividing the normal width, that is, the laser emission time) for each dot of the video data sent from the controller 3 into a plurality of dots. The maximum value in the case of division is 10 times) and is output in parallel.
The video data output unit 76 serializes the parallel information output from the memory block 75 and sends it to the printer engine 4 to turn on / off the laser diode of the LD unit 50 that is a light source provided in the writing unit 26. A signal source.
However, the ON / OFF control of the laser diode of the LD unit 50 in the above description assumes control based on binary data. However, if control based on multi-value data is assumed, the video data output unit 76 described above is assumed. It is no longer necessary to serialize the parallel information output from the memory block 75 and send it to the printer engine 4, and the parallel information from the memory block 75 is used as it is in the LD unit 40 (in this case, the multi-value control LD unit is shown). The writing unit 26 performs writing by corresponding to multi-value image data relating to ON / OFF of the laser diode and power control.
[0018]
The present invention relates to an image data processing apparatus, and the configuration and operation of other embodiments (second to fourth embodiments) will be described below.
FIG. 9 is a block diagram showing a schematic configuration of the second embodiment of the dot correction unit 7, except that a tilt bit switching unit 78 shown in FIG. 1 is provided.
The inclined bit switching means 78 determines whether the inclination of the line segment is upper right or lower right among the multi-bit code information representing the characteristics of the line segment shape recognized for the target dot by the pattern recognition unit 74. The operation illustrated in the timing chart of FIG. 10B is performed using the circuit illustrated in FIG.
[0019]
The operation of the inclined bit switching means 78 in FIG. 10 will be described below.
In the circuit of FIG. 10A, if the inclined bit control signal is high level, the SLOP signal input from the pattern recognition unit 74 is output as it is to the memory block 75, but the inclined bit control signal is low. If it is level, the SLOP signal input from the pattern recognition unit 74 is fixed to the low level output and output to the memory block 75.
By using this configuration, the image correction state shown in FIG. 11 can be switched.
First, FIG. 11A shows an image correction state when the tilt bit control signal is at a high level with respect to the circuit of FIG. 10A. FIG. 11A shows a bitmap of an image B that is symmetric about a vertical line with respect to the image A. Here, the dots indicated by ● in the bit map of the image before correction are dots that are line-symmetric with respect to the vertical line, and are output from the pattern recognition means 74 in this image data processing apparatus. In the multi-bit code information, all the code information signals other than the SLOP signal, which is a bit indicating whether the slope of the line segment is in the upper right direction or the lower right direction, are the same. For example, it is assumed that the SLOP signal = 0 when the slope of the line is on the upper right, and SLOP signal = 1 when the line is on the lower right, and the pattern recognition means 74 other than the SLOP signal for the dots indicated by ● in FIG. Assuming that the outputted multi-bit code information is xxx, the multi-bit code information inputted as the address of the memory block 75 is “1xxx” at the dot position of the image A, and Since the dot position of ● is “0xxx”, the corrected image A and image B shown in the figure can be converted into different image data images.
This is like a corrected image shown in the figure, and is a method that enables precise jaggy correction of image data.
[0020]
Next, FIG. 11 (b) shows an image correction state when the tilt bit control signal is at a low level with respect to the circuit of FIG. 10 (a). FIG. 11B also shows bitmaps of images A and B having the same definition as in FIG. Further, the dots indicated by ● in the bitmap of the image before correction are dots that are in a line-symmetrical position with respect to the vertical line. In this image data processing apparatus, a plurality of dots output from the pattern recognition means 74 are displayed. The code information of the bits is the same for all code information signals other than the SLOP signal, which is a bit indicating whether the slope of the line segment is upper right or lower right. However, here, the SLOP signal indicating the inclination of the line segment becomes the same SLOP signal = 0 by the operation of the inclination bit switching means 78 by the inclination bit control signal, and the SLOP signal for the dot indicated by ● is the same as in FIG. Assuming that the multi-bit code information output from the other pattern recognition means 74 is xxx, the multi-bit code information input as the address of the memory block 75 is the dot position of ● in both the image A and the image B. , “0xxx”. Therefore, the corrected image A and image B shown in the figure are converted into the same image data image.
This is a method in which jaggies are corrected by the same image data, as in the corrected image shown in FIG. 11B, and correction with less accuracy in terms of jaggy correction than the method described in FIG. However, for an electrostatic latent image obtained by electrophotography, there is a possibility that a correction result equivalent to the setting shown in FIG. 11A may be obtained depending on an image to be subjected to jaggy correction, and a memory used for jaggy correction. It is possible to reduce the capacity of the image data stored in the block 75 (reduction to half the capacity in the case of FIG. 11A) and to shorten the time for creating correction data.
This example is a first embodiment corresponding to claim 1.
[0021]
FIG. 12 is a block diagram showing a schematic configuration of the third embodiment of the dot correction unit 7, in which a code information conversion unit 79 further illustrated in FIG. 9 is provided.
The code information conversion means 79 outputs a plurality of bits of code information representing the feature of the line segment shape recognized for the target dot by the pattern recognition unit 74 and the determination unit 747 illustrated in the pattern recognition unit 74 of FIG. NO-MATCH signal, which is a determination signal as to whether or not correction is necessary as a dot at the boundary portion of the image data by recognizing the line segment shape of the boundary portion between the black dot region and the white dot region with respect to the target dot. If the NO-MATCH signal indicates that correction is necessary, the code information is sent to the memory block 75 as it is. If the NO-MATCH signal indicates that correction is not required, the target dot of the input code information is a white dot. Code information indicating white dots and black dots that do not require correction (white / black dots). It is converted into the capital of a total of two types) sent to the memory block 75.
The table of FIG. 13 shows the input / output state of the code information of the code information converting means 79. With the configuration of FIG. 1C, for example, when the multi-bit code information representing the feature of the line segment shape recognized for the target dot by the pattern recognition unit 74 is 12 bits (4096 types), 4096 types are available. If the code information includes a quarter of code information for which the NO-MATCH signal indicates that correction is not necessary (for example, the combination of the DIR0 and DIR1 signals output from the determination unit 747 in FIG. 5 is (DIR1 , DIR0) = (1, 1)), as shown in the table of FIG. 13, the code types can be reduced to 3074 types of code information, and the total capacity of correction data to be stored in the memory block 75 is reduced. it can.
Here, as shown in the table of FIG. 13, the code information is converted with the white dot 600h and the black dot 700h as the target code information indicating that correction is unnecessary.
This example is a third embodiment corresponding to claim 2.
[0022]
Next, FIG. 14 is a block diagram showing a schematic configuration of the fourth embodiment of the dot correction unit 7, which is further provided with code information aggregating means 80 shown in FIG. 12 described above. .
The code information aggregating unit 80 receives the multi-bit code information output from the code information conversion unit 79 described above, and converts the input multi-bit code information into an array of continuous values. The data is sent to the memory block 75.
The table of FIG. 15 shows the input / output state of the code information of the code information aggregation means 80. For example, as in the description of the second embodiment, the multi-bit code information representing the feature of the line segment shape recognized for the target dot by the pattern recognition unit 74 is 12 bits (4096 types), and the code information conversion means A case where the code type is reduced to 3074 types of code information and input to the code information aggregation unit 80 will be described.
In this case, the code information input to the code information aggregating means 80 remains 12 bits, and 3074 arbitrary numerical values out of 4096 numerical values that can be expressed by 12 bits are random values that can be taken. It will be distributed. Therefore, in the first embodiment, the 12-bit numerical value of the random array is assigned as the data call address of the memory block 75, and the random array of the data storage and the call to the memory block 75 is also assigned. The code information conversion means 79 reduces the types of code information, and the code information conversion means 79 is limited to whether the operations are performed separately for each address or to continuously operate for all 4096 types of addresses that can be expressed in 12 bits. However, the efficiency with respect to data access to the memory block 75 is not improved.
[0023]
Therefore, the code information aggregating unit 80 continuously inputs code information (3074 types of fixed values in actual use) which are input as 3074 types of arbitrary numbers among 4096 types of numerical values that can be expressed in 12 bits. If the data is converted into an array of 3074 types of values and sent to the memory block 75, 3074 types of continuous addresses can be accessed for storing and recalling data to the memory block 75. The efficiency with respect to data access to the memory block 75 at the time can be increased. In particular, when the data access to the memory block 75 cannot be performed by directly specifying an address from the CPU or the like, and the serial data transfer is performed, the address of the memory block 75 becomes a continuous array, so that the access time can be shortened. become.
This example is a third embodiment corresponding to claim 3.
[0024]
The timing control unit 77 includes an FGATE signal that defines the writing time for one page from the engine driver 4, an LGATE signal that defines a writing period for one line, an LSYNC signal that indicates the writing start and end timing of each line, and each dot The image clocks WCLK and RESET signals that take the reading and writing cycles are input, and the clock signals and the like necessary for synchronizing the operations are generated for the above-mentioned respective blocks 71-76.
The correction data in the pattern memory 75 can be selectively loaded from the ROM 32 or the ROM 42 by the MPU 31 of the controller 3 or the CPU 41 of the engine driver 4 or can be downloaded from the host computer 1. It is possible to easily change the correction data for the pattern to be corrected.
Further, in addition to the contents described above, the details of the contents of the following (1) to (4) are the same as those described in Japanese Patent Application Nos. 3-314928 and 4-301395. I will omit it.
(1) About window area division for matching, its detection pattern and use area,
(2) About each output signal from each block 741-748 which comprises the pattern recognition part 74,
(3) Regarding the action of each block in the pattern recognition unit 74,
(4) About the dot correction method
Finally, in the above-described embodiment, the embodiment in which the dot correction unit 7 as the image data processing device according to the present invention is provided in the internal interface 5 that connects the controller 3 of the laser printer 2 and the engine driver 4 has been described. However, the dot correction unit 7 may be provided on the controller 3 side or the engine driver 4 side.
Further, the present invention is not limited to a laser printer, and various image forming apparatuses that form images by developing them into a bitmap such as LED printers, various optical printers, digital copying machines, plain paper fax machines, and the like, and images formed thereby The present invention can be similarly applied to an image display device that displays
[0025]
【The invention's effect】
As described above, according to the present invention, the following actions and effects can be obtained with respect to the contents of each claim.
The image data processing apparatus can be used by sharing the line segment shape recognition pattern between the black dot area and the white dot area of the image data developed on the bitmap by the image data processing apparatus. It is possible to shorten the time for creating correction data used for the jaggy correction used, and at the same time minimize the data setting time during actual use.
Recognizing the line segment shape of the boundary between the black dot region and the white dot region of the image data developed on the bitmap, a plurality of bits representing the feature of the line segment shape recognized for the target dot The cost of the apparatus can be reduced by reducing the total capacity of a memory block that reads and outputs correction data stored in advance using code information as an address.
Time required for storing correction data necessary for image correction in the memory block can be shortened, and the use efficiency of software or hardware during actual use can be improved.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of a first embodiment of an image data processing apparatus (dot correction unit) according to the present invention.
FIG. 2 is a block diagram of an image forming apparatus (laser printer) having an image data processing apparatus embodying the present invention.
FIG. 3 is a block diagram of the printer engine shown in FIG. 2;
4 is a perspective view of a main part of the writing unit shown in FIG. 2. FIG.
FIG. 5 is a block configuration diagram of a pattern recognition unit shown in FIG. 1;
6 is a block configuration diagram of a FIFO memory and a window shown in FIG. 1. FIG.
7 is an explanatory diagram of the window shown in FIG. 6. FIG.
8 is an operation explanatory diagram of the memory block shown in FIG. 1. FIG.
FIG. 9 is a block diagram of a second embodiment of an image data processing apparatus according to the present invention.
10A and 10B are explanatory diagrams of the inclined bit switching means shown in FIG.
FIGS. 11A and 11B are operation explanatory diagrams of the inclined bit switching means shown in FIG.
FIG. 12 is a block diagram of a third embodiment of an image data processing apparatus according to the present invention.
13 is a table showing the input / output state of code information of the code information conversion means shown in FIG.
FIG. 14 is a block diagram of a fourth embodiment of an image data processing apparatus according to the present invention.
15 is a table showing the input / output state of code information of the code information aggregating means shown in FIG.
[Explanation of symbols]
1 ... Host computer,
2 ... Laser printer 3 ... Controller
4 ... Engine driver, 5 ... Printer engine,
6 ... Internal interface, 7 ... Dot correction unit,
10 ... paper cassette, 11 ... paper,
12 ... feed roller, 13 ... registration roller pair,
14 ... main motor, 15 ... photosensitive drum,
16 ... Charge charger, 17 ... Developing unit,
18 ... Transfer charger, 19 ... Conveyor belt,
20 ... Fusing unit, 21 ... Discharge roller,
22 ... paper discharge tray, 23 ... cleaning unit,
24 ... printed circuit board, 26 ... writing unit,
27 ... Sequence device group, 28 ... Sensors,
32 ... ROM, 33 ... RAM,
35 ... Control panel, 50 ... LD unit,
52, 57, 60 ... mirror, 55 ... polygon mirror,
56 ... Rotary deflector, 62 ... Synchronous sensor,
71 ... P / S converter, 72 ... FIFO memory,
73 ... Window, 74 ... Pattern recognition unit,
75 ... Memory block, 76 ... Video data output unit,
77 ... Timing control unit, 78 ... Inclination bit switching means,
79: Code information conversion means, 80 ... Code information aggregation means,

Claims (3)

A window for extracting the data of each dot in a predetermined area centering on the target dot of the image data developed in the form of a bitmap, and the white of the black dot area of the image data by the image data extracted through the window A pattern recognition means for recognizing a line segment shape at a boundary with a dot region and generating a plurality of bits of code information representing characteristics of the line segment shape recognized for the target dot; and at least the code information A discriminating unit that discriminates whether or not a dot needs to be corrected by using a part, and code information generated by the pattern recognition unit for the dot that has been determined to be corrected by the discriminating unit in advance as an address An image data processing apparatus comprising a memory block that reads out and outputs stored correction data, and each dot Inclination bit for setting whether to enable or disable the bit indicating whether the slope of the line segment is the upper right or the lower right slope among the plurality of bits representing the feature of the line segment shape recognized An image data processing apparatus comprising a switching unit. Of the plurality of bits of code information representing the feature of the line segment shape recognized for each dot of the image data developed in the form of a bitmap output from the pattern recognition means, it is determined that correction is unnecessary by the determination means. For the generated dots, there is provided code information conversion means for converting into black and white code information of only one bit each indicating only whether the target dot is a black dot or a white dot, and correction is performed by the discrimination means. The multi-bit code information generated by the code information conversion means, together with the multi-bit code information for the dot determined to be necessary, functions as an address of a memory block that reads out and outputs correction data stored in advance. The image data processing apparatus according to claim 1. 3. The image data processing apparatus according to claim 2, further comprising code information aggregating means for sending an array of code information sent to the memory block to the memory block as a continuous address.

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