JP3530284B2 - Image data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing applied to an image forming apparatus of an electrophotographic system using digital image data such as an optical printer such as a laser printer, a digital copying machine, a plain paper fax machine, or an image display apparatus. The present invention relates to a device, and more particularly, to an image quality improving process thereof.

[0002]

2. Description of the Related Art In the above-mentioned image forming apparatus or image display apparatus, character image data obtained by converting character code data using font data, or image image data read by an image scanner or the like is quantized, Bitmap data (dot matrix) is developed as binary data in the video memory area on the memory (RAM), which is sequentially read and sent as video data to the image forming unit (engine) to form an image on recording paper. Or send it to the image display unit (display) to display the image on the screen.

In this case, if the image forming object is an analog image, it can be continuous in any direction, but the digital bit map image developed by quantizing it is stepped in 1 dot units in the direction orthogonal to the dot matrix. Since the direction can be changed only in a shape, the formed image is distorted. As a result, jaggies are created in which straight lines and smooth curves that are inclined with respect to the orthogonal direction of the dot matrix are formed in a staircase pattern, so that characters and images (particularly the outlines) have the same shape as the original image or have the desired shape. It was difficult to form.

An effective method for reducing such image distortion is to increase the resolution of the bitmap image by reducing the dot size of the dot matrix to increase the density. However, increasing the resolution will increase the cost significantly. For example, 300 × 3
When the resolution of a two-dimensional bitmap of 00 dpi is doubled, a bitmap of 600 × 600 dpi can be obtained, but a memory capacity of 4 times and a data processing capacity of 4 times speed are required.

As another method for reducing the distortion of an image, an interpolation technique is used to connect stepwise corners to form a continuous slope, or the brightness of adjacent dots is averaged to obtain an edge. Although there is also a method of blurring the image, this method smoothes the staircase-shaped jaggies, but also removes fine shapes, which causes a problem of lowering contrast and resolution.

Therefore, for example, US Pat. No. 4,544,9
As seen in No. 22, smoothing is performed by selectively adding or removing dots smaller than the standard dot width to a specific portion of the dot pattern developed in the bitmap form. Techniques are being developed. Therefore, pattern recognition and template matching have been performed as a technique for detecting a specific portion of the dot pattern to be corrected.

According to this method, the image quality can be improved by licking the line shape without impairing the contrast, but pattern recognition or template matching processing is performed for all positions of an arbitrary bitmap image. Since each dot is corrected according to the result, there is a problem that the processing device is very expensive and the processing time is long.

In order to solve such a problem, as shown in Japanese Patent Application Laid-Open No. 2-112966, a bit map and a predetermined pre-stored template are collated for each small piece and preselected. It has been proposed to detect a match with the characteristics of the bitmap and replace each of the matched pieces with a correction dot to improve the image quality of the print image.

In order to implement this method, for example, the data of the expanded bitmap image is serialized and the FI
It is input to the FO buffer, and M bits (M ×
(N bits) a subset of the bitmap image is formed, from which data is observed or extracted through a sample window having a predetermined shape and number of bits and having a central bit, and the data is stored in advance. Matching is performed by matching the data of various templates having the characteristic pattern to be performed.

When any template is matched, the center bit is replaced with a compensation sample (correction dot) corresponding to the template, and when no template is matched, the matching sample is corrected. The center bit is not corrected. By performing such a process on the entire arbitrary bitmap image while sequentially shifting the input image data so that each bit becomes the central bit in sequence, the memory can be processed more than other techniques described above. It is possible to precisely improve the image quality without increasing the data storage capacity or the processing capacity of the arithmetic unit.

However, even with such an image data processing method, the data of the template corresponding to the sample window must be created and stored in the memory for all the characteristic patterns to be corrected in advance. In order to be able to deal with the image data of the above, the number of templates becomes considerably large, and not only the time and cost required for the creation become enormous, but also the memory for storing the data of the large number of templates requires a large capacity. become.

Further, each bit constituting the target image data is sequentially made into a central dot, and a pattern of a bitmap image observed or extracted through the sample window with respect to each central dot and all the previously stored patterns. Since it is necessary to match (match) with the pattern of the template, there is a problem that the template matching process takes time.

In order to solve such a problem, Japanese Unexamined Patent Publication No.
A new image data processing method and its apparatus have been developed as seen in Japanese Patent Publication No. 207282. According to this image data processing method, data that needs to be stored in the memory in advance is corrected in order to correct the jaggies of the contour lines and improve the image quality of the image data expanded in the bitmap form. It is possible to minimize the number of dots in the image data that need correction and determine correction data for the dots that need correction in a very short time by simple determination and calculation by a microprocessor or the like.

That is, in this image data processing method, the line segment shape at the boundary between the black dot area and the white dot area of the image data developed in the bit map form is recognized to recognize each required dot. Replace the line segment shape feature with multi-bit code information and use at least a part of the code information to determine whether or not the dot needs correction,
The dots determined to be corrected are corrected according to the code information. The code information representing the characteristics of the line segment shape includes a code indicating the inclination direction of the line segment, a code indicating the degree of inclination, and the first dot of the line segment that continues in the horizontal or vertical direction of the target dot. And a code indicating the position of.

Further, the data of each dot in a predetermined area is extracted through a window with the target dot of the image data as the center, and the window is divided into a central core area and a plurality of peripheral areas around the core area. Then, the code information is generated based on a combination of the recognition information based on the image data extracted from the core area and the recognition information based on the image data extracted from one or more peripheral areas designated according to the recognition result. .

On the other hand, the image data processing apparatus according to this image data processing method has a window for extracting data of each dot in a predetermined area centering on a dot which is a target of image data developed in a bit map form, and a window for extracting the data. The line segment shape at the boundary between the black dot region and the white dot region of the image data is recognized based on the image data extracted through the window, and the feature of the line segment shape recognized for the target dot is expressed. A pattern recognition means for generating code information of a plurality of bits, a determination means for determining whether or not a dot needs correction by using at least a part of the code information, and a dot for which correction is determined by the means. On the other hand, the correction information stored in advance is read out by using the code information generated by the pattern recognition means as an address. It is obtained by a pattern memory.

Then, as the code information representing the feature of the line segment shape recognized by each of the required dots by the pattern recognition means, a code indicating the inclination direction of the line segment, a code indicating the degree of inclination, and a target The code information including the code indicating the position from the first dot of the line segment that continues in the horizontal or vertical direction of the dot to be generated is generated.

In this image data processing device,
The window is divided into a core area in the center and a plurality of peripheral areas around the window, and the pattern recognition means recognizes image data extracted from the core area, and Based on a peripheral area recognition unit that recognizes image data extracted from one or more peripheral areas specified according to the recognition result, and a combination of recognition information by the core area recognition unit and recognition information by the peripheral area recognition unit. And a means for generating the code information.

According to the image data processing method and apparatus described above, the line segment of the boundary portion (outline of characters or the like) between the black dot area and the white dot area of the image data expanded in the bitmap form. Recognize the shape, replace each required dot with multi-bit code information, use at least part of the code information to determine whether the dot needs correction, and select the dot that needs correction. On the other hand, since the correction is performed according to the above code information, it is not necessary to previously create and store all the characteristic patterns that need to be corrected as templates, and the dots that need to be corrected and the dots that need to be corrected need not be stored. The correction data for can be determined easily using the code information in a short time.

The code information representing the characteristics of the line segment shape is
It can be easily generated depending on the inclination direction of the line segment, the degree of inclination, the position of the target dot from the first dot that is continuous in the horizontal or vertical direction, and the like.

[0021]

In order to improve the image quality by correcting the jaggies of the contour lines in the image data expanded in the bit map by the image data processing method and the image data processing apparatus as described above. , The amount of data that needs to be stored in the memory in advance is reduced, the determination of the dots of the image data that need to be corrected and the determination of the correction data for the dots that need to be corrected are performed by a simple determination and calculation by the CPU or the like. It became possible to do it in an extremely short time.

Therefore, the present invention is an apparatus for further reducing the amount of data that needs to be stored in the memory in advance in order to cope with the higher resolution of image data in the image data processing apparatus and to improve the image quality. It is an object of the present invention to reduce its own cost and improve versatility regarding control of an image data processing device.

[0023]

In order to achieve the above object, the present invention provides an image data processing apparatus having the following (a) to (g). (A) A window for extracting the data of each dot in a predetermined area centering on the target dot of the image data developed in the bit map form, (b) the image data by the image data extracted through the window A pattern recognition means for recognizing the line segment shape of the boundary portion between the black dot area and the white dot area, and generating a plurality of bits of code information representing the feature of the recognized line segment shape for the target dot,

(C) Discriminating means for discriminating whether or not the target dot is a dot that needs to be corrected by using at least a part of the above code information, and (d) image data expanded in a bit map form. A resolution setting unit that can set what resolution the image data is, and generates code information indicating what resolution each dot of the image data developed by the setting is.
(E) The same image data expanded in the same bitmap as the image data expanded in the above bitmap is repeatedly generated for any timing signal any number of times, and each generated image data is Image data generation means for generating code information indicating whether the generation is the first time,

(F) Code information selecting means for selecting either the code information generated by the image data generating means or the code information generated by the setting of the resolution setting means, and (g) correction by the discriminating means. For the dot determined to be necessary, the pre-stored correction data is read and output using the code information generated by the pattern recognition means and the code information selected by the code information selection means as addresses. Correction data output means,

Then, the correction data output means uses the code information generated by the pattern recognition means and the code information selected by the code information selection means as addresses to generate a pattern of correction data stored in advance. A table memory for reading and outputting the indicated code information, and a pattern memory for reading and outputting the correction data stored in advance by using the code information output from the table memory as an address may be configured.

Alternatively, the correction data output means uses the code information generated by the pattern recognition means as an address to read out and output the code information indicating the pattern of the correction data stored in advance, and the table memory. The code information output from the memory and the code information selected by the code information selecting means may be used as addresses to form a pattern memory that reads out and outputs the correction data stored in advance.

Further, it is preferable to provide a means for replacing the code information indicating how many times each image data generated by the image data generating means is generated with the code information in which the generation order is reversed .

[0029]

The image data processing apparatus according to the present invention has the same function as that of the image data processing apparatus which is the basis of the present invention described above, and further determines what resolution the image data developed in the bit map form is. It is possible to set, and it is possible to select whether to perform correction with different data for each resolution, or to perform correction with different data for each image data developed in a repeatedly generated bitmap, It is possible to save memory by effectively using a memory related to image data processing and to improve versatility in creating data for image data processing (image correction data and the like).

Further, the image data expanded in the same bitmap as the image data expanded in the bitmap is repeatedly generated an arbitrary number of times with respect to an arbitrary timing signal, whereby the bitmap of each time is generated. It is possible to increase the degree of freedom in selection of image data processing (image correction data) even for the same image data expanded in (3) and improve versatility in creating image correction data.

Further, the correction data output means uses the code information generated by the pattern recognizing means and the code information selected by the code information selecting means as an address to form a pattern of the correction data stored in advance in the table memory. If the code information shown is read and output, and the correction information stored in advance in the pattern memory is read and output using the code information as an address, the total capacity of the memory related to image correction is deteriorated. Can be reduced without

Further, the correction data output means reads out and outputs the code information indicating the pattern of the correction data stored in advance in the table memory by using the code information generated by the pattern recognition means as an address, and outputs the code information. Even if the correction data stored in advance in the pattern memory is read out and output using the code information selected by the code information selecting means as an address, the total capacity of the memory relating to image correction is reduced. Can be reduced without incurring.

Further, if the code information indicating how many times each image data generated by the image data generating means is generated can be replaced with code information in which the generation order is reversed. The versatility of creating image correction data when improving the image quality of the image data developed in the same bitmap form repeatedly generated for any timing signal any number of times can be improved.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a laser printer which is an image forming apparatus embodying the present invention. The laser printer 2 includes a controller 3, an engine driver 4, a printer engine 5,
And an internal interface (hereinafter abbreviated as “internal I / F”) 6.

Then, the laser printer 2 receives the print data transferred from the host computer 1, develops it into bit map data in page units by the controller 3, and converts it into video data which is dot information for driving the laser. The converted image is sent to the engine driver 4 via the internal I / F 6, and the printer engine 5 is sequence-controlled to form a visible image on a sheet. The internal I / F 6 is provided with a dot correction unit 7 which is an image data processing device according to the present invention, and dot correction is performed on the video data sent from the controller 3 to improve the image quality.

The controller 3 includes a main microcomputer (hereinafter referred to as "MPU") 31 and its MPU.
A ROM 32 storing programs and constant data and character fonts required by 31, a RAM 33 for storing temporary data and dot patterns, an I / O 34 for controlling data input / output, and the I / O 34 Through M
Comprised of an operation panel 35 connected to the PU 31,
They are connected to each other via a data bus, address bus, control bus, etc. The internal I / F 6 including the host computer 1 and the dot correction unit 7 is also connected to the MPU 31 via the I / O 34.

The engine driver 4 includes a sub-microcomputer (hereinafter referred to as "CPU") 41 and its CP.
ROM 42 storing programs and constant data required by U 41, and RAM 4 storing temporary data
3 and an I / O 44 for controlling the input / output of data, which are connected to each other by a data bus, an address bus, a control bus, and the like.

The I / O 44 is connected to the internal I / F 6, and inputs the video data from the controller 3 and the states of various switches on the operation panel 35 and the image clock (WC).
Status signals such as LK) and paper end are output to the controller 3. Further, the I / O 44 is connected to the writing unit 26 and the other sequence device group 27 which configure the printer engine 5, and is also connected to various sensors 28 including a synchronization sensor described later.

The controller 3 is the host computer 1
Receives commands such as print commands and print data such as character data and image data, edits them,
If it is a character code, it is converted into a dot pattern necessary for image writing by a character font stored in the ROM 32, and bitmap data of those characters and images (hereinafter collectively referred to as “image”) is converted into a video R in the RAM 33.
The page is expanded in the AM area.

When the image signal WCLK is input from the engine driver 4 together with the ready signal, the controller 3 converts the bit map data (dot pattern) developed in the video RAM area in the RAM 33 into video data synchronized with the image clock WCLK. , Inside I
Output to the engine driver 4 via / F6. The dot correction unit 7 in the internal I / F 6 performs dot correction on the video data according to the present invention as described later.

Further, on the operation panel 35, there are switches and indicators (not shown) for controlling data according to instructions from the operator, transmitting the information to the information engine driver 4, and displaying the printer status on the indicator. To do.

The engine driver 4 receives the dot-corrected video data from the controller 3 through the internal I / F 6, and inputs the video data to the writing unit 26 of the printer engine 5 and a sequence device group 27 such as a charging charger and a developing unit described later. Control, or input video data required for image writing via the internal I / F 6 and output to the writing unit 26, and input signals indicating the state of each part of the engine from the synchronization sensor and other sensors 28. It processes and outputs necessary information and status signals of error status (for example, paper end) to the controller 3 via the internal I / F 6.

FIG. 3 is a schematic structural view showing the mechanism of the printer engine 5 in the laser printer 2. According to the laser printer 2, the upper and lower two-stage paper feed cassette 1
0a or 10b, for example, the upper sheet feeding cassette 1
The paper 11 is fed by the paper feed roller 12 from the paper stack 11a of 0a, the paper 11 is timed by the registration roller pair 13, and then the photoconductor drum 1
5 is conveyed to the transfer position.

The surface of the photosensitive drum 15 which is driven to rotate in the direction of the arrow by the main motor 14 is charged by the charging charger 16 and is scanned by the PWM-modulated spot from the writing unit 26 to electrostatically latentize the surface. An image is formed. The latent image is visualized with toner attached by the developing unit 17, and the toner image is transferred onto the sheet 11 conveyed by the pair of registration rollers 13 by the action of the transfer charger 18.

The transferred sheet is separated from the photoconductor drum 15, and is fixed by the conveyor belt 19 to the fixing unit 20.
To the fixing roller 20b by the pressure roller 20a, and fixing is performed by the pressure and the temperature of the fixing roller 20b. The paper leaving the fixing unit 20 is
Paper ejection tray 2 provided on the side surface by the paper ejection roller 21
It is discharged to 2.

On the other hand, the toner remaining on the photosensitive drum 15 is removed and collected by the cleaning unit 23. Further, in the upper part of the laser printer 2, a plurality of printed circuit boards 2 constituting the controller 3, the engine driver 4, and the internal I / F 6, respectively.
4 is installed.

FIG. 4 shows the writing unit 26 shown in FIG.
It is a principal part perspective view which shows the structural example of. The writing unit 26 includes an LD (laser diode) unit 50,
A rotary deflector 56 including a first cylinder lens 51, a first mirror 52, an imaging lens 53, a disk type motor 54, and a polygon mirror 55 rotated by the disk motor 54 in the direction of arrow A, and a second mirror 57, Second cylinder lens 58,
And a third mirror 60, a condenser lens 61 composed of a cylinder lens, and a synchronization sensor 62 composed of a light receiving element.

The LD unit 50 has a laser diode (hereinafter referred to as "LD") and a collimator lens for converting a divergent beam emitted from the LD into a parallel light beam, which are integrally incorporated therein. The first cylinder lens 51 has a function of shaping the parallel light beam emitted from the LD unit 50 in the sub-scanning direction on the photosensitive drum 15, and the imaging lens 53 reflects the parallel light reflected by the first mirror 52. It is converted into a convergent beam and is incident on the mirror surface 55a of the polygon mirror 55.

The polygon mirror 55 has each mirror surface 55a.
Rotation of a post-object type (a type of arranging a polarizer after converting a light beam into convergent light) which does not use an fθ lens conventionally arranged between the second mirror 57 and an R polygon mirror formed by bending The polarizer 56 is used.

The second mirror 57 reflects the beam (scanning beam) reflected and polarized by the rotary polarizer 56 toward the photosensitive drum 15. The scanning beam reflected by the second mirror 57 passes through the second cylinder lens 58 and forms an image as a sharp spot on the main scanning line 15a on the photosensitive drum 15.

The third mirror 60 is arranged outside the scanning area on the photosensitive drum 15 by the light beam reflected by the rotary polarizer 56, and the incident light beam is synchronized with the synchronous sensor 62.
Reflect toward the side. The light beam reflected by the third mirror 60 and condensed by the condenser lens 61 is the synchronization sensor 6
A light receiving element such as a photodiode, which constitutes the second element 2, converts it into a synchronization signal for keeping the scanning start position constant.

FIG. 1 is a block diagram showing a schematic structure of the dot correction unit 7 in FIG. 2, and FIG.
It is a figure which shows the specific structural example of O memory 72 and window 73).

As shown in FIG. 1, the dot correction section 7 includes a parallel / serial converter (hereinafter abbreviated as "P / S converter") 71, a FIFO memory 72, a window 73, a pattern recognition section 74, and correction data output means. A memory block 75, a video data output section 76, a timing control section 77 for synchronously controlling these, a control signal generating means 78 for generating a control signal for controlling the timing of image data processing by the timing control section 77, and an internal The resolution setting means 79 for setting the resolution of the image data expanded in the memory in a bit map form, the count inverting means 80, and the selector 8
It is composed of 1.

The timing control unit 77 uses the FGAT which defines the writing period for one page from the engine driver 4.
LGAT that defines the E signal and the writing period for one line
The E signal, the LSYNC signal indicating the write start and end timings of each line, the image clock WCLK that takes a read and write cycle for each dot, and the reset (RESET) signal are input to the blocks 71 to 76. It generates clock signals and the like necessary for synchronizing operations. Further, the timing control unit 77 includes
Timing signal generating means is provided and outputs a line synchronizing signal (LSINC-OUT) and a line gate signal (LGATE-OUT) to the controller 3.

However, the operation basic clock for operating the timing control unit 77 to generate each of the above output signals is a control signal different from the signal input from the engine driver 4 and is shown in FIG. The control signal generated by the control signal generation means 78 provided inside the dot correction section 7 or the control signal generated by any signal generation means provided outside the dot correction section 7 is used. A voltage-controlled oscillator (VCO), for example, is used as the control signal generating means 78 provided inside, and a voltage-controlled oscillator (VCO), a crystal oscillator, or the like is used as the signal generating means provided outside the dot correction section 7. Shall be used.

In the P / S converter 71, the video data transferred from the controller 3 shown in FIG.
In the case of (bit) data, it is provided to convert it to serial (1 bit) data and send it to the FIFO memory 72, and basically does not participate in dot correction. If the video data transferred from the controller 3 is serial data, the P / S converter 71 is not necessary.

The FIFO memory 72 is a first-in-first-out memory, and stores a plurality of lines of video data (seven lines in this embodiment) sent from the controller 3 as shown in FIG. The line buffers 72a to 72g for storing the multiplexer 7
It is serially connected via 21.

Here, the multiplexer 721, when the data select (data-sel) signal from the timing signal generating means provided in the timing control section 77 is "0",
Serial video data sent from the controller 3 via the P / S converter 71 and the line buffer 72a
When the output data from ~ 72f is "1", the output data from the line buffers 72a to 72g are selected and input and stored in the line buffers 72a to 72g.

Therefore, the operation of the FIFO memory 72 is as shown in the timing chart of FIG. 6 or 7. That is, with respect to the input of video data (1, 2, 3, 4, etc.), the output of each line buffer becomes a repetitive output as shown by a data select (data-sel) signal, which is an arbitrary timing signal. As the code information indicating how many times the output of the line buffer is repeatedly generated, the count signal (A1
4, A15) is output. The numerical value of this count signal is counted up with the first generation being 0. In addition, in FIG. 6 and FIG. 7, the portion indicated by the broken line indicates indefinite data.

However, at this time, only the write signal is given to the FIFO memory 72 during the period shown in FIGS. 6 and 7 in which the first data-sel signal is "0". Only the data is written, and then the data write and read signals are always
It is assumed that data is written bit by bit and data is read bit by bit at the same time. The FIFO memory 72 serves as the image data generating means in the present invention.

The count signals (A14, A15) output from the FIFO memory 72 serve as one input of the selector 81 as they are, and also the inverted count signal inverted by the count inversion means 80 as shown in FIGS. 6 and 7. (! A14,! A15) is the other input of the selector 81. Then, one of the count signals is selected by the selector 81 and given to the memory block 75. Here, the inverted count signal (! A14,! A15)
Is a signal in which the code information indicating how many times each of the generated image data of the count signals (A14, A15) is generated is replaced with code information in which the generation order is reversed.

The window 73 in FIG. 5 is a FIFO.
11-bit shift registers 73a to 73g are serially connected to 7 lines of data output from the line buffers 72a to 72g of the memory 72, and a pattern detection window (sample window: 8 shows its shape example by a broken line). The bit in the middle of the shift register 73d at the center (indicated by X in FIG. 5) is the storage position of the target dot (target dot) that is the target.

Of the shift registers 73a to 73g forming the window 73, the shift register 7
3a and 73g are 7 bits, shift registers 73b and 73
8 bits is sufficient for f, and the portion indicated by the broken line in FIG. 5 may be omitted. Line buffer 7 forming the FIFO memory 72
2a to 72g and the shift registers 73a to 73g forming the window 73 sequentially shift the video data bit by bit, thereby sequentially changing the target dot, and the video in the window 73 centered on each target dot. Data can be continuously extracted.

Based on the dot information extracted from the window 73, the pattern recognition section 74 determines the target dot of interest and its surrounding information, especially the line segment shape of the boundary between the black dot and the white dot of the image data. Features are recognized, and the recognition result is output as code information in a predetermined format. This code information becomes the address code of the memory block 75.

FIG. 9 is a block diagram showing the internal structure of the pattern recognition section 74 and the relationship with the window 73. A window 73, which is a sample window, has a central 3 × 3 bit core area (3 × 3 dot area shown by a solid line in FIG. 8) 7.
3C, an upper area 73D, a left area 73L and a right area 73R. The details will be described later.

The pattern recognition section 74 includes a core area recognition section 741, a peripheral area recognition section 742 and a multiplexer 74.
3, 744, Gradient calculation unit 745, Position (Posit)
ion) calculation unit 746, determination unit 747, and gate 748. The peripheral region recognition unit 742 further includes an upper region recognition unit 742U, a right region recognition unit 742R, a lower region recognition unit 742D, and a left region recognition unit. It is composed of 742L. The function of each of these units is the same as that described in Japanese Patent Application Laid-Open No. 5-207282 related to the previous application, but they will be described later.

The resolution setting means 79 in FIG.
By writing data by U, etc., of the dot correction section 7
A means for image data developed in the internal memory to a bit-mapped is set whether of any resolution, from the resolution setting unit 79, the bitmap
Code information A12 and A13 indicating the resolution of the image data expanded in a frame shape is generated and given to the memory block 75.

Here, the memory block 75 in FIG.
That is, the specific configuration example and the operation of the correction data output means will be described with reference to FIGS. (1) Example shown in FIG. 10 Although not related to the present invention, it is shown for comparison and is the same as that described in Japanese Patent Application Laid-Open No. 5-207282 filed previously. The memory block 75 includes only the pattern memory 752, and the pattern recognition unit 7
Using the code information output from No. 4 as an address, the correction data stored in advance in the pattern memory 752 is read, and the laser driving video data is output. This video data becomes a corrected dot pattern.

(2) Example shown in FIG. 11 This example shows the memory configuration of an embodiment corresponding to claim 1, and the memory block 75 is also the pattern memory 752.
Composed of only. However, the code information output from the pattern recognition section 74 and the resolution setting means 7 shown in FIG.
The code information (A12, A13) indicating the resolution of the image data expanded in the form of a bitmap output from No. 9 or the image data output from the FIFO memory 72 which is the image data generating means. A count signal (A14, A15), which is code information indicating how many times the signal is generated by repeating an arbitrary number of times with respect to an arbitrary timing signal, or an inverted count signal (! A14 ,! A15) obtained by inverting the count signal. ) Is selected by the selector 82 as an address.

Then, according to the selected address,
The correction data stored in advance in the pattern memory 752 is read and the video data for driving the laser is output. This is the corrected dot pattern. Note that the selector 8
The selection of code information by 2 is performed by setting a register or the like. Therefore, in this example, unlike the example shown in FIG. 10, the resolution of the image data to be corrected is different, or the number of times of image data generated by repeating any number of times with respect to any timing signal. Since it is possible to recognize this, it is possible to select different output for each resolution or each generation count even for code information showing the same line segment shape feature.

(3) Example shown in FIG. 12 This example shows the memory structure of an embodiment corresponding to claim 2, and the memory block 75 is composed of a table memory 751 and a pattern memory 752. The table memory 751 stores the code information output from the pattern recognition unit 74 and the selector 8 as in the case of the above-described example.
2 is selected, that is, the code information (A12, A1) output from the resolution setting means 79.
3), or the code information (A14, A15) output from the FIFO memory 72 or the code information (! A14,! A15) obtained by reversing the order thereof as an address, the pattern of the correction data stored in advance. The code information shown is read and output.

Then, the pattern memory 752 reads the correction data stored in advance by using the code information output from the table memory 751 as an address and outputs the laser driving video data, which becomes the corrected dot pattern. . The selection of the code information by the selector 82 in this case is also performed by setting the register or the like.

In other words, in this example, the dot pattern of the correction data described in the above two examples is actually a large part of the code information indicating the feature of the line segment shape recognized for each dot. Since they are redundant and are much smaller than the number of code information (correction data for a plurality of different code information uses one common correction pattern), the pattern of the correction data in the table memory 751 is set. By setting the bit width of the output data, which is the code information shown, to a size that can cover the total number of dot patterns of the correction data, and by giving this code information as an address of the pattern memory 752, the total memory capacity related to image correction can be obtained. The number can be reduced without lowering the function.

Further, in this example, similarly to the example shown in FIG. 11, which resolution the image data to be corrected has, or what number of times the image data to be corrected is repeatedly generated an arbitrary number of times with respect to an arbitrary timing signal. Since it is possible to recognize whether the image data is the image data, it is possible to select the output as different data for each resolution or for each generation even for the code information indicating the same line segment shape feature.

(4) Example shown in FIG. 13 This example shows the memory structure of an embodiment corresponding to claim 3, and in this example as well, the memory block 75 is composed of a table memory 751 and a pattern memory 752. However, the table memory 751 is used by the pattern recognition unit 7
By using only the code information output from No. 4 as an address, the code information indicating the pattern of the correction data stored in advance is read and output.

The pattern memory 752, together with the code information output from the table memory 751, is code information selected by the selector 82, that is, the bits output from the resolution setting means 79 in FIG. Code information (A12, A1) indicating the resolution of the image data developed in the map form
3), or code information (A14, A15) indicating the number of times the image data output from the FIFO memory 72 is generated an arbitrary number of times with respect to an arbitrary timing signal, or the order thereof. Using any of the reversed code information (! A14,! A15) as an address, the correction data stored in advance is read and the laser driving video data is output, and this becomes the corrected dot pattern. The selection of the code information by the selector 82 in this case is also performed by setting the register or the like.

That is, also in this example, as in each of the above-described examples, the dot pattern of the correction data is actually in many parts with respect to the code information indicating the feature of the line segment shape recognized for each dot. Since it overlaps and is much smaller than the number of the code information, the bit width of the output data, which is the code information indicating the pattern of the correction data in the table memory 751, is set to a size that can cover the number of dot patterns of the correction data, Further, by giving this code information as an address of the pattern memory 752, the total memory capacity related to image correction can be reduced without lowering the function.

At the same time, the code information indicating which image area the image data to be corrected belongs to, or the number of times the information is generated by repeating any number of times with respect to any timing signal is generated. Since any one of the code information shown is input as an address of the pattern memory 752, even code information showing the same line segment shape feature is output as different data for each image region or each generation number. You can choose.

FIG. 14 shows a comparison of memory capacities related to image correction according to the examples shown in FIGS. As can be seen from this figure, the example of the prior application shown in FIG. 10 has the minimum memory capacity (about 41 kb), but it does not depend on the resolution as in the embodiment of the present invention shown in FIG. 11 to FIG. It is not possible to realize a sophisticated function that outputs different correction data for each number of generations. The example shown in FIG. 11 can realize the above-described functions according to the present invention, but the total memory capacity of the memory block 75 is about 4 as compared with the example of FIG.
Doubled (about 164 kb).

The example shown in FIG. 12 can reduce the total memory capacity of the memory block 75 to about 2/3 (about 116 kb) while having the same function as that of FIG. Further, in the example shown in FIG. 13, the total memory capacity of the memory block 75 is
It can be smaller (about 34 kb) than that of FIG. The correction data of the memory block 75 can be selectively loaded from the ROM 32 or 42 by the MPU 31 of the controller 3 or the CPU 41 of the engine driver 4 shown in FIG. 2 or downloaded from the host computer 1. For example, it is possible to easily change the correction data for the pattern to be corrected of the image data.

The correction data output from the memory block 75 is an integral multiple (10 divisions) of the regular width of each dot of the video data sent from the controller 3, that is, a value obtained by dividing the laser emission time. In this case, the maximum value is 10 times) and the information is output in parallel. Figure 1
The video data output unit 76 sends the video data obtained by serializing the parallel information output from the memory block 75 to the printer engine 5, and turns on the laser diode of the LD unit 50, which is the light source provided in the writing unit 26. The signal source is turned on / off (see FIGS. 2 to 4).

However, the LD unit 5 in the above description is used.
The ON / OFF control of the laser diode of 0 assumes control by binary data, but when control by multi-value data is assumed, the above-mentioned video data output unit 7 is used.
It is no longer necessary to serialize the parallel information output from the memory block 75 according to No. 6 and send it to the printer engine 4 and output the parallel information from the memory block 75 as it is to the LD unit 50 (in this case, the multi-value control LD unit). Laser diode ON /
Writing is performed by the writing unit 26 by making it correspond to the data regarding the OFF control.

At this time, the parallel information from the memory block 75 is the table memory 75 described above.
Either 1 or the data output from the pattern memory 752 can be associated as parallel information for performing ON / OFF control of the multi-value control LD unit. Further, the above-mentioned parallel information recognizes the line segment shape of the boundary portion between the black dot area and the white dot area of the image data, which is the information itself developed in the bitmap form, and recognizes it for each required dot. The laser diode of the LD unit 50 has an O
In addition to being used as N / OFF control data, it is possible to use it as data when the CPU processes the image data processing at the time of image expansion (enlargement / reduction) of image data.

Further, as the data at the time of this image development, either the code information generated by the pattern recognition unit 74 described above or the data output from the table memory 751 or the pattern memory 752 in the memory block 75 described above is used. It is possible to correspond.

Next, an example of actual image data correction processing will be described with reference to FIGS. FIG. 15 is the original image data expanded in the form of bitmap, FIG.
FIG. 3 is a diagram showing a dot configuration of image data after the data processing for an example of image data having different resolutions. In both cases, (a) is 240 dpi and (b) is 480 dpi
It shows what the image looks like for i.

As described above, when the same original image data exists for different resolutions, the code information indicating the recognized line segment shape characteristics output from the pattern recognition unit 74 is associated with each corresponding dot position. However, the address to the memory block 75 is code information (A12, A1) indicating the above-mentioned resolution.
By adding 3), the address becomes different for each resolution, and the output data of the memory block can be output as different image data.

In FIGS. 17 to 19, the same image data as the image data expanded in the bit map form is repeatedly generated three times with respect to an arbitrary timing signal (Example 1 → 1-
1, 1-2, 1-3), and what happens to the image when it is set to perform different image data processing (image correction) for each number of generations. Here, the original image data shown in FIG.
Image data at the time of output by the FIFO memory 72 is repeatedly generated three times with respect to the LSYNC signal indicating the write start and end timings of each line of the main scanning of the laser printer, and as shown in FIG. The data is output to the pattern recognition unit 74 described above at a cycle of 1/3 of the original image data in the sub-scanning direction.

FIG. 18 shows a case where the original image data shown in FIG. 17A is divided into three parts in the sub-scanning direction without image data processing and the same image data is generated three times. Show. FIG. 19 shows an example when image data processing according to the present invention is performed.

In this case as well, the code information indicating the recognized line segment shape characteristics output from the pattern recognition section 74 is the same code information for each corresponding dot position, but the address to the memory block 75 is Is generated by adding the code information (A14, A15) indicating the number of times of generation of the image data expanded in the same bitmap described above or the code information (! A14,! A15) obtained by inverting the code information. Since the addresses are different, the output data of the memory block 75 can be output as different image data as shown in FIG.

20 to 23 show examples of the different image data. FIG. 20 shows the original image data, and FIG. 21 shows the same image data repeated three times without image data processing. Indicate the case. 22 and 23
FIG. 22 is a diagram showing an image of an output image after image data processing, and FIG. 22 shows a case where the image data generation counts are not interchanged in the left half part and the right half part, that is, as generation count information, An example in which the count signals (A14, A15) shown in FIG. 7 are used for the addresses of the memory block 75 is shown.

FIG. 23 shows the case where the image data generation counts in the left half portion and the right half portion are exchanged, that is, as the generation count information, the inverted count signal (! A1) shown in FIG.
4 ,! A15) is used as an address of the memory block 75. By reversing the order of the generated count information in this way, it may be possible to smoothly correct the inclined line.

However, in this example, the code information of the recognition result by the pattern recognition unit 74 with respect to the image data of the dot positions shown by squares with halftone dots in FIGS. 20 to 23 is the same code information. Shows. That is, when the image data generation counts are not exchanged, the shapes of the image processing dots at the dot positions shown by the squares are the same, and the shape of the boundary line segment of the right inclined line image is more jaggy (jagged). However, when the image data generation count is replaced, the shape of the image processing dot at the dot position where the jagged edge is generated is upside down, and the inclined line image on the right side is displayed. The shape of the boundary line segment of is a smooth process in which jaggies are not noticeable.

Here, a technique common to the previously filed invention which is the premise of the present invention will be described. First, the area division of the window for matching, its detection pattern, the used area, and the like will be described with reference to FIGS. 8 and 24 to 26.

(1) Window The window 73 used in the embodiment of the present invention is a sample window of 7 (height) × 11 (width), as shown in FIG. As shown in FIG. 7, it is composed of 7-line shift registers 73a to 73g.
Each line is composed of an 11-bit register. Of the total 77-bit register output, 49 dots surrounded by a broken line in FIG. 8 are used for detection of a specific pattern, that is, a line segment close to horizontal or vertical (strictly speaking, a boundary of a black dot area). .

(2) Core Area The area surrounded by the solid line in the window 73 shown by the broken line in FIG. 8 is the core area 73C of 3 × 3 dots. Core area 7
The central dot in 3C is the target pixel (target dot) to be corrected. 24 to 26 show examples of patterns appearing in the core region 73C of a line segment having a 1-dot width. In these figures, the black circles represent black dots, the double circles represent white dots, and the triangles represent undefined dots (either black or white is acceptable).

In FIGS. 24A to 24D, the inclination is 45 degrees (1 /
In 1), types of patterns appearing in the core region 73C of a line segment having a 1-dot width are illustrated. These patterns are not subject to correction in this example. A jaggy is recognized when the inclination is 1/2 or less in the case of a line segment close to horizontal, and when the inclination is 2/1 or more in the case of a line segment close to vertical. The recognition of the line segments close to horizontal and the line segments close to vertical is performed in the same manner. The only difference is that the matching pattern is rotated 90 degrees with respect to the other. Therefore, in the following description, only line segments that are nearly horizontal will be described.

FIGS. 25A to 25G exemplify the types of patterns appearing in the core area 73C of a line segment having a width of one dot which is nearly horizontal. When the inclination is ½ or less, there are the following two patterns that appear in the core region. When the step (change point) that is the source of jaggies is captured, it becomes a line segment (Ro, Ha, Ho, F) with a slope of 1/2, and otherwise it is a straight line (I,
D, G).

26A to 26G exemplify the types of patterns appearing in the core region 73C of a line segment having a width of one dot which is nearly vertical. If each of the patterns shown in FIGS. 24 to 26 is stored as a basic pattern, and the actual pattern in the core area 73C is captured and matched with each of these patterns, is it necessary to correct the pattern? It can be easily identified whether it can be part of a line segment that is nearly horizontal or part of a line segment that is nearly vertical.

(3) In the detection of the peripheral area jaggy pattern, the pattern appearing in the core area 73C has been described above, but the line segments of the patterns shown in FIGS. 25 and 26 are not horizontal or vertical straight lines,
The state around the core region 73C needs to be examined in order to reliably determine whether or not the line segment has a slope of 1/2 or less or 2/1 or more. Therefore, a peripheral area surrounded by a thick solid line in FIG. 27 is provided. 27A is a right region 73R, FIG. 27B is a left region 73L, and FIG. 27C is an upper region 73R.
U and (d) indicate the lower region 73D, respectively. One dot at each end of each of these peripheral regions overlaps two regions adjacent to each other.

Each of these peripheral regions 73R, 73L, 73
U and 73D are each subdivided into three sub-regions (however, the central region of each sub-region is used in duplicate). That is, the right area 73R and the left area 73L
Are right sub-regions 73 shown in (a) to (c) of FIG. 27, respectively.
Ra, 73Rb, 73Rc and left sub-region 73La, 7
It is divided into 3Lb and 73Lc. The upper region 73U and the lower region 73D are divided into upper sub regions 73Ua, 73Ub, 73Uc and lower sub regions 73Da, 73Db, 73Dc shown in (a) to (c) of FIG. 29, respectively.

The subdivision in this way is for ease of circuit design. Which of these sub regions is used to perform pattern detection is determined by the peripheral regions 73R and 73R.
It is determined by the state of the boundary (line segment) between the black dot and the white dot of the detection pattern in the core area 73C that is in contact with L, 73U, and 73D. That is, when the detection pattern of the line segment in the core area 73C is nearly horizontal and the inclination is ½ or less, the right area 73R shown in FIG.
The left area 73L shown in (b) or both may be examined. In addition, the detection pattern of the line segment is nearly vertical and the inclination is 2 /
In the case of 1 or more, the upper area 73U shown in (c) of FIG.
The lower region 73D shown in (d) or both may be checked.

In this case, as shown in FIG. 30 or 31, only the specific sub-region of each peripheral region needs to be checked according to the position of the line segment detected in the core region 73C. In the example of FIG. 30, the left sub-region 73Lb and the right sub-region 73Ra, and in the example of FIG. 31, the upper sub-region 73U.
It is only necessary to check b and the lower sub-region 73Dc. Note that FIG.
In the case of, only the right sub region 73Ra may be checked, and in the case of FIG. 31, only the upper sub region 73Ub may be checked.

Next, each output signal from each of the blocks 741 to 748 constituting the pattern recognition section 74 shown in FIG. 9 will be described. (1) Output signal H / V of the core area recognition unit 741: a signal indicating whether the line segment is close to horizontal or close to vertical. High level “1” when the line segment is close to horizontal, line segment close to vertical At the time of, the low level becomes "0".

DIR0 to 1: 2-bit coded signal indicating the inclination direction of the line segment. Two bits of DIR1 and DIR0 represent the following four types of information.

B / W: A signal indicating whether the target dot (pixel) is black or white, and the content of the target dot is output as it is.
Therefore, if the target dot is black, it is "1", and if it is white, it is "0". U / L: When the target dot is white, it is a signal indicating whether the position of the target dot is the upper side (right side) or the lower side (left side) of the line segment. If it is the upper side (right side), it is “1”. , Lower side (left side), it becomes “0”.

GST: A signal indicating whether or not the target dot is the start point of the gradient calculation, and is "1" when the target dot is the start point of the step (change point) which is the source of jaggies. In other cases, it is “0”. RUC: right area 7 with respect to the pattern in the core area 73C
The state of the 3R or the upper area 73U is also a flag indicating whether or not judgment is necessary, and is "1" if necessary and "0" if unnecessary.

LLC: This flag indicates whether or not the state of the left area 73L or the lower area 73D needs to be judged with respect to the pattern in the core area 73C, and is "1" if necessary and "0" if unnecessary. Becomes When both RUC and LLC are "1", the core area 73C
The line segment pattern inside is horizontal or vertical, and RUC, L
When LC is “0”, no matching is required.

CC0 to 1: 2-bit information indicating the number of continuous dots of the line segment pattern in the core area 73C, which is "0 to 0".
3 ”is shown. RUAS0 to 1: A 2-bit signal that specifies one of three sub-regions in the right region 73R or the upper region 73U.

(2) Output signals cn0 to cn2 of the peripheral area recognizing unit 742: 3-bit information indicating the number of continuous dots in the horizontal or vertical direction in the peripheral area with respect to a specific dot in the core area 73C. .About.4 ". dir0 to 1: A 2-bit signal indicating the inclination direction of the line segment pattern detected by the matching detection in the sub-region, and is coded in the same manner as DIR0 to DIR described above.

(3) Multiplexer (MUX) 743
Output signals RUCN0 to 744 of 744: 3-bit information indicating the number of horizontal or vertical continuous dots in the right area 73R or the upper area 73U. RUDIR0 to 1: Coded signals indicating the inclination directions of the line segments in the right region 73R or the upper region 73U. LLCN0-2: 3-bit information indicating the number of horizontal or vertical continuous dots in the left area 73L or the lower area 73D. LLDIR0 to 1: Coded signals indicating the inclination direction of the line segment in the left area 73L or the lower area 73D.

(4) Output signal DIR0 of the discriminating unit 747: signal DIR from the core area recognizing unit 741
Same as 0-1. NO-MATCH: A signal indicating that there is no pattern to be corrected in the recognized line segment (it becomes "1" when there is no pattern to be corrected).

(5) Output signals G0 to G3 of the inclination calculator 745: 4-bit code information indicating the degree of inclination (GRADIENT) of the recognized line segment. The degree of this inclination is not represented by a mathematical inclination angle but by the number of continuous dots in the horizontal or vertical direction of the line segment pattern of interest. That is, the number of continuous dots until the step of one dot occurs corresponds to the degree of inclination (angle).

(6) Position calculator 746 and gate 748
Output signal p0-3: 4-bit code information indicating the position (POSITION) of the target dot. If the line segment is close to horizontal, the number of dots from the left end to the target dot in the continuous dots, and the line segment close to vertical In this case, the number of dots from the lower end to the target dot in continuous dots. P0-3: Position code output from the gate 748,
When the signal NO-MATCH from the discriminator 747 is false (“0”), p0 to 3 are output as they are, and when true (“1”), they are “0”.

Next, the operation of each block in the pattern recognition unit 74 shown in FIG. 9 will be briefly described. The core area recognizing unit 741 extracts and takes in data of each dot in the core area 73C of the window 73, executes various judgments and counting on the target dot at the center thereof, and executes the above-mentioned respective signals H / V and B. / W and U / L are output to the pattern memory 75, and the multiplexers 743 and 744 are selected depending on H / V, that is, a line segment near horizontal or a line segment near vertical.
Switch each input of.

Further, RUC and LLC indicating which peripheral region the state needs to be determined are output to the inclination calculating section 745 and the determining section 747, and GST indicating whether or not the target dot is the start point of the step. Is output to the position calculation unit 746. In addition, DI which is code information indicating the inclination direction of the line segment
R0 to 1 are output to the determination unit 747.

Then, CC0 to 1 indicating the number of continuous dots in the core area are sent to the inclination calculating section 745, and RUAS is designated to specify one of the three sub areas of the upper area 73U and the right area 73R.
0-1 is the upper area recognition unit 742U of the peripheral area recognition unit 742.
And LLAS0 that specifies one of the three sub-regions of the lower region 73D and the left region 73R to the right region recognition unit 742R.
1 is output to the lower area recognition unit 742D and the left area recognition unit 742L.

The peripheral area recognizing section 742 is connected to the upper area recognizing section 7.
42U, right area recognition unit 742R, lower area recognition unit 742
The D and left area recognition unit 742L extracts and imports each dot data in the specified sub areas of the upper area 73U, the right area 73R, the lower area 73D, and the left area 73L of the window 73, and the line segment pattern thereof. Recognize
The multiplexer 743 is provided with cn0 to 2 indicating the number of continuous dots in the area and dir0 to dir indicating the inclination direction of the line segment.
Or output to 744.

When the signal H / V from the core area recognition section 741 is "0", the multiplexer 743 detects the upper area recognition section 7
When the information from 42U is "1", the right area recognition unit 742
Information from R is selected and input, and the number of consecutive dots in each sub-region is output to the inclination calculation unit 745 as RUCN0 to 2, and the inclination direction of the line segment is output to the determination unit 747 as RUDIR0-1.

When the signal H / V from the core area recognition section 741 is "0", the multiplexer 744 detects the lower area recognition section 7
When the information from 42D is "1", the left area recognition unit 742
Information from L is selected and input, and the number of consecutive dots in each sub-region is set to LLCN0 to 2, and the inclination calculation unit 745 and the position calculation unit 746 are instructed.
To the discrimination unit 747.

The discriminator 747 determines the code information DIR.
0 to 1, RUDIR 0-1 and LLDIR 0-1 and signals RUC and LLC are input to determine whether or not dot correction is necessary, and a code indicating the inclination direction of the line segment recognized as being necessary The information DIR0 to DIR1 is output and the determination signal N0-MATCH is set to "1". This signal closes the gate 748, and the position information P0-3
Will not be output.

The gradient calculator 745 inputs the code information CC0-1, RUCN0-2, and LLCN0-2 indicating the number of continuous dots and the signals RUC, LLC, respectively, and recognizes the gradient degree (GRADIENT) of the line segment pattern. ) Is calculated as the number of consecutive dots, and code information G0 to 3 is output. The position calculation unit 746 inputs the code information LLCN0 to 2 indicating the number of consecutive dots in the left area 73L or the lower area 73D of the window 73 and the signal GST, calculates the position (POSITION) of the target dot, and calculates the code. Information p0
3 (= P0 to 3) is output.

Here, the method of calculating the tilt and position in the tilt calculator 747 and the position calculator 746 will be described. Tilt degree (GRADIENT) and position (POSITION)
Is GST (1-GST = not GST), C, which is the information output from the core area recognition unit 741 described above.
It is calculated from C, RUC, LLC and RUCN, LLCN, which is information output from the peripheral usage area recognition unit 742 through the multiplexers 743, 744, by the following formulas 1 and 2.

[0123]

[Equation 1] GRADIENT = CC + (RUC × RUCN) + (L
LC x LLCN)

[0124]

[Equation 2] POSITION = GST + notGST × (LLCN + 2)

A concrete calculation example is shown by the examples of the line segment patterns shown in FIGS. In addition, d line 6 in each figure
The dots in the row are the target (target) dots. (1) In the core area 73C of the example window 73 shown in FIG. 32, the target dot is not the start point of the step and the number of continuous dots is 3,
Since it is also necessary to determine the states of the right area 73R and the left area 73L, the above-mentioned information output from the core area recognition unit 741 is GST = 0, CC = 3, RUC = 1, LLC =
It becomes 1.

Since the number of horizontal dots following the line segment pattern in the core area 73C is 1 in the left and right peripheral areas 73R and 73L, the above information output from the MUXs 743 and 744 is RUCN = 1. LLCN = 1.
Therefore, based on Equation 1 and Equation 2 above, the following Equation 3
The tilt and position can be calculated with.

[0127]

[Equation 3]   GRADIENT = CC + (RUC × RUCN) + (LLC × LLCN)           = 3 + (1 × 1) + (1 × 1) = 3 + 1 + 1 = 5 (Slope: 5)   POSITION = GST + notGST × (LLCN + 2)           = 0 + (1-0) × (1 + 2) = 0 + 1 × 3 = 3 (position: 3)

(2) Example shown in FIG. 33 A line segment pattern is shown when the data of each dot shown in FIG. 32 is shifted to the right by one bit. The difference from the case of FIG. 32 lies in the right region 73R. Since the number of continuous dots in the horizontal direction becomes 2 and the number of continuous dots in the horizontal direction in the left area 73L becomes 0, it is only a point where RUCN = 2, LLCN = 0. This is the same as in the case of FIG. Therefore, the inclination and the position can be calculated by the following equation 4 based on the above equations 1 and 2.

[0129]

[Equation 4]   GRADIENT = CC + (RUC × RUCN) + (LLC × LLCN)           = 3 + (1 × 2) + (1 × 0) = 3 + 2 + 0 = 5 (Slope: 5)   POSITION = GST + notGST × (LLCN + 2)           = 0 + (1-0) × (0 + 2) = 0 + 1 × 2 = 2 (position: 2)

(3) Example shown in FIG. 34 A line segment pattern is shown when the data of each dot shown in FIG. 33 is further shifted to the right by one bit. In the core area 73C of the window 73, the dot of interest is It is the start point of the step, the number of continuous dots is 2, and the right area 73R
The state of the left area 73L does not have to be determined, but the above-mentioned information output from the core area recognition unit 741 is GST = 1, CC = 2, RUC =
1, LLC = 0.

Since the number of horizontal dots following the line segment pattern of the core area 73C is 3 in the right area 73R and that in the left area 73L is 4, the above information output from the MUXs 743 and 744 is RUCN = 3, LLCN = 4. Therefore, the inclination and the position can be calculated by the following equation 5 based on the above equations 1 and 2.

[0132]

[Equation 5]   GRADIENT = CC + (RUC × RUCN) + (LLC × LLCN)           = 2 + (1 × 3) + (0 × 4) = 2 + 3 + 0 = 5 (Slope: 5)   POSITION = GST + notGST × (LLCN + 2)           = 1 + (1-1) × (4 + 2) = 1 + 0 × 6 = 1 (position: 1)

The above is an example of calculation in the case of a line segment pattern close to horizontal, but also in the case of a line segment pattern close to vertical, the RU
CN is only the number of continuous dots in the upper area 73U, and LLCN is only the number of continuous dots in the lower area 73D. The inclination degree (GRADIENT) is calculated by the equation 1 and the position (POSITION) is calculated by the equation 2 respectively. It can be calculated as in the case of the example.

Next, the dot correction method according to this embodiment will be described. First, correction of line segments that are nearly horizontal will be described with reference to FIGS. 30, 35, 37, and the like. Figure 3
In the 7 × 11 video area shown in FIG. 5, the circle indicated by the broken line is the dot information transferred from the controller 3, and the hatched portion changes the dot diameter by correction (changes the pulse width of laser ON). It has been added or has a dot added. The information indicated by the broken line transferred from the controller 3 is a line segment that is nearly horizontal with jaggies of 1/5 steps, as is clear from this figure.

In FIG. 35, the ON / OFF state of the laser based on the correction result of row d is shown below. Figure 30
Shows the state of the window in the case where the dot in the d-th row and the 9-th column in FIG. 35 becomes the target dot. Values of the output signal of each block in the pattern recognition unit 74 shown in FIG. 1 at this time are shown in the columns of FIG. 30 in (a) to (d) of FIG.

Of these signals, H / V, DIR1, DI
R0, B / W, U / L, G3 to G0, and P3 to P0 are address inputs of the pattern memory in the memory block 75 shown in FIG. 1, and the data corresponding to the address is stored as corrected video data in the memory. It is read from the block 75 and sent from the video output section 76 to the engine driver 4 of FIG. 2 and becomes a signal for driving the laser of the writing unit 26.

As a result, the pulse width of the laser ON at the time of writing the dot in the d-th row and the 9-th column in FIG. 35 is reduced to, for example, 6/10 of the pulse width at the full dot, and the dot diameter formed thereby. Is reduced to 6/10 as shown by the hatched full dots.
With respect to other dots, the above-mentioned signals are sequentially output as dots of interest, and the corrected video data is sent to the engine driver 4 by using the signals as addresses.
The dots shown in FIG. 5 are corrected as shown by hatching.

In this case, even if the data transferred from the controller 3 is a white dot, a correction dot having an optimum diameter is added as necessary by recognizing the line segment pattern around the dot. The reduction of the dot diameter or the diameter of the correction dot (pulse width of the laser ON) is made in units of 1 / (1/10 in this example) of the full dot diameter.

The corrected dot array shown in FIG. 35 seems to have a gap in the stepped portion, but the actual printing result of the laser printer is not such a fine print, and some blurring (spreading) occurs. As a result, these adjacent dots are connected and integrated with each other, whereby jaggies are corrected and a slightly inclined smooth straight line is formed.

Note that this example is a correction in the case of one dot line, but in the case of a boundary between a black dot area in which two or more black lines are lined up with a white dot area, a correction dot is placed on the white dot area side. The original black dot adjacent to the added portion is not corrected to reduce the diameter, and naturally, the correction dot is not added to the black dot area side. For example, in the diagram of the line segment pattern which is almost horizontal in FIG. 35, if the lower side is all black dot regions, e row 2 column 3 column d
The black dots in the 7th and 8th rows are left as full dots indicated by the dotted circles, and the correction dots in the 4th and 5th rows in the eth row and the 9th row and the Ath row are not added.

Next, the correction of a line segment close to vertical will be described with reference to FIG.
1, FIG. 36, FIG. 37, etc. will be described. In the 7 × 11 video area shown in FIG. 36, the circle indicated by the broken line is the dot information transferred from the controller 3, and the hatched portion has the dot position changed by correction. The information indicated by the broken line transferred from the controller 3 is a line segment that is almost vertical with a jaggy of 3/1 step, as is clear from this figure. Note that b
Figure 3 shows the ON / OFF state of the laser according to the line correction result.
It is shown below 6.

FIG. 31 shows the state of the window in the case where the dot on the b-th row and the 5-th column in FIG. 36 becomes the target dot. The values of the output signals of the blocks in the pattern recognition section 74 shown in FIG. 9 at this time are shown in the columns of FIG. 31 in (a) to (d) of FIG. H / V and DIR of these signals
1, DIR0, B / W, U / L, G3 to G0, P3 to P
0 becomes an address input of the memory block 75 shown in FIG. 1, data corresponding to the address is read out from the memory block 75 as corrected video data, and sent from the video output unit 76 to the engine driver 4 in FIG. And becomes a signal for driving the laser of the writing unit 26.

As a result, the pulse of the laser ON at the time of writing the dot of row b, column 5 in FIG. 36 is the pulse whose phase is delayed by ⅓ of the pulse width, although the width is not changed. The dot diameter formed thereby is also shifted from the original position shown by the broken line to the right in the figure by 1/3 of the diameter as shown by hatching.

With respect to the other dots, the above-mentioned signals are sequentially output as the dots of interest, and the corrected video data is sent to the engine driver 4 using the signals as addresses, so that the dots shown in FIG. 35 are hatched. The horizontal position is corrected as shown by the arrow, and a slightly inclined straight line without jaggies is formed. Also in this case, the dot position can be corrected in the horizontal direction in units of an integral fraction of the full dot diameter.

Note that this example is a correction in the case of one dot line. However, in the case of a boundary between a black dot area in which two or more black dots are lined up with a white dot area, the black dot area side to the white dot area When a correction dot whose position is shifted to the side is required, the original black dot is left at the original position and a new correction dot is added. For example, in the diagram of a line segment pattern which is almost vertical in FIG. 36, if the left side is all black dot areas, the original black dots in row b, column 5, column e, and column 6, are the original positions indicated by the dashed circles. A correction dot shown by hatching that is left as it is and shifted to the right (white dot area side) by 1/3 dot diameter is added.

The original black dots indicated by the dashed circles in the c-row 6-column and the f-row 7-column are hatched with a shift of 1/3 dot diameter to the left (black dot area side). It is corrected to the position shown. If this is done, there will be a portion where two black dots overlap in the black dot area, but the laser is turned on.
There are no problems, only the pulses of are continuous.

Finally, in the above-mentioned embodiment, the case where the dot correction section 7 which is the image data processing device according to the present invention is provided in the internal interface 5 connecting the controller 3 of the laser printer 2 and the engine driver 4 Although an example has been described, the dot correction unit 7 may be provided on the controller 3 side or the engine driver 4 side.

Furthermore, the present invention is not limited to laser printers, but various image forming apparatuses such as LED printers and other various optical printers, digital copying machines, plain paper facsimiles, and the like, which form images by expanding in a bit map form. The same can be applied to an image display device that displays the formed image.

[0149]

As described above, the image data processing apparatus according to the present invention can improve the image quality by correcting the jaggies of the contour lines of the image data developed in the bit map form and further improving the image quality. It is possible to set the resolution of the image data expanded in the map form, and perform image correction with different data for each resolution, or each image data expanded in the repeated bitmap form. It is possible to select whether or not to perform different image corrections for each. Therefore, it is possible to perform highly accurate image correction, improve the degree of freedom in selection, and improve versatility in creating image correction data.

Further, according to the inventions of claims 2 and 3, the total capacity of the memory relating to the image correction can be reduced without deteriorating the function. Further, claim 4
According to the invention, it is possible to replace the code information indicating the number of generations of the repeatedly generated bitmap image data with the code information in which the generation order is reversed according to an arbitrary condition. By doing so, it is possible to improve versatility regarding creation of image correction data when improving image quality .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a dot correction unit in FIG.

FIG. 2 is a block diagram showing a schematic configuration of a control system of a laser printer showing an embodiment of the present invention together with a host computer.

FIG. 3 is a schematic cross-sectional view showing a schematic structure of the mechanical section.

FIG. 4 is a perspective view showing an arrangement example of an optical system of the writing unit 26 as well.

5 is a block diagram showing a specific example of a FIFO memory 72 and a window 73 in FIG.

6 is a timing chart showing the operation of the FIFO memory 72 in FIG.

FIG. 7 is a timing chart showing another example of the same operation.

FIG. 8 is an explanatory diagram showing an example of the shape of the window shown in FIG. 5 and its core region.

9 is a block diagram showing a configuration example of a pattern recognition section 74 in FIG. 1 and respective output signals thereof.

10 is a block diagram showing a conventional configuration example of a memory block 75 in FIG.

FIG. 11 is a block diagram showing a first configuration example of the memory block 75 according to the present invention.

FIG. 12 is a block diagram showing a second configuration example of the memory block 75 according to the present invention.

FIG. 13 is a block diagram showing a third exemplary configuration of the memory block 75 according to the present invention.

14 is a diagram showing a comparison of total memory capacities required for the memory blocks shown in FIGS. 10 to 13;

FIG. 15 is a resolution 240d expanded in a bitmap form.
It is a figure which shows the dot structural example of the original image data of pi and 480 dpi.

16 is a diagram showing a dot configuration example of image data after the image data processing according to the present invention is applied to each original image data in FIG.

FIG. 17 is a diagram showing an example of original image data expanded into a bitmap and an example in which the image data is repeatedly generated three times.

FIG. 18 is an explanatory diagram when the generated image data is not corrected.

FIG. 19 is an explanatory diagram showing an example of a case in which the generated image data is similarly subjected to different correction processing each time it is generated.

FIG. 20 is a diagram showing an example of other original image data expanded in a bit map.

FIG. 21 is a diagram showing an example in which the image data is repeatedly generated three times and the correction process is not performed.

22 is a diagram showing an example of a case where the image data of FIG. 20 is corrected and the image generation counts are not replaced.

FIG. 23 is a diagram showing an example in which the image data of FIG. 20 is corrected and the image generation counts are exchanged.

24 is an explanatory diagram showing types of recognition patterns of line segments inclined by 45 ° in the core region in the window 73 shown in FIG.

FIG. 25 is an explanatory diagram similarly showing types of recognition patterns of horizontal or near-inclined line segments in the core region.

FIG. 26 is an explanatory diagram similarly showing types of recognition patterns of vertical or near-inclined line segments in the core region.

27 is an explanatory diagram of a right area, a left area, an upper area, and a lower area that are peripheral areas with respect to the core area 73C in the window 73 shown in FIG.

FIG. 28 is an explanatory diagram of each of the three sub-regions of the right region 73R and the left region 73L.

FIG. 29 is likewise an explanatory diagram of three sub-regions of each of the upper region 73U and the lower region 73D.

FIG. 30 is an explanatory diagram showing an example of sub-region selection based on the recognition result of a line segment pattern that is almost horizontal in the core region.

FIG. 31 is an explanatory diagram showing an example of selecting a sub region based on the recognition result of a line segment pattern close to vertical in the core region.

32 is an explanatory diagram showing an example of a line segment pattern in a window 73 for explaining an example of calculation of the inclination (GRADIENT) and the position (POSITION) by the inclination calculation unit 745 and the position calculation unit 746 shown in FIG. is there.

FIG. 33 is an explanatory diagram showing a state where each dot in FIG. 32 is shifted to the right by 1 bit.

34 is an explanatory diagram showing a state where each dot in FIG. 33 is further shifted to the right by 1 bit. FIG.

35 is an explanatory diagram showing a correction example of each dot forming a line segment that is nearly horizontal by the dot correction section 7 shown in FIG. 1 in association with the pulse width of laser ON.

FIG. 36 is an explanatory diagram showing an example of correction of each dot that constitutes a line segment that is also nearly vertical, in association with the phase of the laser-ON pulse.

FIG. 37 is an explanatory diagram showing various recognition results by the pattern recognition unit 74 shown in FIG. 1 for each target dot (the central dot of the core area 73C) in FIGS. 30 and 31.

[Explanation of symbols]

1: Host computer 2: Laser printer 3: Controller 4: Engine driver 5: Printer engine 6: Internal interface 7: Dot correction unit 11: Paper 15: Photosensitive drum 17: Development unit 24: Printed circuit board 26: Writing unit 70: Pattern recognition processing unit 71: Parallel / serial converter 72: FIFO memory 72a to 72g: Line buffer 73: Window 73a to 73g: shift register 73C: core area 73R: right area 73L: left area 73U: upper area 74: Pattern recognition unit 75: Memory block 76: Video data output unit 77: Timing control unit 78: Control signal generating means 79: Resolution setting means 81, 82: Selector 741: Core area recognition unit 742: Peripheral area recognition unit 743, 744: multiplexer 745: Inclination calculator 746: Position calculator 747: Discrimination unit 748: Gate 751: Table memory 752: Pattern memory

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Claims (4)

(57) [Claims] 1. A window for extracting data of each dot in a predetermined area centering on a target dot of image data developed in a bit map form, and image data extracted through the window,
A pattern for recognizing the line segment shape at the boundary between the black dot area and the white dot area of the image data and generating a plurality of bits of code information indicating the feature of the recognized line segment shape for the target dot. Recognition means, discrimination means for discriminating whether or not the target dot is a dot that needs to be corrected by using at least a part of the code information, and what resolution the image data developed in the bitmap form has It is possible to set whether the image data is image data, and a resolution setting unit that generates code information indicating what resolution each dot of the image data expanded by the setting is image data, Image data expanded in the same bitmap format as image data is repeatedly generated for an arbitrary timing signal an arbitrary number of times, and the generated image is generated. Image data generating means for generating code information indicating how many times the data has been generated, and selecting one of the code information generated by the image data generating means and the code information generated by the setting of the resolution setting means. Code information selecting means, the code information generated by the pattern recognizing means, and the code information selected by the code information selecting means are used as addresses for the dots determined to be corrected by the determining means. An image data processing apparatus comprising: a correction data output unit that reads out and outputs correction data stored in advance. 2. The image data processing device according to claim 1, wherein the correction data output means uses the code information generated by the pattern recognition means and the code information selected by the code information selection means as addresses. A table memory for reading out and outputting code information indicating a pattern of correction data stored in advance, and a pattern memory for reading out and outputting the correction data stored in advance using the code information output from the table memory as an address An image data processing device comprising: 3. The image data processing apparatus according to claim 1, wherein the correction data output means uses the code information generated by the pattern recognition means as an address to indicate code information indicating a pattern of correction data stored in advance. A table memory for reading and outputting, and a pattern memory for reading and outputting pre-stored correction data using the code information output from the table memory and the code information selected by the code information selecting means as addresses. An image data processing device comprising: 4. The image data processing apparatus according to claim 1, further comprising: code information indicating how many times each image data generated by the image data generating unit is generated. An image data processing device, characterized in that a means for replacing the generation order with code information is provided.