JPH06153110A - Sub sampling demodulation circuit - Google Patents

Abstract

PURPOSE:To provide the sub sampling demodulation circuit stable against a change in a delay due to a temperature change or a skew change in a clock pulse or the like with respect to the sub sampling demodulation circuit. CONSTITUTION:The sub sampling demodulation circuit is provided with a synchronization delay circuit delaying a sub sampling control signal synchronously with a clock pulse 3 being frequency division of a pulse input signal 8 by P periods of the pulse input signal 8 and outputs the resulting delay control signal 10, a control signal synchronization delay circuit 17 outputting a delay data signal 14 synchronously with the delay control signal 10 from a digital data signal 1 in plural bits synchronously with the clock pulse 3, and a data latch 15 outputs a sub sampling demodulation signal 16 synchronously with the pulse input signal 8 based on the delay data signal 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to sub-sampling demodulation of a sub-sampled digital video signal, and MUSE (Multiple Sub-Nyquist sampling enco
ding) It can be used for signal demodulation.

[0002]

2. Description of the Related Art A high-definition television signal has a transmission band of 20M.
There is more than Hz, and it is necessary to perform band compression by some method when transmitting using satellite broadcasting. The MUSE method has been proposed as a method of significantly compressing the band of high-definition television signals. When demodulating an image from this MUSE signal using a MUSE decoder or MUSE-NTSC converter, the receiving side does not perform sub-sampling demodulation performed for each frame, field, or scanning line performed on the transmission side. must not. An example of the demodulation method in the conventional sub-sampling demodulation circuit will be described below with reference to FIGS.

FIG. 5 shows an example of a conventional configuration of a subsampling demodulation circuit. The digital data signal 1 composed of a plurality of bits is synchronized with the clock pulse 3 obtained by dividing the pulse input signal 8, and the subsampling control signal 2 for determining the phase of subsampling is also synchronized with the clock pulse 3. ． In addition, the data latches 31, 33, 34, 3
6 latches input data at the rising edge of the input clock.

In the data latch 34, the first delay phase control signal 4 which is the exclusive OR output of the sub-sampling control signal 2 and the clock pulse 3 is latched by the inverted clock signal 5 of the pulse input signal 8 and the second delay Obtain the phase control signal 7. In the data latch 36, the second delay phase control signal 7 is latched by the clock pulse 35 to obtain the sub sampling control clock 37. On the other hand, the delay circuit 29 delays the digital data signal 1 to obtain the delayed data signal 30. The data latch 31 latches the delayed data signal 30 with the sub-sampling control clock 37 to obtain the delayed data signal 32.

Here, the clock pulse 35 is phased by the propagation delay of the data latch 36 so that the rising change point of the sub-sampling control clock 37 coincides with the rising change point of the pulse input signal 8. We will use the advanced clock pulse. Also,
Regarding the delay amount of the delay circuit 29, the delay data signal 30
Is delayed from the rising change point of the sub-sampling control clock 37 by the setup time of the data latch 31.

Further, in the data latch 33, the delayed data signal 32 can be latched by the pulse input signal 8 and the sub-sampling demodulation signal 16 synchronized with the pulse input signal 8 can be obtained as an output.

Regarding the operating principle of the circuit configured as described above, FIG. 6 shows a time chart for each signal.

[0008]

However, in the above-mentioned configuration, the phase of the digital data signal input by the delay circuit is delayed in an analog and asynchronous manner in order to prevent a latch error, and the sub-sampling delay signal is added. Regarding the above, the clock signal used for the data latch must be advanced in phase in relation to the change point of the digital data signal.

Therefore, the delay amount of the delay element must be determined in consideration of the change of the delay amount due to the temperature change of the delay element and the change of the skew of the clock pulse.
Difficulty occurred when performing SI conversion.

In order to solve the above problems, the present invention provides a sub-sampling demodulation circuit which has a relatively easy circuit configuration and is stable against changes in delay amount due to temperature changes, changes in skew of clock pulses, and the like. With the goal.

[0011]

In order to solve the above problems, a sub-sampling demodulation circuit of the present invention provides a sub-sampling control signal synchronized with a clock pulse obtained by dividing a pulse input signal by a P cycle with respect to the pulse signal. A synchronous delay circuit that delays by a minute and outputs a delay control signal; and a control signal synchronous delay circuit that outputs a delayed data signal synchronized with the delay control signal from a digital data signal composed of a plurality of bits synchronized with the clock pulse A subsampling demodulation circuit that outputs a subsampling demodulation signal synchronized with the pulse input signal from the delayed data signal by a data latch.

According to a second aspect of the present invention, a first delay is obtained by delaying a digital data signal composed of a plurality of bits synchronized with a clock pulse obtained by dividing the pulse input signal by Q cycles with respect to the clock pulse. The data signal, a data signal synchronous delay circuit for outputting a second delayed data signal obtained by further delaying the first delayed data signal by a half cycle with respect to a clock pulse, and the sub-sampling control signal synchronized with the clock pulse, A selection circuit for selecting either the delayed data signal 1 or the second delayed data signal and outputting a control synchronization signal, and a subsampling demodulation signal synchronized with the pulse input signal by a data latch from the control synchronization signal. The sub-sampling demodulation circuit is characterized by

According to a third aspect of the invention, a first delay is obtained by delaying a digital data signal composed of a plurality of bits synchronized with a clock pulse obtained by dividing the pulse input signal by Q cycles with respect to the clock pulse. The data signal, the data signal synchronous delay circuit for outputting the second delayed data signal obtained by further delaying the first delayed data signal by a half cycle with respect to the clock pulse, and the sub-sampling control signal synchronized with the clock pulse, A selection circuit for selecting either the first delayed data signal or the second delayed data signal and outputting the first control synchronization data signal, and an inverted clock of the pulse input signal from the first control synchronization data signal. A first data latch for outputting a second control synchronization data signal synchronized with the signal, and the second control synchronization data signal. The second data latch from a sub-sampling the demodulation circuits and outputting a sub-sampled demodulated signal synchronized with the pulse input signal.

[0014]

With the above-described structure, the present invention can provide a sub-sampling demodulation circuit which is stable against changes in delay amount due to temperature changes, changes in skew of clock pulses, and the like. That is, by synchronizing the pulse input signal or the clock pulse obtained by dividing the pulse input signal with the subsampling control signal or the digital data signal, the subsampling demodulation can be stably operated, and It can be realized with a relatively easy circuit configuration.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a subsampling demodulation circuit will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a sub-sampling demodulation circuit according to the first embodiment of the present invention. Further, the same numbers used in FIGS. 1, 2, 3, 4, 5, and 6 indicate the same things, and the data latches in the figures latch the input data at the rising edge of the clock. And

An exclusive OR of the sub-sampling control signal 2 and the clock pulse 3 which are synchronized with the clock pulse 3 obtained by dividing a certain pulse input signal 8 is calculated, the first delay phase control signal 4 is generated, and the data latch is performed. At 6, the first delay phase control signal 4 is latched by the inverted clock signal 5 of the pulse input signal 8, and the second delay phase control signal 7 is obtained. In the data latch 9, the second delay phase control signal 7 is latched by the pulse input signal 8 and the delay control signal 10 is output.

In the data latch 11, the digital data signal 1 composed of a plurality of bits synchronized with the clock pulse 3 is latched by the inverted clock signal 5 to obtain the delayed data signal 12. In the data latch 13, the delayed data signal 12 is latched by the pulse input signal 8 to obtain the delayed data signal 14.

Further, in the data latch 15, the delayed data signal 14 is latched by the pulse input signal 8 so that the sub-sampling demodulation signal 16 can be obtained.

According to the first embodiment thus constructed, it is possible to provide a sub-sampling demodulation circuit which is stable against changes in the delay amount due to changes in temperature, changes in skew of clock pulses, and the like. . That is, by synchronizing the pulse input signal or the clock pulse obtained by dividing the pulse input signal with the subsampling control signal or the digital data signal, the subsampling demodulation can be stably operated, and It can be realized with a relatively easy circuit configuration.

Regarding the operating principle of the circuit configured as described above, FIG. 4 shows a time chart for each signal.

Next, a second embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. The digital data signal 1 composed of a plurality of bits synchronized with the clock pulse 3 obtained by dividing the pulse input signal 8 is latched by the clock pulse 3 in the data latch 19 to obtain the first delayed data signal 22. Further, the digital data signal 1 is latched in the data latch 21 by the inverted clock 20 of the clock pulse 3 to obtain the second delayed data signal 23.

The sub-sampling control signal 2 synchronized with the clock pulse 3 is input to the selection circuit 24 by inputting the first delayed data signal 22 and the second delayed data signal 23.
Is 0, the first delayed data signal 22 is selected, and when 1 is selected, the first delayed data signal 22 is selected and used as the control synchronization signal 25. Further, in the data latch 28, the sub-sampling demodulation signal 16 can be obtained by latching the control synchronization signal 25 with the pulse input signal 8.

According to the second embodiment thus constructed, it is possible to provide a stable sub-sampling demodulation circuit against changes in the delay amount due to changes in temperature, changes in skew of clock pulses, and the like. . That is, by demodulating the sub-sampling control signal and the digital data signal in synchronization with the pulse input signal or the clock pulse obtained by dividing the pulse input signal, the sub-sampling demodulation can be stably operated, and The circuit structure can be realized more easily than that of the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. Since the signal processing up to the selection circuit 24 is the same as that of the second embodiment of the present invention, it will be omitted. The control synchronization signal 25 selected by the sub-sampling control signal 2 in the selection circuit 24 is latched by the inverted clock signal 5 in the data latch 27 to obtain the delay control synchronization data signal 26. Further, the delay control synchronizing data signal 26 can be latched by the pulse input signal 8 in the data latch 28 to obtain the sub-sampling demodulation signal 16.

According to the third embodiment thus constructed, it is possible to provide a stable sub-sampling demodulation circuit against changes in the delay amount due to changes in temperature, changes in skew of clock pulses, and the like. . That is, by delaying the sub-sampling control signal or the digital data signal in synchronization with the pulse input signal or the clock pulse obtained by dividing the pulse input signal, the sub-sampling demodulation can be operated stably, and As compared with the second embodiment, by adding the data latch 27, it is possible to provide a circuit that is relatively easy and more stable against changes in the delay amount of the selection circuit due to temperature changes.

[0027]

As described above, according to the present invention, by delaying the input digital data signal and the sub-sampling control signal in synchronization with the synchronized clock pulse, the delay amount changes due to temperature changes, It is possible to provide a sub-sampling demodulation circuit that is stable against changes in the skew of clock pulses. Moreover, it can be realized with a relatively easy circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a sub-sampling demodulation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a sub-sampling demodulation circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a sub-sampling demodulation circuit according to a third embodiment of the present invention.

FIG. 4 is a time chart used for explaining the first embodiment of the present invention.

FIG. 5 is an example of a conventional sub-sampling demodulation circuit.

FIG. 6 is a time chart used for explaining an example of a conventional sub-sampling demodulation circuit.

[Explanation of symbols]

 1 Digital Data Signal 2 Subsampling Control Signal 3 Clock Pulse 8 Pulse Input Signal 10 Delay Control Signal 14 Delay Data Signal 15 Data Latch 16 Subsampling Demodulation Signal 17 Control Signal Synchronous Delay Circuit 18 Synchronous Delay Circuit

Claims (3)

[Claims] 1. A synchronous delay circuit for delaying a sub-sampling control signal synchronized with a clock pulse obtained by dividing a pulse input signal by P periods with respect to the pulse input signal, and outputting a delay control signal, and a synchronous delay circuit synchronized with the clock pulse. A control signal synchronization delay circuit for outputting a delayed data signal synchronized with the delay control signal from a digital data signal composed of a plurality of bits, and a sub-sampling demodulation signal synchronized with the pulse input signal by a data latch from the delayed data signal. A sub-sampling demodulation circuit characterized by outputting. 2. A first delay data signal obtained by delaying a digital data signal composed of a plurality of bits in synchronization with a clock pulse obtained by dividing a pulse input signal by Q cycles with respect to the clock pulse, and the first delay data thereof. A data signal synchronous delay circuit for outputting a second delayed data signal obtained by further delaying the signal by a half cycle with respect to the clock pulse;
A selection circuit that selects either the first delayed data signal or the second delayed data signal by a sub-sampling control signal synchronized with the clock pulse and outputs a control synchronization signal, and a data latch from the control synchronization signal. A sub-sampling demodulation circuit, which outputs a sub-sampling demodulation signal synchronized with the pulse input signal. 3. A first delay data signal obtained by delaying a digital data signal composed of a plurality of bits synchronized with a clock pulse obtained by dividing a pulse input signal by Q cycles with respect to the clock pulse, and the first delay data thereof. A data signal synchronous delay circuit for outputting a second delayed data signal obtained by further delaying the signal by a half cycle with respect to the clock pulse;
A selection circuit for selecting either the first delay data signal or the second delay data signal by a sub-sampling control signal synchronized with the clock pulse and outputting a first control synchronization data signal; A first data latch that outputs a second control synchronization data signal that is synchronized with the inverted clock signal of the pulse input signal from the control synchronization data signal, and the pulse that is generated by the second data latch from the second control synchronization data signal. A sub-sampling demodulation circuit, which outputs a sub-sampling demodulation signal synchronized with an input signal.