JPH06151810A - Photoelectric-semiconductor integrated circuit, semiconductor device and their manufacture - Google Patents

Abstract

PURPOSE:To provide a photoelectric' integrated circuit device capable of being manufactured at low cost in a simple process in one-time crystal growth regarding the photoelectric integrated circuit device, in which a laser diode and a transistor are integrated on the same compound semiconductor substrate. CONSTITUTION:A photoelectric-semiconductor integrated device has one conductivity type compound semiconductor substrate 41 with a first surface consisting of a face (100) or a face close to the face (100) and a second surface composed of a face (311) A or a face close to the face (311) A, a semiconductor laser being formed to the upper section of the second face and having at least an active layer 47 and an opposite conductivity type clad layer 48 on the active layer 47, and the opposite conductivity type clad layer 48 as a collector layer extending from the upper section of the second face to the upper section of the first face. The device is constituted while including a bipolar transistor with one conductivity type base layer 49 shaped onto the clad layer 48 in the upper section of the second face and the upper section of the first face, reverse conductivity type emitter layers 50a, 50c formed onto the base layer 49 in the upper section of the first face, and one conductivity type base leading-out layer 50b formed onto the base layer 49 in the upper section of the second 12 face.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a photoelectric-semiconductor integrated device,
More particularly, the present invention relates to a photoelectric-semiconductor integrated device in which a laser diode and a transistor are integrated on the same compound semiconductor substrate, a semiconductor device, and manufacturing methods thereof.

[0002]

2. Description of the Related Art In recent years, visible light semiconductor lasers are expected to be applied not only to compact discs but also to POS, optical disc devices, laser printers and the like.

When using a semiconductor laser in such an application device, it is required to reduce the cost and improve the performance of the semiconductor laser. As a countermeasure, it is conceivable to manufacture a semiconductor laser by one crystal growth and reduce the price of the semiconductor laser itself, and as a further countermeasure, integrate the semiconductor laser and the active circuit on the same compound semiconductor substrate. What to do, etc. are possible.

As the first countermeasure, there is a technique that utilizes the plane orientation dependence of the rate of incorporation of a dopant that determines the conductivity type into the compound semiconductor substrate. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor laser using such a technique.

First, a p-type GaAs substrate (hereinafter referred to as "p") having a plane having an off angle of 6 degrees with respect to the (111) A plane.
-It is called a GaAs substrate. ), A strip-shaped resist mask extending in the (011) direction is formed.

Next, based on the resist mask, hydrofluoric acid +
The p-GaAs substrate is etched with a hydrogen peroxide solution. As a result, a slope having the (311) A plane is formed along one side end of the resist mask, and further along the terminal end of the slope, at a position lower than the surface covered with the resist mask by the height of the slope, A plane is formed which is substantially parallel to the surface covered with the resist mask and has an off-angle of about 20 degrees with respect to the (111) A plane. Although another slope and a flat surface are formed at the other end of the resist mask, it is not shown.

Next, zinc which is a p-type impurity (hereinafter referred to as Zn
Called. ) Is grown while GaAs is doped, and p−
A GaAs buffer layer is formed. Then, GaInP is grown while doping with Zn to form a p-GaInP buffer layer.

Next, selenium (hereinafter, S
e. ) And Zn, which is a p-type impurity, are doped to grow AlGaInP. At this time, due to the plane orientation dependence of the incorporation rate of the dopant, Zn is formed in the slope portion.
Is taken in, and Se is taken in a lot in the plane, so that the slope becomes p-type and the plane becomes n-type. As a result, the p-AlGaInP layer which is a part of the current channel layer is formed on the slope portion, and the n-AlGaInP clad layer / current block layer is formed on the flat portions on both sides of the slope portion.

Then, while doping with Zn, AlGaI
Then, nP is grown to form the p-AlGaInP cladding layer 5. The p-AlGaInP layer on the sloped surface becomes a part of the current channel layer.

Next, AlGaInP is grown while doping Se which is an n-type impurity and Zn which is a p-type impurity. At this time, a large amount of Zn is taken into the slope portion and a large amount of Se is taken into the flat surface portion due to the plane orientation dependence of the incorporation rate of the dopant.
It becomes a mold, and the plane part becomes n-type. As a result, the p-AlGaInP layer which is a part of the current channel layer is formed on the slope portion, and the n-AlGaInP cladding layer / current block layer 6 is formed on the flat portions on both sides of the slope portion. .

Then, GaInP is grown without a dopant to form a GaInP active layer 7 on the slope. next,
AlGaInP is grown while doping Si. At this time, since Si has no dependence on the plane orientation of the incorporation rate, the AlGaInP layer on the sloped surface also has a flat surface AlGaI.
Both nP layers also contain Si of similar concentration, and n-
The AlGaInP clad layer 8 is formed.

Then, while doping Si, GaInP
Are grown to form an n-GaInP buffer layer 9. Next, GaAs is grown while doping Si, and n-Ga
The As contact layer 10 is formed.

Next, an n-electrode made of AuGe / Au film is formed on the n-GaAs contact layer 10. Then, a p-electrode made of an AuZn / Au film is formed on the surface of the p-GaAs substrate 1 to complete the semiconductor laser.

As described above, a semiconductor laser can be produced by a single crystal growth by the technique utilizing the plane orientation dependence of the rate of incorporation of the dopant into the compound semiconductor substrate.

Next, the second measure will be described. Figure 6
(A) is a sectional view of an optoelectronic integrated circuit device in which an FET and a semiconductor laser are integrated on one chip according to a conventional example. 21 is a compound semiconductor substrate made of Si-InP, 2
2 is a compound semiconductor layer formed on the compound semiconductor substrate 21 to be a channel layer, a source layer and a drain layer of the FET, and 23a and 23b are formed on the compound semiconductor layer 22.
Connection between contact layer 24a and source layer and contact layer
Connection layers made of a compound semiconductor used for connecting 24b and the drain layer, 24a and 24b are contact layers on the connection layers 23a and 23b, and 31 is the connection layers 23a and 23b and the contact layer 24.
The gate electrode formed on the channel layer exposed by etching the compound semiconductor layer for forming a and 24b is formed by the lift-off method, and the connection portion between the channel layer and the gate electrode is a Schottky junction. ing.
32 is a source electrode connected to the contact layer 24a, 33
Is a drain electrode connected to the contact layer 24b.

Further, 25 is a contact layer 24 on the drain side.
b is an active layer formed on b, 26 is a compound semiconductor layer covering the active layer 25, 27 is a high resistance layer grown on the undercut portions of the compound semiconductor layers 26 on both sides of the active layer 25, This is to concentrate the current flowing in the layer 26 in the active layer 25. Reference numeral 28 is a silicon oxide film that covers the compound semiconductor layer 26, and an opening is formed on the compound semiconductor layer 26, and an electrode 29 is connected thereto. Reference numeral 30 is a wiring connected to the electrode 29. An equivalent circuit of the optoelectronic integrated circuit device is shown in FIG. 6 (b).

[0017]

However, as described above, when a semiconductor laser alone is used, a laser device can be manufactured inexpensively by a single crystal growth and a simple process. In the case of manufacturing an optoelectronic integrated circuit device in which a transistor and a transistor are integrated on one chip, in order to connect the gate electrode 31 to the compound semiconductor layer 22, the connection layers 23a and 23b and the contact layers 24a and 24b are formed. It is necessary to etch the compound semiconductor layer, and further it is necessary to pattern the compound semiconductor layer to form the compound semiconductor layer 26 on the semiconductor laser side.

Therefore, the step of growing the compound semiconductor layer is required twice and a complicated electrode process is required. Therefore, there is a problem that the process becomes complicated and cannot be manufactured at low cost.

The present invention was created in view of the problems of the conventional example, and an optoelectronic integrated circuit device which can be manufactured at a low cost by a single crystal growth and a simple process, and its manufacture. The purpose is to provide a method.

[0020]

The above-mentioned problems are as follows.
One conductivity type compound semiconductor substrate having a first surface composed of a (100) surface or a surface near the (100) surface and a second surface composed of a (311) A surface or a surface near the (311) A surface And a semiconductor laser formed above the second surface and having at least an active layer and a clad layer of opposite conductivity type on the active layer, and extending from above the second surface to above the first surface. A clad layer of opposite conductivity type as a collector layer, a base layer of one conductivity type formed on the clad layers above the first surface and above the second surface, and a base above the first surface Opto-semiconductor integrated device having a bipolar transistor having an emitter layer of opposite conductivity type formed on a layer and a base extraction layer of one conductivity type formed on a base layer above the second surface. Achieved by
Secondly, one conductivity type having a first surface composed of a (100) surface or a surface near the (100) surface and a second surface composed of a surface near the (311) A surface or a (311) A surface A compound semiconductor substrate, a cladding layer of the opposite conductivity type as a collector layer extending from above the first surface to above the second surface, and a cladding above the first surface and above the second surface. A base layer of one conductivity type formed on the layer, an emitter layer of opposite conductivity type formed on the base layer above the first surface, and a base layer above the second surface. And a bipolar transistor having a base conduction layer of one conductivity type formed, and thirdly,
One conductivity type compound semiconductor substrate having a first surface composed of a (100) surface or a surface near the (100) surface and a second surface composed of a (311) A surface or a surface near the (311) A surface A plurality of compound semiconductor layers are laminated thereon, at least a current channel layer and an active layer of a semiconductor laser on the current channel layer are formed above the second surface, and the current layer is formed above the first surface. The current block layer is in contact with the current channel layer on the side of the channel layer, and the undoped compound semiconductor layer is in contact with the active layer on the side of the active layer on the current block layer. Growing a first compound semiconductor while doping a conductivity type impurity, and forming a first cladding layer / collector layer of opposite conductivity type on the active layer and the compound semiconductor layer; Don't dope And growing a second compound semiconductor to form a second clad layer / base layer of one conductivity type on the first clad layer / collector layer, and doping impurities of opposite conductivity type and one conductivity type impurity. While growing a third compound semiconductor, the second clad layer /
A first base extraction layer of one conductivity type is formed on the base layer, and a third clad layer / emitter layer of opposite conductivity type is formed on the second cladding layer / base layer of the first surface portion. And a second method according to the third aspect of the invention.
Forming a first base extraction layer on the second clad layer / base layer of the first surface part and a third clad layer / emitter layer on the second clad layer / base layer of the first surface part. Then, a fourth compound semiconductor is grown while doping an impurity of opposite conductivity type and an impurity of one conductivity type to form a second base extraction layer of one conductivity type on the first base extraction layer of the second surface portion. And a step of forming an emitter extraction layer of opposite conductivity type on the third cladding layer / emitter layer of the first surface portion, and a fifth compound semiconductor while doping impurities of opposite conductivity type and impurities of one conductivity type. To form a base contact layer of one conductivity type on the second base extraction layer of the first surface portion and an emitter contact layer of opposite conductivity type on the emitter extraction layer of the first surface portion. Work A step of forming a first electrode on the emitter contact layer and a second electrode on the base contact layer, a boundary portion between the emitter contact layer and the base contact layer, and the emitter Photoelectric-semiconductor integrated device including a step of etching / removing a boundary portion between the extraction layer and the base extraction layer, and further etching a boundary portion between the sixth cladding layer / emitter layer and the base extraction layer halfway A fifth aspect of the present invention is achieved by a method of manufacturing a device, and fifthly, a first surface composed of a (100) plane or a plane near the (100) plane, and (311)
A plurality of compound semiconductor layers are laminated on a compound semiconductor substrate of one conductivity type having an A surface or a second surface composed of a surface near the (311) A surface, and at least a current channel layer is provided above the second surface. And at least a current blocking layer in contact with the current channel layer is formed above the first surface and lateral to the current channel layer, the first compound being doped with an impurity of opposite conductivity type. Growing a semiconductor and forming a first cladding layer / collector layer of opposite conductivity type on the current channel layer and the current block layer; and growing a second compound semiconductor while doping an impurity of one conductivity type, A step of forming a second clad layer / base layer of one conductivity type on the first clad layer / collector layer, and a third compound semiconductor while doping impurities of opposite conductivity type and impurities of one conductivity type Is grown to form a first base extraction layer of one conductivity type on the second cladding layer / base layer of the second surface portion, and on the second cladding layer / base layer of the first surface portion. And a step of forming a third cladding layer / emitter layer of opposite conductivity type.

[0021]

According to the photoelectric-semiconductor integrated device and the method of manufacturing the same of the present invention, different conductivity can be obtained in one compound semiconductor layer by the technique utilizing the plane orientation dependence of the rate of incorporation of the dopant into the compound semiconductor substrate. Since the mold region can be formed at the same time, by switching the source appropriately,
With a single crystal growth, a plurality of compound semiconductor layers in which different conductivity type regions coexist in one layer are laminated to form a photoelectric-semiconductor integrated device in which a semiconductor laser and a control bipolar transistor are integrated. .

Further, a base extraction layer is formed on the slope,
Since the emitter layer is formed on the flat surface portion adjacent to the inclined surface portion, the traveling distance of the carriers moving in the base layer can be reduced. This enables high-speed operation of the photoelectric-semiconductor integrated device.

By forming a current blocking layer composed of a layer of one conductivity type and a layer of opposite conductivity type sandwiching the layer of one conductivity type on both sides of the current channel layer, the current blocking layer is formed by facing pn junctions. It is possible to limit the current flowing through the device to concentrate the drive current in the current channel layer, and the drive current can be effectively used to drive the semiconductor laser. Further, the compound semiconductor substrate surface can be effectively used by connecting the semiconductor laser and forming two parallel bipolar transistors. Further, the bandgap of the emitter layer is larger than that of the base layer, for example, Al _x Ga as the emitter layer and the collector layer.
_The current amplification factor can be increased by using _1-x As and using GaAs as the base layer so that the structure of the bipolar transistor becomes an HBT (heterojunction bipolar transistor) structure. A semiconductor laser can be driven.

Further, according to the semiconductor device and the method of manufacturing the same of the present invention, different conductivity type regions are formed in one compound semiconductor layer by the technique utilizing the plane orientation dependency of the rate of incorporation of the dopant into the compound semiconductor substrate. Since it is possible to simultaneously form a plurality of compound semiconductor layers in which different conductivity type regions are mixed in one layer by one-time crystal growth, the first conductivity type having the opposite conductivity type can be simultaneously formed. A first conductivity type first base extraction layer is formed on the second conductivity type second clad layer / base layer on the second surface part clad layer / collector layer of A bipolar transistor can be prepared by forming a third cladding layer / emitter layer of the opposite conductivity type on the second cladding layer / base layer of the one conductivity type.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a method of manufacturing an optoelectronic integrated circuit device according to an embodiment of the present invention.

First, the off angle to the (111) A plane is about 6
It extends in the (011) direction on a p-type (one conductivity type) GaAs substrate (hereinafter referred to as a p-GaAs substrate (compound semiconductor substrate)) 41 having a flat surface (first surface) that is inclined. A band-shaped resist mask (not shown) having a width of 150 μm is formed with a pitch of 300 μm.

Then, based on the resist mask, hydrofluoric acid +
The p-GaAs substrate 41 is etched by about 1 μm with a hydrogen peroxide solution. As a result, a slope having a substantially (311) A surface (second surface) is formed along one end of the resist mask, and the slope from the surface covered with the resist mask to the slope along the end of the slope. It is almost parallel to the surface covered by the resist mask, and
11) A flat surface (first surface) having an off angle to the surface A of about 20 degrees is formed. Although another slope and plane are formed at the other end of the resist mask,
Not shown.

Next, by the MOVPE method (organic metal vapor phase epitaxial method), the crystal growth is performed once while sequentially switching the source, and has a slope portion (second surface) and a flat surface portion (first surface). The following compound semiconductor layers are sequentially formed on the p-GaAs substrate 41.

That is, Ga is doped with zinc (hereinafter referred to as Zn) which is a p-type impurity (one conductivity type impurity).
As is grown to form a p-GaAs buffer layer 42 having a film thickness of about 1 μm.

Next, while doping with Zn, Ga _0.5 In _0.5
P is grown to form a p-GaInP buffer layer 43 having a film thickness of about 0.1 μm on the p-GaAs buffer layer 42 on the inclined surface portion and both flat surface portions.

Next, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is grown while doping selenium (hereinafter referred to as Se) which is an n-type impurity (opposite conductivity type impurity) and Zn which is a p-type impurity. . At this time, due to the plane orientation dependency of the incorporation rate of the dopant, as shown in FIG. 3A, a large amount of Zn is incorporated into the AlGaInP layer on the sloped surface which is the (311) A plane, and as shown in FIG. As shown in b), the AlGaInP layer in the plane portion near the (100) A plane has S
Since a large amount of e is taken in, AlG formed on the slope
The aInP layer becomes p-type, and the AlGa formed on the plane portion
The InP layer becomes n-type. As a result, p-Ga in the slope portion
A p-AlGaInP layer, which is a part of the current channel layer 55, is formed on the InP buffer layer 43, and a film thickness of about 0. A 3 μm n-AlGaInP cladding layer / current blocking layer 44 is formed.

Next, while doping with Zn (Al _0.7 Ga
_0.3 ) _0.5 In _0.5 P is grown and p-AlGaInP on the slope is grown.
P-A with a film thickness of about 0.5 μm on both the layer and the n-AlGaInP clad layer / current blocking layer 44 on both planes
The lGaInP clad layer 45 is formed. The p-AlGaInP layer on the sloped surface becomes a part of the current channel layer 55.

Next, while doping with Zn is Se and p-type impurity is an n-type impurity (Al _{0. 7} Ga _0.3) grown _0.5 In _0.5 P. At this time, a large amount of Zn is taken into the AlGaInP layer in the slope portion and a large amount of Se is taken into the AlGaInP layer in the flat portion due to the plane orientation dependence of the incorporation rate of the dopant, so that the AlGaInP layer in the slope portion has p
The AlGaInP layer in the plane portion becomes n-type. As a result, a p-AlGaInP layer, which is a part of the current channel layer 55, is formed on the p-AlGaInP layer on the slope portion, and p-AlGa on both planes sandwiching the slope portion is formed.
On the InP clad layer 45, n-Al with a film thickness of about 500Å
The GaInP cladding layer / current blocking layer 46 is formed.

Then Ga _0.45 In _0.55 P without dopant
And a film thickness of about 3 on the p-AlGaInP layer on the slope.
A GaInP active layer 47 of 00Å is formed. In addition, the n-AlGaInP clad layer / current blocking layer 4 in the plane portion
An undoped GaInP layer (compound semiconductor layer) on 6 as well
47a is formed.

Next, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P (first compound semiconductor) is grown while doping Si which is an n-type impurity (opposite conductivity type impurity). At this time, as shown in FIG. 4, since Si has no dependence on the plane orientation of the incorporation rate, the AlGaInP layer on the sloped surface also has a flat surface AlGaI.
The nP layer also contains Si of approximately the same concentration, and is on the GaInP active layer 47 in the slope portion and the GaInP layer in the flat portion.
N-AlGaInP clad layer / collector layer (first clad layer / collector layer) 4 having a thickness of about 0.8 μm on 47a
8 is formed.

Next, while doping with magnesium (hereinafter referred to as Mg) which is a p-type impurity (one conductivity type impurity), (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P (second compound semiconductor)
To grow. At this time, as shown in FIG.
Has a plane orientation dependence of the incorporation rate, but since it is a single dopant, a high concentration of Mg is contained in the AlGaInP layer on the slope and a low concentration of M is contained in the AlGaInP layer on the plane.
g of p-AlGaI having a thickness of about 300Å on the n-AlGaInP cladding layer / collector layer 48.
An nP clad layer / base layer (second clad layer / base layer) 49 is formed. Thereby, n-AlGaIn
A collector / base pn junction is formed at the connection between the P clad layer / collector layer 48 and the p-AlGaInP clad layer / base layer 49.

Next, while doping with Zn is Se and p-type impurity is an n-type impurity _{(Al 0. 7 Ga 0.3) 0.5} In 0.5 P
(Third compound semiconductor) is grown. At this time, due to the plane orientation dependency of the incorporation rate of the dopant,
A large amount of Zn is taken into the lGaInP layer, and
Since a large amount of Se is taken into the lGaInP layer, the AlGaInP layer on the slope becomes p-type and the AlGaInP layer on the flat surface becomes
The InP layer becomes n-type. As a result, the p-Al
P-AlG is formed on the GaInP clad layer / base layer 49.
aInP base extraction layer (first base extraction layer) 50b
And the n-AlGaInP clad layer / emitter layer (third clad layer / third clad layer / third clad layer / Emitter layers) 50a and 50c are formed. As a result, the emitter / base pn is formed at the connection between the n-AlGaInP clad layer / emitter layers 50a and 50c and the p-AlGaInP clad layer / base layer 49.
A bond is formed.

[0038] Then, to grow while doping with Zn is Se and p-type impurity is an n-type impurity Ga _{0. 5} In _0.5 P (fourth compound semiconductor). At this time, as shown in FIG.
As shown in (b), due to the plane orientation dependence of the incorporation rate of the dopant, a large amount of Zn is incorporated in the GaInP in the slope portion and a large amount of Se is incorporated in the GaInP in the flat portion, so that the GaInP layer in the slope portion is It becomes p-type, and the GaInP layer in the plane becomes n-type. As a result, the p-
A film thickness of about 0.1 is formed on the AlGaInP base extraction layer 50b.
A μ-μm p-GaInP base extraction layer (second base extraction layer) 51b is formed, and the film thickness is about 50 nm on the n-AlGaInP clad layer / emitter layers 50a, 50c on both sides of the inclined surface. 0.1 μm n-GaInP
Emitter extraction layers (emitter extraction layers) 51a and 51c are formed.

Next, GaAs is grown while doping Se which is an n-type impurity and Zn which is a p-type impurity. At this time, due to the plane orientation dependence of the incorporation rate of the dopant, a large amount of Zn is incorporated in the GaAs in the slope portion and a large amount of Se is incorporated in the GaAs in the flat portion, so that the GaAs layer in the slope portion becomes p-type. , The GaAs layer in the plane portion becomes n-type. As a result, a p-GaAs base contact layer (base contact layer) 52b having a film thickness of about 2 μm is formed on the p-GaInP base extraction layer 50b on the inclined surface portion, and n on both sides of the inclined surface portion is sandwiched. -GaInP
An n-thickness of about 2 μm is formed on the emitter extraction layers 51a and 51c.
GaAs emitter contact layers (emitter contact layers) 52a and 52c are formed. This completes one crystal growth.

Next, the emitter electrodes 53a and 53c made of AuGe / Au films are formed on the n-GaAs emitter contact layers 52a and 52c, and the base electrode 53b made of AuZn / Au film is formed on the p-GaAs base contact layer 52b. To form.

Next, an n-GaAs emitter contact layer
52a, 52c / p-GaAs base contact layer 52b, and n-GaInP emitter extraction layers 51a, 51c
/ P-GaInP base extraction layer 50b, the boundary portion is etched and removed, and the n-AlGaInP clad layer /
The boundaries between the emitter layers 50a and 50c / p-AlGaInP base extraction layer 50b are etched halfway. As a result, the base is physically and electrically separated from the emitter.

Then, Au is formed on the surface of the p-GaAs substrate 41.
When the p-contact electrode 54 made of a Zn / Au film is formed, an optoelectronic integrated circuit device in which a semiconductor laser and a control bipolar transistor are integrated is completed. The equivalent circuit is shown in FIG.

The case of operating the optoelectronic integrated circuit device thus manufactured will be described with reference to FIG. First, a negative voltage is applied to the emitter electrodes 53a and 53c, and a positive voltage is applied to the p-contact electrode 54. At this time, since the base voltage is not applied, the control transistor does not operate and the semiconductor laser also does not operate.

When a positive voltage is applied to the base electrode 53b when necessary in such a state, a base current flows between the emitter and the base, and at the collector side, that is, p-
A drive current corresponding to the base current is introduced from the contact electrode 54 side. At this time, the driving current is n-AlGaI.
The current tends to flow toward the nP clad layer / emitter layers 50a and 50c, but due to the current limitation in the current block layer, the drive current concentrates in the adjacent current channel layer 55.
That is, the driving current is GaInP above the current channel layer 55.
Since the current flows intensively in the active layer 47, the drive current can be effectively used. As a result, the semiconductor laser operates to generate laser light, and the laser light generated by the base current can be modulated.

Further, the resistivity of the semiconductor laser is changed by passing a current, but since the differential resistance between the emitter and the collector of the NPN bipolar transistor is large, the semiconductor laser is positively fed back and is not destroyed. . Therefore, the semiconductor laser can be driven by an inexpensive power supply.

As described above, according to the method of manufacturing an optoelectronic integrated circuit device of the embodiment of the present invention, one layer of a layer is formed by the technique utilizing the plane orientation dependence of the incorporation rate of the dopant into the compound semiconductor substrate. Since different conductivity type regions can be simultaneously formed in the compound semiconductor layer, a plurality of compound semiconductor layers in which different conductivity type regions are mixed in one layer can be stacked by one crystal growth by appropriately switching the sources. An optoelectronic integrated circuit device in which a semiconductor laser and a controlling bipolar transistor are integrated can be produced.

Since the current block layers having the pn junctions facing each other are formed on both sides of the current channel layer, the drive current can be effectively used to drive the semiconductor laser.

Further, a base extraction layer is formed on the slope portion,
Since the emitter layer is formed on the flat surface portion adjacent to the inclined surface portion, the traveling distance of the carriers moving in the base layer can be reduced. This enables high speed operation of the optoelectronic integrated circuit device.

In the above embodiment, two parallel bipolar transistors connected to the semiconductor laser are formed, but one bipolar transistor may be formed.

Although AlGaInP is used as the emitter layer, the base layer and the collector layer of the bipolar transistor, for example, Al _x Ga is used as the emitter layer and the collector layer.
By using _1-x As and using GaAs as the base layer, the band gap of the emitter layer may be made larger than the band gap of the base layer to form an HBT (heterojunction bipolar transistor) structure. As a result, the current amplification factor can be increased, so that the semiconductor laser can be driven even with a small current.

Further, although GaAs / GaInP / AlGaInP is used, GaAs / AlGaAs, InP / InGaAsP / InGaAs / AlInAs, GaAs
It is also possible to use a combination such as / InGaAs.

[0052]

As described above, according to the optoelectronic integrated circuit device and the method for manufacturing the same of the present invention, the optoelectronic integrated circuit device and the method for manufacturing the optoelectronic integrated circuit device can be used once by the technique of utilizing the plane orientation dependence of the incorporation rate of the dopant into the compound semiconductor substrate. With the crystal growth of (1), a plurality of compound semiconductor layers in which different conductivity type regions are mixed in one layer are stacked to form a photoelectric-semiconductor integrated device in which a semiconductor laser and a control bipolar transistor are integrated.

Further, a base extraction layer is formed on the slope portion,
Since the emitter layer is formed on the flat surface portion adjacent to the inclined surface portion, the photoelectric-semiconductor integrated device can operate at high speed. It should be noted that by forming a current blocking layer composed of one conductivity type layer and opposite conductivity type layers sandwiching the one conductivity type layer on both sides of the current channel layer, the drive current can be concentrated in the current channel layer. Therefore, the drive current can be effectively used to drive the semiconductor laser. Further, the compound semiconductor substrate surface can be effectively used by connecting the semiconductor laser and forming two parallel bipolar transistors. Furthermore, by making the bandgap of the emitter layer larger than the bandgap of the base layer,
Since the structure of the bipolar transistor is an HBT (heterojunction bipolar transistor) structure and the current amplification factor can be increased, the semiconductor laser can be driven even with a small current.

Further, according to the semiconductor device and the method of manufacturing the same of the present invention, by using the technique of utilizing the plane orientation dependence of the rate of incorporation of the dopant into the compound semiconductor substrate, different conductivity type regions can be obtained by one crystal growth. A plurality of compound semiconductor layers mixed in one layer are laminated on the first clad layer / collector layer of opposite conductivity type, and the second clad layer / base of one conductivity type of the second surface portion is laminated. A first conductivity type first base extraction layer is formed on the layer, and a first conductivity type second clad layer / base layer having a third conductivity type is formed on the first surface portion.
By forming the clad layer / emitter layer of, a bipolar transistor can be manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a photoelectric-semiconductor integrated device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the operation of the photoelectric-semiconductor integrated circuit device according to the embodiment of the invention.

FIG. 3 is a diagram (No. 1) explaining the incorporation rate of a dopant according to an example of the present invention.

FIG. 4 is a diagram (No. 2) explaining the incorporation rate of the dopant according to the example of the present invention.

FIG. 5 is a sectional view illustrating a semiconductor laser according to a conventional example.

FIG. 6 is a sectional view illustrating a photoelectric-semiconductor integrated device according to a conventional example.

[Explanation of symbols]

41 p-GaAs substrate, 42 p-GaAs buffer layer, 43 p-GaInP buffer layer, 44 n-AlGaInP clad layer / current block layer, 45 p-AlGaInP clad layer, 46 p-AlGaInP clad layer / current block layer, 47 GaInP active layer, 47a GaInP layer, 48 n-AlGaInP clad layer / current blocking layer, 49 p-AlGaInP clad layer / base layer, 50 a, 50 c n-AlGaInP clad layer / emitter layer, 50 b p-AlGaInP base extraction layer, 51 a , 51c n-GaInP emitter extraction layer, 51b p-GaInP base extraction layer, 52a, 52c n-GaAs emitter contact layer, 52b n-GaAs base contact layer, 53a, 53c AuGe / Au emitter electrode, 53b AuZn / Au base layer. Source electrode, 54 AuZn / Aup-contact electrode, 55 current channel layer.

Claims (5)

[Claims] 1. A first surface comprising a (100) plane or a plane near the (100) plane and a (311) A plane or a (311) A plane.
A compound semiconductor substrate of one conductivity type having a second surface composed of a surface near the surface, and at least an active layer formed above the second surface and a cladding layer of the opposite conductivity type on the active layer. A semiconductor laser, a cladding layer of the opposite conductivity type as a collector layer extending from above the second surface to above the first surface, and a cladding layer above the second surface and above the first surface. A base layer of one conductivity type formed on the above,
Bipolar transistor having an emitter layer of opposite conductivity type formed on a base layer above the first surface and a base lead layer of one conductivity type formed on a base layer above the second surface. A photoelectric-semiconductor integrated device having: 2. A first surface comprising a (100) plane or a plane near the (100) plane and a (311) A plane or a (311) A plane.
A compound semiconductor substrate of one conductivity type having a second surface composed of a surface near the surface, and the cladding layer of the opposite conductivity type as a collector layer extending from above the first surface to above the second surface. A base layer of one conductivity type formed on the clad layer above the first surface and the second surface, and a base layer of opposite conductivity type formed on the base layer above the first surface. A semiconductor device having a bipolar transistor having an emitter layer and a one-conductivity-type base extraction layer formed on the base layer above the second surface. 3. A first surface comprising a (100) surface or a surface near the (100) surface and a (311) A surface or a (311) A surface.
A plurality of compound semiconductor layers are stacked on a compound semiconductor substrate of one conductivity type having a second surface composed of a surface near the surface,
At least a current channel layer and an active layer of a semiconductor laser on the current channel layer are formed above the second surface, and contact the current channel layer laterally of the current channel layer above the first surface. A first compound semiconductor while doping an impurity of opposite conductivity type in a state in which at least a current blocking layer and an undoped compound semiconductor layer in contact with the active layer on the side of the current blocking layer are formed. And forming a first cladding layer / collector layer of opposite conductivity type on the active layer and the compound semiconductor layer, and growing a second compound semiconductor while doping an impurity of one conductivity type, A step of forming a second clad layer / base layer of one conductivity type on the first clad layer / collector layer, and a third compound while doping impurities of opposite conductivity type and impurities of one conductivity type A conductor is grown to form a first conductivity type first base extraction layer on the second clad layer / base layer of the second surface portion, and the second clad layer / base layer of the first surface portion is formed. On top of the third clad layer of opposite conductivity type /
And a step of forming an emitter layer. 4. The first base extraction layer on the second cladding layer / base layer of the second surface portion according to claim 3, and the first base extraction layer on the second cladding layer / base layer of the first surface portion. After the step of forming the clad layer / emitter layer of No. 3, a fourth compound semiconductor is grown while doping impurities of opposite conductivity type and impurities of one conductivity type, and on the first base extraction layer of the second surface portion. Forming a second base extraction layer of one conductivity type and forming an emitter extraction layer of the opposite conductivity type on the third cladding layer / emitter layer of the first surface portion; A fifth compound semiconductor is grown while doping a conductivity type impurity to form a one conductivity type base contact layer on the second base extraction layer of the second surface portion, and an emitter extraction of the first surface portion. Of opposite conductivity type on the layer Forming a Mitter contact layer, forming a first electrode on the emitter contact layer and forming a second electrode on the base contact layer, and forming the emitter contact layer and the base contact layer And the boundary between the emitter extraction layer and the base extraction layer are etched and removed.
Of the clad layer / emitter layer and the base extraction layer, and a method of manufacturing the photoelectric semiconductor integrated device. 5. A first surface comprising a (100) surface or a surface near the (100) surface and a (311) A surface or a (311) A surface.
A plurality of compound semiconductor layers are stacked on a compound semiconductor substrate of one conductivity type having a second surface composed of a surface near the surface,
At least a current channel layer is formed above the second surface, and at least a current blocking layer that is in contact with the current channel layer on the side of the current channel layer above the first surface is formed. Growing a first compound semiconductor while doping a conductivity type impurity, and forming a first cladding layer / collector layer of opposite conductivity type on the current channel layer and the current block layer; Growing a second compound semiconductor while doping to form a second clad layer / base layer of one conductivity type on the first clad layer / collector layer, and an impurity of opposite conductivity type and an impurity of one conductivity type While growing a third compound semiconductor to form a first conductivity type first base extraction layer on the second cladding layer / base layer of the second face portion, and The second cladding layer / base layer on the opposite conductivity type third cladding layer of the part /
And a step of forming an emitter layer.