JPH08236811A - Semiconductor light emitting device and its manufacture - Google Patents

Abstract

PURPOSE: To improve light take-out efficiency, and form an element structure having a current blocking region in a part above an active layer by one crystal growth process, by widely diffusing a current injected in an active layer, outside the part of the active layer just under an electrode on the element surface. CONSTITUTION: A current path adjusting layer 5 composed of a current blocking region 5a for blocking a current and a current passing region 5b for passing a current is formed on a multilayer structure 110 containing an active layer 3. An N-type electrode 102 is arranged above the current path adjusting layer 5, so as to face the current blocking region 5a. A P-type GaAs substrate 1 has a trench forming part 1a where a plurality of trenches 1a1 are formed in the substrate surface. The face orientation of an inclined surface of the trench 1a1 and the face orientation of a flat part 1b of the substrate surface control the conductivity of the current adjusting layer 5 which is grown on the substrate and contains dopants Zn and Se.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and a method of manufacturing the same, and more particularly to a device structure and a manufacturing process thereof for achieving higher brightness without increasing the number of manufacturing steps.

[0002]

2. Description of the Related Art In recent years, LEDs (light emitting diodes) have been spotlighted as indoor and outdoor display devices. In particular, with the increase in brightness, the outdoor display market is expected to grow rapidly in the next few years, and LEDs are expected to grow into display media that will replace neon signs in the future. High-brightness LEDs have been realized in red LEDs having an AlGaAs-based DH (double hetero) structure, and recently, high-brightness LEDs have been realized even in orange to green by AlGaInP-based DH structure LEDs.

AlGaInP-based materials exclude nitrides II
It has the largest direct transition type band gap among I-V group compound semiconductor materials, and is attracting attention as a light emitting device material in the 0.5 to 0.6 μm band.

In particular, a pn junction type light emitting diode (LED) using GaAs as a substrate material and having a light emitting portion made of AlGaInP lattice-matched to it is an indirect transition type material such as GaP or GaAsP as a constituent material of the light emitting portion. It is possible to emit light of high brightness from red to green as compared with the LED using. In order to realize a high-brightness LED, that is, to increase the amount of light emitted from the LED, in addition to increasing the luminous efficiency of the light emitting portion of the element, the light generated by the light emitting portion is absorbed inside the element. It is important to efficiently extract the light outside the device in consideration of the relative positional relationship between the light emitting portion and the electrode.

FIG. 19 is a view showing a sectional structure of a conventional LED (see Japanese Patent Laid-Open No. 4-229665) having an AlGaInP light emitting portion. In FIG. 19 (a), the current distribution in the sectional structure is indicated by a dotted line. Shown, Figure 19 (b)
Shows the way of light emission inside the element by the path (solid line) of light emitted from the light emitting portion (hereinafter referred to as LED light).

In the figure, 10 is a pn junction type light emitting diode (LED), and on the p-GaAs substrate 11,
P-AlGaInP lower clad layer 12, A on the surface
A laminated structure 10a having a double heterojunction portion, which is formed by sequentially laminating the 1GaInP active layer 13 and the n-AlGaInP upper cladding layer 14, is provided. An n-type electrode 15a is provided on the n-GaAs contact layer 15 formed on a part of the upper cladding layer 14, and p
A p-type electrode 11a is formed on the entire back surface of the -GaAs substrate 11. Then, the n-type electrode 1 of the active layer 13 is formed.
The light emitting portion 1 of the LED 10 is located immediately below 5a and in the vicinity thereof.
3a.

In the LED 10 having such a structure, there are three problems. The first problem is that the light emitting portion 13a is limited to a narrow region below the n-type electrode 15a, so that the surface of the device ( That is, the efficiency of extracting light from the upper surface is low.

[0008] That is, although the resistivity of the n-AlGaInP upper cladding layer 14 is slightly smaller than the p-AlGaInP lower cladding layer 12, the electron mobility in the upper cladding layer 14, the impurity concentration of 10 ¹⁸ cm ^- N-AlG is as small as 100 cm / V · s even when doped to a level of ^3.
There is not much current spread in the aInP upper cladding layer 14.

Therefore, the amount of light emission in the portion of the active layer directly below the n-type electrode 15a increases, and as shown in FIG.
The ED light (a to c) is reflected by the n-type electrode 15a, so that the light extraction efficiency from the upper surface of the element is low.

The second problem is that LE on the device surface is
This is the point that the light extraction efficiency is lowered due to the reflection of the D light. That is, as shown in FIG. 19B, the LED light (d) traveling from the portion immediately below the n-electrode to the outside of the n-type electrode arrangement portion on the element surface is incident on the upper surface of the element at a critical angle or more, The light is reflected inside the element on the upper surface of the element, and therefore the light extraction efficiency from the upper surface of the element is extremely low. Furthermore, as a third problem, L
For high-brightness LEDs where the ED light is in the orange to green range,
An AlGaInP mixed crystal semiconductor material is used as the constituent material, and a natural superlattice is formed in the growth layer when the crystal is grown on the surface of the substrate whose plane orientation is the (100) plane.

This natural superlattice is a group III atom I
n, Ga, and Al form a long-range ordered structure in the <111> direction. Taking GaInP as an example, the band gap of Ga _0.5 In _0.5 P in which such a natural superlattice is formed is About 9 than the band gap of Ga _0.5 In _0.5 P in which the natural superlattice is not formed in the ideal mixed crystal state.
It becomes 0 meV smaller. Therefore, when a natural superlattice is formed, the wavelength becomes longer than the desired emission wavelength, so it is necessary to increase the Al composition so that the wavelength becomes the original set value, and the emission efficiency decreases due to the increase in the Al composition. Also, there were problems such as deterioration of reliability.

As a solution to the first of the above-mentioned three problems, Japanese Patent Laid-Open No. 4-229665 discloses a method of diffusing a current between a light emitting portion and an electrode on the light extraction side. It has been disclosed that a current diffusion layer is provided to improve the current distribution in the light emitting portion.

FIG. 20 shows an L having such a current spreading layer.
The cross-sectional structure of the ED is shown. In the figure, 20 is an LED having the current spreading layer 28, and the LE shown in FIG.
Similar to D10, on the n-GaAs substrate 21, the n-AlGaInP lower cladding layer 22, AlG is formed on the surface thereof.
A laminated structure 20a having a double heterojunction portion, which is formed by sequentially laminating an aInP active layer 23 and a p-AlGaInP upper cladding layer 24, is provided. The p-GaInP intermediate bandgap layer 2 is formed on the upper cladding layer 24.
6 is formed, and n-AlG is formed on a predetermined area of the surface.
An aInP current blocking layer 27 is provided.

The current diffusion layer 28 is formed on the entire surface of the intermediate bandgap layer 26 and the current blocking layer 27. The current blocking layer 2 on the surface of the current diffusion layer 28.
P-GaAs contact layer 25 in the region facing 7
P-type electrode 25a is provided via the
An n-type electrode 21b is formed on the entire back surface of the substrate 21.

Next, the manufacturing method will be described.

First, in the first crystal growth step, n-Al is placed on the n-GaAs substrate 21 placed in the crystal growth apparatus.
GaInP lower clad layer 22, AlGaInP active layer 2
3. The p-AlGaInP upper clad layer 24 is sequentially formed, and then the p-GaInP intermediate bandgap layer 26 and the n-AlGaInP layer are grown.

Here, the substrate is once taken out from the crystal growth apparatus, mounted in an etching apparatus, and a first etching process is performed. That is, the n-AlGaInP layer is selectively etched, and the intermediate band gap layer 2 is formed.
A circular n-AlGaInP current blocking layer 27 is formed on the substrate 6.

Then, the substrate that has been subjected to the above etching treatment is mounted again in the crystal growth apparatus to perform the second crystal growth. In this second crystal growth step, a p-AlGaAs current diffusion layer 28 is grown on the entire surface of the intermediate band gap layer 26 and the n-AlGaInP current blocking layer 27, and then p-
Grow a GaAs layer.

Next, the substrate is taken out from the crystal growth apparatus, and the p-type electrode 25a and the n-type electrode 25a are formed on the p-GaAs layer.
An n-type electrode 21a is formed on the back surface side of the GaAs substrate 21. Here, the p-type electrode 25a is formed by the lift-off method using a resist or the like, or by etching the current diffusion layer 2 described above.
P-GaA formed in a region corresponding to immediately above the current blocking layer 27 on the surface of 8 and other than directly below the p-type electrode 25a.
The s layer is removed by selective etching to remove the p-type electrode 2
A p-GaAs contact layer 25 is formed immediately below 5a.

In the conventional LED 20 shown in FIG. 20,
The current L injected from the p-type electrode 25a into the current diffusion layer 28
The current diffusion layer 28 spreads greatly to both sides of the p-type electrode 25a and the p-type electrode 20 is formed through the intermediate band gap layer 26.
It is injected into the upper cladding layer 24. Therefore, in the LED 20 having this structure, the light emitting region is broadly spread to the region directly below the p-type electrode 25a and outside the vicinity thereof. In addition, since the current flowing from the p-type electrode 25a to the region directly below the p-type electrode 25a is blocked by the current blocking layer 27, the current injected into the portion of the active layer 23 immediately below the p-type electrode is diverted to the other portion. The Rukoto. As a result, the amount of light emission in the region of the active layer other than the portion directly below the p-type electrode can be increased, and the LED light extraction efficiency can be increased.

However, in order to manufacture such a device structure of the LED 20, two crystal growth steps are required, which is a problem in terms of cost and yield. Also, n
After selectively etching the n-AlGaInP layer to be the current blocking layer 27, the p-current diffusion layer 28 is formed on the p-InGaP intermediate bandgap layer 26 and the n-current blocking layer 27.
Therefore, there is a problem with the crystallinity of the regrowth interface,
It affected the characteristics and reliability.

As described above, in the conventional light emitting diode 20 shown in FIG. 20, the first problem is that the light emitting portion is limited to the narrow region below the p-type electrode, and therefore the light extraction efficiency in the upper surface direction of the element is high. Although it is effective against the problem that the value becomes low, it newly causes a problem in the manufacturing process as the fourth problem.

In the device structure of the light emitting diode 20, the second problem is that the light extraction efficiency becomes low due to the reflection of the LED light on the device surface, and further the AlG.
The third problem resulting from the natural superlattice that occurs when the aInP mixed crystal semiconductor material is grown on the (100) plane of the substrate cannot be solved, and further higher brightness can be achieved, and good characteristics and It was difficult to secure reliability.

[0024]

As described above,
The conventional semiconductor light emitting device shown in FIGS. 19 and 20 has various problems.

In summary, in the conventional semiconductor light emitting device 10 shown in FIG. 19, the current spread in the n-AlGaInP upper cladding layer 14 is not sufficient, so that n
The amount of light emission increases in the region immediately below the mold electrode, and FIG.
As shown in, the LED light (a to c) that goes upward from the region immediately below the n-type electrode is reflected by the n-type electrode 15a. Therefore, the light extraction efficiency in the upper surface direction of the device is low.

Further, the LED light (d) which is emitted from the light emitting portion to the outside of the electrode arrangement portion on the upper surface of the element and which is incident on the upper surface of the element at a critical angle or more, is not emitted from the element to the outside. From this point as well, the light extraction efficiency from the upper surface of the device was low.

In addition, in the AlGaInP mixed crystal semiconductor-based semiconductor light emitting device, a natural superlattice is formed on the surface of the substrate having a plane orientation of (100), whereby the LED light has a wavelength longer than a desired emission wavelength. Turn into. However, in order to adjust the deviation of the emission color of the LED light due to the longer wavelength,
It is necessary to increase the Al composition, and the increase of the Al composition causes problems such as a decrease in luminous efficiency and a decrease in reliability.

Further, in the semiconductor light emitting device shown in FIG. 20, by providing the current diffusion layer and the current blocking layer,
The light emitting region can be spread over a wide area other than directly below the electrodes, and the light extraction efficiency can be improved. However, the LED light incident on the upper surface of the device from the inside of the device at a critical angle or more is
There is still a problem that the efficiency of light extraction from the upper surface of the element is very low because the light cannot be emitted from the upper surface of the element. The element structure of this LED 20 is AlG.
It is not effective for the problem caused by the natural superlattice in the aInP mixed crystal semiconductor LED.

Moreover, L having the element structure shown in FIG.
The method of manufacturing the ED 20 requires two crystal growth steps, which causes an increase in cost and a decrease in yield.

Further, after growing the lower clad layer to the semiconductor layer which becomes the current blocking layer on the wafer (substrate), the wafer is once taken out from the growth apparatus and the semiconductor layer is subjected to etching treatment to select the semiconductor layer. After forming the current blocking layer by etching, the wafer is put in the growth apparatus again, and p-
The p-current spreading layer is regrown on the wafer with the intermediate bandgap layer 26 and the n-current blocking layer exposed. For this reason,
During the etching process of the current blocking layer, the wafer is taken out of the growth apparatus and exposed to the atmosphere, which easily causes oxidation of the regrowth interface and inclusion of impurities. There are problems such as deterioration of crystallinity and adverse effects on characteristics and reliability.

The present invention has been made in order to solve the above problems, and diffuses the current injected into the active layer to the outside of the portion of the active layer directly below the electrode on the device surface, A device structure capable of improving the light extraction efficiency and having a current block region in a part above the active layer is provided.
It is an object of the present invention to obtain a semiconductor light emitting device that can be formed by a single crystal growth step and a method for manufacturing the same.

Further, the light extraction efficiency can be improved not only by the diffusion of the current injected into the active layer but also by suppressing the reflection of the LED light on the device surface.
It is possible to avoid the occurrence of a natural superlattice in the case of using a P-mixed crystal semiconductor material, obtain emission light of a desired emission wavelength without causing a decrease in emission efficiency and a decrease in reliability, and activate it. It is an object of the present invention to obtain a semiconductor light emitting device capable of forming a device structure having a current blocking region in a portion above a layer by a single crystal growth step, and a manufacturing method thereof.

[0033]

A semiconductor light emitting device according to the present invention (claim 1) is a p-type compound semiconductor substrate, and a p-type lower clad layer, an active layer and an n-type upper clad layer on the surface side of the substrate. A laminated structure having a double heterojunction portion sequentially laminated, a current blocking region formed on the laminated structure for blocking a current, and a current passage region for allowing a current to pass therethrough. A current path adjusting layer containing the first and second dopants, and n formed on the upper side of the current path adjusting layer so as to face the current block region.
The p-type electrode and the p-type electrode formed on the back surface side of the p-type compound semiconductor substrate. The p-type compound semiconductor substrate has a groove forming portion in which one or a plurality of grooves are formed on the surface thereof, and the plane orientation of the slope of the groove and the plane orientation of the flat portion of the substrate surface are on the substrate. It controls the conductivity of the semiconductor region containing a predetermined dopant that is grown on the substrate.
The current blocking region of the current path adjusting layer is a region formed so as to have conductivity by the first dopant due to the plane orientation of the inclined surface of the groove, and the current passing region of the current path adjusting layer is the region of the substrate. This is a region formed to have conductivity by the second dopant depending on the plane orientation of the flat portion. Thereby, the above object is achieved.

According to a second aspect of the present invention, in the semiconductor light emitting device according to the first aspect, the plane orientation of the flat portion of the surface of the p-type compound semiconductor substrate is the (100) plane, and the groove in the groove forming portion is formed. The plane direction of the slope is the A plane, and the current path adjusting layer has a structure in which the current block region has a p-type conductivity type and the current passage region has an n-type conductivity type.

According to a third aspect of the present invention, in the semiconductor light emitting device according to the first aspect, a second n-type upper cladding layer is provided between the current path adjusting layer and the n-type electrode.

According to a fourth aspect of the present invention, in the semiconductor light emitting device according to the first aspect, the cross-sectional area of the current path on the side of the current path adjustment layer is between the current path adjustment layer and the n-type electrode. The current is diffused so that it becomes larger than that on the n-type electrode side.
A mold current spreading layer is provided.

According to a fifth aspect of the present invention, in the semiconductor light emitting device according to the fourth aspect, the n-type current diffusion layer has a structure having a second current path adjusting layer therein.
The current path adjusting layer is formed so as to have conductivity by the first dopant due to the plane orientation of the slope of the groove in the groove forming region of the p-type compound semiconductor substrate, and the surface of the flat portion of the substrate. And a current passage region formed to have conductivity by the second dopant depending on the direction.

A semiconductor light emitting device according to the present invention (claim 6) includes an n-type compound semiconductor substrate, a current block region formed on the front surface side of the substrate for blocking a current, and a current passage region for passing a current. A double-hetero structure comprising a current path adjusting layer including first and second dopants having different conductivity types, and an n-type clad layer, an active layer, and a p-type clad layer sequentially laminated on the current path adjusting layer. A laminated structure having a junction, a p-type electrode formed on the upper side of the laminated structure so as to face the current block region of the current path adjusting layer, and an n-type formed on the back surface side of the n-type compound semiconductor substrate. And electrodes. The n-type compound semiconductor substrate has a groove forming portion in which one or a plurality of grooves are formed on the surface, and the plane orientation of the slope of the groove and the plane orientation of the flat portion of the substrate surface are on the substrate. It controls the conductivity of the semiconductor region containing a predetermined dopant that is grown on the substrate. The current blocking region of the current path adjusting layer is a region formed so as to have conductivity by the first dopant due to the plane orientation of the inclined surface of the groove, and the current passing region of the current path adjusting layer is the region of the substrate. This is a region formed to have conductivity by the second dopant depending on the plane orientation of the flat portion. Thereby, the above object is achieved.

The present invention (Claim 7) is defined by Claim 1 or Claim 6.
In the semiconductor light emitting device described above, the current blocking region of the current path adjusting layer is a high resistance region.

According to the present invention (claim 8), in the semiconductor light emitting device according to claim 6, a second n-type lower cladding layer is provided between the n-type compound semiconductor substrate and the current path adjusting layer. is there.

According to a ninth aspect of the present invention, in the semiconductor light emitting device according to the eighth aspect, the cross-sectional area of the current path on the side of the laminated structure is between the laminated structure and the p-type electrode. Is provided with a p-type current diffusion layer for diffusing a current so as to be larger than that of the above.

According to a tenth aspect of the present invention, in the semiconductor light emitting device according to any one of the first to ninth aspects, a reflective layer that reflects light generated in the active layer is provided on the surface of the compound semiconductor substrate. It is arranged.

According to the present invention (claim 11), in the semiconductor light emitting device according to any one of claims 1 to 10, a laminated structure having the double heterojunction portion is formed by (Al _x G
a _1-x ) _1-y In _y P layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1).

The present invention (claim 12) is the semiconductor light-emitting device according to any one of claims 1 to 10, wherein the current path adjusting layer is an (Al _x Ga _1-x ) _1-y In _y P layer. (0 ≦ x ≦ 1, 0 ≦ y ≦ 1).

According to the present invention (claim 13), in the semiconductor light emitting device according to any one of claims 1 to 10, the current diffusion layer is composed of Al _x Ga _1-x As (0 ≦ x ≦ 1). It was done.

The present invention (claim 14) is the semiconductor light-emitting device according to any one of claims 1 to 10, wherein the current diffusion layer is an In _y (Ga _1-x Al _x ) _1-y P layer ( 0 ≦
x ≦ 1, 0 ≦ y ≦ 1).

In the method for manufacturing a semiconductor light emitting device according to the present invention (claim 15), a groove is formed on a predetermined region of a p-type compound semiconductor substrate and a semiconductor region containing a predetermined dopant is grown on the substrate. Process the substrate surface so that the conductivity of the substrate becomes different depending on the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface; A step of sequentially growing a clad layer, an active layer, and an n-type upper clad layer to form a laminated structure having a double heterojunction, and a current path adjusting layer on the laminated structure, and And a step of growing while simultaneously doping the second dopant. In the current path adjusting layer, a current blocking region that blocks a current is formed in a portion facing the groove forming portion of the substrate so as to have conductivity by the first dopant due to the plane orientation of the slope of the groove, A current passing region for passing a current is formed in a portion of the substrate facing the flat portion other than the groove forming portion so as to have conductivity due to the second dopant depending on the plane orientation of the flat portion. Thereby, the above object is achieved.

In the method for manufacturing a semiconductor light emitting device according to the present invention (claim 16), a groove is formed on a predetermined region of an n-type compound semiconductor substrate, and a semiconductor region containing a predetermined dopant is grown on the substrate. Process the substrate surface so that the conductivity of the substrate becomes different depending on the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface, and adjusting the current path on the surface side of the substrate. The layers are composed of first and second layers having different conductivity types.
Forming a p-type lower cladding layer, an active layer, and an n-type on the current path adjusting layer.
Sequentially growing the on-die clad layer to form a laminated structure having a double heterojunction. In the current path adjusting layer, a current blocking region that blocks a current is formed in a portion facing the groove forming portion of the substrate so as to have conductivity by the first dopant due to the plane orientation of the slope of the groove, A current passing region for passing a current is formed in a portion of the substrate facing the flat portion other than the groove forming portion so as to have conductivity due to the second dopant depending on the plane orientation of the flat portion. Thereby, the above object is achieved.

According to a seventeenth aspect of the present invention, in the method for manufacturing a semiconductor light emitting device, the p-type dopant of the first and second dopants is Zn, and the n-type dopant of the both dopants is Zn. It is Se.

A semiconductor light emitting device according to the present invention (claim 18) is an n-type compound semiconductor substrate, and an n-type compound semiconductor substrate is provided on the front surface side of the substrate.
A laminated structure having a double heterojunction portion, which is formed by sequentially growing a lower type clad layer, an active layer and a p-type upper clad layer,
A current path adjusting layer formed on the laminated structure, comprising a current blocking area for blocking a current and a current passing area for passing a current, and including a first and a second dopant having different conductivity types, and the current path. A p-type electrode formed on the upper side of the adjustment layer so as to face the current blocking region,
And an n-type electrode formed on the back surface of the type compound semiconductor substrate. The n-type compound semiconductor substrate has a groove forming portion in which a groove is formed on the surface thereof, and the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface are predetermined to be grown on the substrate. It controls the conductivity of the semiconductor region containing the dopant. The current blocking region of the current path adjusting layer is a region formed to have conductivity by the first dopant due to the plane orientation of the flat portion of the substrate, and the current passing region of the current path adjusting layer is the groove. Is a region formed to have conductivity by the second dopant depending on the plane orientation of the slope. Thereby, the above object is achieved.

The present invention (claim 19) is the semiconductor light-emitting device according to claim 18, wherein the current path adjusting layer and the p
A p-type current diffusion layer for diffusing the current is provided between the mold electrode and the current path adjusting layer so that the cross-sectional area of the current path on the current path adjusting layer side is larger than that on the p-type electrode side.

According to the present invention (claim 20), in the semiconductor light emitting device according to claim 19, the p-type current diffusion layer comprises:
A structure having a second current path adjusting layer therein is formed, and the second current path adjusting layer is formed to have conductivity by the first dopant depending on the plane orientation of the flat portion of the n-type compound semiconductor substrate. And a current passing region formed so as to have conductivity by the second dopant due to the plane orientation of the slope of the groove in the groove forming region of the substrate.

A semiconductor light emitting device according to the present invention (claim 21) includes a p-type compound semiconductor substrate, a current block region formed on the front surface side of the substrate for blocking a current, and a current passage region for passing a current. A current path adjusting layer including first and second dopants having different conductivity types, and a double layer formed by sequentially growing a p-type lower clad layer, an active layer and an n-type upper clad layer on the current path adjusting layer. A laminated structure having a heterojunction portion, an n-type electrode formed on the upper side of the laminated structure so as to face the current block region of the current path adjusting layer, and a p-type formed on the back surface side of the p-type compound semiconductor substrate.
And a mold electrode. The p-type compound semiconductor substrate has a groove forming portion in which a groove is formed on the surface thereof, and the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface are predetermined to be grown on the substrate. It controls the conductivity of the semiconductor region containing the dopant. The current blocking region of the current path adjusting layer is a region formed to have conductivity by the first dopant due to the plane orientation of the flat portion of the substrate, and the current passing region of the current path adjusting layer is the groove. Is a region formed to have conductivity by the second dopant depending on the plane orientation of the slope. Thereby, the above object is achieved.

The present invention (claim 22) is the semiconductor light-emitting device according to claim 18 or 21, wherein the current blocking region of the current path adjusting layer is a high resistance region.

According to a twenty-third aspect of the present invention, in the semiconductor light emitting device according to the twenty-first aspect, the cross-sectional area of the current path on the laminated structure side is between the n-type electrode and the laminated structure. The n-type current diffusion layer for diffusing the current so as to be larger than that of the above is provided.

The present invention (claim 24) provides the semiconductor light-emitting device according to any one of claims 18 to 23.
A reflective layer that reflects light generated in the active layer is provided on the surface of the compound semiconductor substrate.

In the method for manufacturing a semiconductor light emitting device according to the present invention (claim 25), a groove is formed in a predetermined region of an n-type compound semiconductor substrate, and a semiconductor region containing a predetermined dopant is grown on the substrate. Processing the substrate surface so that the conductivity of the substrate becomes different depending on the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface, and an n-type lower layer is formed on the surface side of the substrate. A step of sequentially growing a clad layer, an active layer, and a p-type upper clad layer to form a laminated structure having a double heterojunction portion; a current path adjusting layer on the laminated structure; Forming the second dopant while simultaneously doping the second dopant. In the current path adjusting layer, a current blocking region for blocking current is formed in a portion facing the flat portion other than the groove forming portion of the substrate so as to have conductivity by the first dopant due to the plane orientation of the flat portion. A current passage region, which is formed and allows a current to pass therethrough, is formed in a portion of the substrate facing the groove formation portion so as to have conductivity due to the second dopant due to the plane orientation of the slope of the groove. Thereby, the above object is achieved.

In the method for manufacturing a semiconductor light emitting device according to the present invention (claim 26), a groove is formed in a predetermined region of a p-type compound semiconductor substrate and a semiconductor region containing a predetermined dopant is grown on the substrate. Process so that the conductivity of the substrate becomes different depending on the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface, and a current path adjusting layer is provided on the surface side of the substrate. Forming a p-type lower clad layer, an active layer, and an n-type upper clad layer on the current path adjusting layer in sequence while simultaneously forming the first and second dopants different from each other. Forming a laminated structure having parts. In the current path adjusting layer, a current blocking region for blocking current is formed in a portion facing the flat portion other than the groove forming portion of the substrate so as to have conductivity by the first dopant due to the plane orientation of the flat portion. A current passage region, which is formed and allows a current to pass therethrough, is formed in a portion of the substrate facing the groove formation portion so as to have conductivity due to the second dopant due to the plane orientation of the slope of the groove. Thereby, the above object is achieved.

According to a twenty-seventh aspect of the present invention, in the method of manufacturing a semiconductor light-emitting device according to the twenty-fifth or twenty-sixth aspect, the p-type dopant of the first and second dopants is Zn, and the dopant of the both dopants is Zn. Of these, the n-type dopant is Se.

[0060]

In the present invention (claim 1), a current blocking region for blocking current and a current passing region for passing current are provided on the laminated structure including the active layer provided on the surface side of the p-type compound semiconductor substrate. And the n-type electrode is arranged on the upper side of the current path adjusting layer so as to face the current block area. Therefore, the operating current of the element is the current blocking area immediately below the n-type electrode. It will be blocked by and spread widely on both sides. For this reason, the LED is formed in a region of the active layer other than the portion directly below the n-type electrode.
Since light is generated, the generated LED light is effectively extracted to the outside without being blocked by the n-type electrode.
As a result, the efficiency of deriving the LED light is improved and the brightness of the semiconductor light emitting device can be increased.

Further, the p-type compound semiconductor substrate has a groove forming portion in which one or a plurality of grooves are formed on the surface thereof, and the plane orientation of the slope of the groove and the plane orientation of the flat portion of the substrate surface. Has a structure that controls the conductivity of the semiconductor layer containing a predetermined dopant grown on the substrate, and therefore, the current blocking region and the current passing region are included in the current path adjusting layer having the first and second dopants. The region and the region can be formed at the same time. That is, the current blocking region is formed as a region having conductivity with the first dopant due to the plane orientation of the slope of the groove of the substrate, and the current passage region is formed with the second dopant due to the plane orientation of the flat portion of the substrate. Is formed as a region having conductivity. As a result, an element structure having a current block region in a part above the active layer can be formed by one crystal growth step.

According to the present invention (claim 2), in the semiconductor light emitting device according to claim 1, the plane direction of the flat portion of the surface of the p-type compound semiconductor substrate is set to (100) plane, and the groove in the groove forming portion is formed. Since the plane orientation of the slope is the A plane and the current path adjusting layer has a structure in which the current block region has the p-type conductivity type and the current passage region has the n-type conductivity type, By using Zn as the p-type dopant and Se as the n-type dopant in the adjustment layer, the conductivity of the p-type current block region and the n-type current passage region based on the plane orientation of the substrate can be made high in the carrier concentration in each region. Therefore, the function of the current path adjusting layer can be made more effective.

According to the present invention (claim 3), in the semiconductor light emitting device according to claim 1, since the second n-type upper cladding layer is provided on the current path adjusting layer, the current path adjusting layer and the active layer are formed. The thickness of the n-type upper clad layer in between can be reduced.
Therefore, it is possible to prevent the current once spread by the current blocking region of the current path adjusting layer from wrapping around the lower side of the current blocking region, and reduce the current injected into the portion of the active layer immediately below the n-type electrode. be able to. As a result, light emission increases in the region of the active layer other than the portion directly below the n-type electrode, and the light extraction efficiency can be further improved.

According to the present invention (claim 4), in the semiconductor light emitting device according to claim 1, the current path adjusting layer and n
Since the current diffusion layer is provided between the n-type electrode and the mold electrode, the current flowing from the n-type electrode to the active layer spreads largely on the side of the current path adjusting layer as compared with the n-type electrode side. As a result, in the active layer, the light emitting region spreads from the portion directly below the n-type electrode to a portion further away from the n type electrode, which can help improve the light extraction efficiency.

Further, by making the current diffusion layer have a structure having a wider bandgap than the active layer, it is possible to promote the improvement of the light extraction efficiency without causing the light generated in the active layer to be absorbed in the current diffusion layer. Therefore, a semiconductor light emitting device with higher brightness can be obtained.

According to the present invention (claim 5), in the semiconductor light emitting device according to claim 4, the n-type current diffusion layer is
Since the structure has the second current path adjusting layer formed therein, which includes the current block area and the current passing area having the same configuration as the current path adjusting layer, the current path from the n-type electrode to the active layer is formed. The current can be spread over a wider area. As a result, the amount of light emission outside the portion of the active layer directly below the n-type electrode increases, and the light extraction efficiency can be further improved.

In the present invention (claim 6), a current path adjusting layer consisting of a current blocking area for blocking current and a current passing area for passing current is provided on the n-type compound semiconductor substrate, and the current path adjusting layer is provided. Since the laminated structure including the active layer is provided on the adjustment layer, and the p-type electrode is arranged above the laminated structure so as to face the current block region of the current path adjustment layer, the operating current of the device is It is blocked by the current blocking region immediately below the electrode and spreads widely on both sides. For this reason, LED light is generated in a region of the active layer other than the portion directly below the p-type electrode, and the generated LED light is effectively taken out without being blocked by the p-type electrode. As a result, the efficiency of deriving the LED light is improved and the brightness of the semiconductor light emitting device can be increased.

Further, the n-type compound semiconductor substrate has a groove forming portion in which one or a plurality of grooves are formed on the surface thereof, and the plane orientation of the slope of the groove and the plane orientation of the flat portion of the substrate surface. Has a structure that controls the conductivity of the semiconductor layer containing a predetermined dopant grown on the substrate, and therefore, the current blocking region and the current passing region are included in the current path adjusting layer having the first and second dopants. The area and the area can be formed at the same time. As a result, an element structure having a current block region in a part below the active layer can be formed by one crystal growth step.

Moreover, since the n-type compound semiconductor substrate is used, the current path adjusting layer composed of the p-type current block region and the n-type current passage region is arranged at a position close to the substrate below the laminated structure. it can. As a result, the shape of the groove formed in the substrate is sufficiently reflected in the current path adjustment layer, and the carrier concentrations of the p-type current block region and the n-type current passage region depending on the plane orientation of the underlayer are: Each conductivity can be set to a desired large value, so that the function of the current path adjusting layer can be made more effective.

According to the present invention (claim 7), in the semiconductor light emitting device according to claim 1 or 6, since the current blocking region of the current path adjusting layer is a high resistance region, the first and second dopants are not added. The doping amount of one of them can be reduced.

According to the present invention (claim 8), in the semiconductor light emitting device according to claim 6, a second n-type lower cladding layer is provided between the n-type compound semiconductor substrate and the current path adjusting layer. Therefore, n between the current path adjusting layer and the active layer
The layer thickness of the under-mold clad layer can be reduced, and the current to the portion of the active layer facing the p-type electrode can be reduced.
Therefore, the current can be spread over a wider area, light emission in the active layer other than the groove portion can be increased, and the light extraction effect can be further improved.

According to the present invention (claim 9), in the semiconductor light emitting device according to claim 8, the current spreading layer is provided between the p-type electrode and the laminated structure having the active layer.
The current spreads in the current diffusion layer from the p-type electrode to the active layer, and the amount of light emission in the part of the active layer other than the part facing the p-type electrode increases, thereby improving the current derivation efficiency. it can. In addition, by configuring the current diffusion layer to have a wider bandgap than the active layer, it is possible to prevent the light from the active layer from being absorbed by the current diffusion layer, thereby further improving the light extraction efficiency and improving the semiconductor light emitting device. It is possible to increase the brightness.

In the present invention (claim 10), in the semiconductor light emitting device, since the light reflecting layer is provided on the surface of the compound semiconductor substrate, the light emitted to the substrate side among the light emitted from the active layer. Is reflected by the reflective layer, is not absorbed by the substrate having a high refractive index, and the light extraction efficiency can be further improved.

According to the present invention (claim 11), in the above semiconductor light emitting device, a laminated structure having a double heterojunction portion is formed into an (Al _x Ga _1-x ) _1-y In _y P layer (0 ≦ x
≤1, 0 ≤ y ≤ 1), so that light emission in the visible light region from red to green can be realized by changing the Al composition.

According to the present invention (claim 12), in the semiconductor light emitting device according to any one of claims 1 to 10, the current path adjusting layer is (Al _x Ga _{1- x} ) _1-y.
Since it is composed of the In _y P layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), the light emitted from the active layer can be prevented from being absorbed by the current path adjustment layer. Further, the dopants are Zn and S
The conductivity of the current path adjusting layer, which is e, can be adjusted by the plane orientation of the substrate.

According to the present invention (claim 13), in the semiconductor light emitting device according to any one of claims 1 to 10, the current diffusion layer is composed of Al _x Ga _{1 -x} As, It is possible to prevent the light emitted from the layers from being absorbed in the current path adjusting layer, and the current diffusion layer and the substrate are lattice-matched, so that the semiconductor layer between them is strain-free and has good crystallinity. Can be something.

According to the present invention (Claim 14), in the semiconductor light emitting device according to any one of Claims 1 to 10, the current diffusion layer is formed of (Al _x Ga _{1- x} ) _1-y In.
Since it is composed of _y P layers (0 ≦ x ≦ 1, 0 ≦ y ≦ 1),
The bandgap can be made wider than that of Al _x Ga _{1 -x} As used in claim 12, absorption of light emitted from the active layer in the current diffusion layer can be further reduced, and light extraction efficiency can be further improved. Can be made.

In the present invention (claim 15), a groove is formed on a predetermined region of the p-type compound semiconductor substrate, and the conductivity of the semiconductor layer containing the predetermined dopant grown on the substrate is controlled by the groove. Of the flat surface of the substrate and the plane orientation of the flat part of the substrate surface to form different ones, and after forming a laminated structure having a double heterojunction portion on the substrate, a current is formed on the laminated structure. Since the path adjusting layer is formed while simultaneously doping the first and second dopants having different conductivity types, the current blocking region has the first blocking area in the current path adjusting layer due to the plane orientation of the slope of the groove. Except for the groove forming part of the substrate, the current passing region is formed so as to have conductivity by the dopant and is opposed to the groove forming part of the substrate, and the current passage region has conductivity by the second dopant depending on the plane orientation of the flat part. Flat part of It is formed on the opposing portions.

Therefore, the semiconductor light emitting device having the current block region in the laminated structure of the semiconductor layers is subjected to MOCVD once.
It can be manufactured by growth, which can significantly reduce the cost and significantly improve the yield. In addition, the current block region in the current path adjustment layer has a MOCV
Since it is selectively formed in the current path adjusting layer during the D growth, the etching process for forming the current block region is unnecessary. In other words, there is no need for the step of growing the semiconductor layer on the substrate, then removing the substrate from the growth apparatus and subjecting it to an etching process. This prevents exposure of the surface of the growing semiconductor layer to the atmosphere, and re-growth. It is possible to solve the problem of crystallinity at the regrowth interface, which is caused by the oxidation of the interface and the mixing of impurities. As a result, the characteristics and reliability of the semiconductor light emitting device can be kept high.

According to the present invention (claim 16), the selectivity of the surface of the n-type compound semiconductor substrate with respect to the conductivity of the semiconductor layer in which the groove forming portion and the flat portion include a predetermined dopant grown thereon. To form a current path adjusting layer on the substrate while simultaneously doping first and second dopants having different conductivity types, and then forming a laminated structure having an active layer on the current path adjusting layer. Since it is formed, in the current path adjusting layer, a current block region is formed in a portion corresponding to the groove forming portion, and a current passage region is formed in a portion corresponding to the flat portion. As a result, the semiconductor light emitting device having the current blocking region can be subjected to one MOCV
It can be manufactured by D growth, which can significantly reduce the cost and greatly improve the yield and solve the problem of crystallinity at the regrowth interface.

Further, since the n-type compound semiconductor substrate is used, the current path adjusting layer composed of the p-type current block region and the n-type current passage region is formed in the portion below the laminated structure near the substrate. Therefore, the shape of the groove formed in the substrate is sufficiently reflected in the current path adjusting layer, and the carrier concentration in the p-type current block region and the n-type current passage region can be controlled with high accuracy.

In the present invention (claim 17), since Zn is used as the II group dopant and Se is used as the VI group dopant in the method for manufacturing a semiconductor light emitting device, a p-type current block region based on the plane orientation of the substrate and The conductivity of the n-type current passage region can be made high in the carrier concentration in each region, and the function of the current path adjustment layer can be made more effective.

In the present invention (claim 18), a current path adjusting layer comprising a current block region and a current passing region is provided on the laminated structure including the active layer formed on the surface side of the n-type compound semiconductor substrate. , Above the current path adjustment layer,
Since the p-type electrode is arranged so as to face the current block region, the current flowing from the p-type electrode to the active layer is blocked by the current block region and spreads widely on both sides thereof. For this reason, the amount of LED light emitted in the region of the active layer other than the portion directly below the p-type electrode increases, and the generated LED light is effectively extracted to the outside without being blocked by the p-type electrode. As a result, the efficiency of deriving the LED light is improved and the brightness of the semiconductor light emitting device can be increased.

Further, the n-type compound semiconductor substrate has a groove forming portion having a groove formed on the surface and a flat portion having a flat surface, and the plane orientation of the slope of the groove and the plane of the flat portion of the substrate surface. Since the azimuth has a structure that controls the conductivity of the semiconductor layer containing a predetermined dopant grown on the substrate,
And in the current path adjusting layer having the second dopant,
The current block region and the current passage region can be formed at the same time. As a result, an element structure having a current block region in a part below the active layer can be formed by one crystal growth step.

Further, in the present invention, since the p-type electrode is not arranged in the area of the device surface where the LED light is emitted, the LED light is not blocked, and the surface of this area is the same as that of the substrate. Since the unevenness of the groove formation part is reflected and the unevenness is achieved, the ratio of the LED light that enters the surface of the device from the inside at a critical angle or more decreases, which results in the light extraction efficiency from the top surface of the device. Is improved.

Further, since the current passage region of the current path adjusting layer is located corresponding to the groove forming portion of the substrate, the light emitting region of the active layer is also located corresponding to the groove forming portion of the substrate, and the groove shape is also formed. Is reflected in the uneven shape. Therefore, the light emitting area is increased as compared with an LED in which the light emitting region of the active layer is flat, and the light output efficiency is increased due to the increase in the light emission amount.

Further, by configuring the current path adjusting layer to have a wider bandgap than the active layer, it is possible to prevent light from the active layer from being absorbed by the current path adjusting layer.
It is possible to further improve the light extraction efficiency and increase the brightness of the semiconductor light emitting device.

Further, by setting the plane orientation of the groove slope in the groove forming region of the substrate to be the A plane, AlGaI is formed by the MOCVD method.
Even if the nP mixed crystal semiconductor system is grown, the natural superlattice is not formed in the light emitting region of the active layer, and it is possible to prevent the emission wavelength from becoming longer due to the natural superlattice. Therefore, it is not necessary to increase the Al composition of the active layer so as to obtain the set wavelength, and a semiconductor light emitting device with high brightness and high reliability can be realized.

Moreover, since the portion of the substrate just below the p-type electrode is flat, the surface of the p-type electrode is flat, and the adhesion strength between the p-type electrode and the wire bonded thereto is increased. Can be improved.

In the present invention (claim 19), in the semiconductor light emitting device according to claim 18, since the p-type current diffusion layer is provided above the current path adjusting layer, the current is spread by the p-type current diffusion layer. Therefore, light emission is possible in a wider area of the active layer other than the portion corresponding to the p-type electrode. Further, by configuring the current diffusion layer to have a wider bandgap than that of the active layer, it is possible to prevent light from the active layer from being absorbed by the current diffusion layer, further improving the light extraction efficiency, and The brightness of the light emitting element can be increased.

According to the present invention (claim 20), in the semiconductor light emitting device according to claim 19, the p-type current diffusion layer is formed inside the current block region and has the same structure as the current path adjusting layer. Since it has a structure having a current passing region, and in the path from the p-type electrode to the active layer,
The current can be spread over a wider area. This increases the amount of light emitted outside the portion of the active layer directly below the p-type electrode,
Further, the light extraction efficiency can be improved.

According to the present invention (claim 21), the compound semiconductor substrate in the semiconductor light emitting device according to claim 18 has a conductivity type of p-type, and a laminated structure having a double heterojunction portion is used. And the n-type upper clad layer, and a current path adjusting layer having an n-type current blocking region and a p-type current passage region is disposed between the laminated structure and the substrate. The function of the current path adjusting layer in the semiconductor light emitting device according to claim 18 can be made more effective.

That is, since the p-type compound semiconductor substrate is used, the current path adjusting layer composed of the n-type current block region and the p-type current passage region is arranged at a position close to the substrate below the laminated structure. it can. As a result, the shape of the groove formed in the substrate is sufficiently reflected in the current path adjustment layer, and the carrier concentrations of the p-type current block region and the n-type current passage region depending on the plane orientation of the underlayer are: Each conductivity can be set to a desired large value, so that the function of the current path adjusting layer can be made more effective.

According to the present invention (claim 22), in the semiconductor light emitting device according to claim 18 or 21, the current blocking region of the current path adjusting layer is a high resistance region.
The doping amount of one of the first and second dopants can be reduced.

According to the present invention (claim 23), in the semiconductor light emitting device according to claim 21, since the current spreading layer is provided on the laminated structure having the double heterojunction portion, the current spreading layer can generate a current. It can be widened, and light emission is possible in a wider region of the active layer other than the portion corresponding to the n-type electrode.

Further, in the n-type current diffusion layer, the carrier mobility is higher and the resistivity is lower than that of the p-type one.
It has a large current diffusion effect and can emit light over a wider area. Further, by configuring the current diffusion layer to have a wider bandgap than that of the active layer, it is possible to prevent light from the active layer from being absorbed by the current diffusion layer, thereby further improving the light extraction efficiency, The brightness of the light emitting element can be increased.

In the present invention (claim 24), in each of the semiconductor light emitting devices, since the light reflecting layer is provided on the surface of the compound semiconductor substrate, the light emitted to the substrate side out of the light emitted from the active layer. Since the light is reflected by the reflective layer, it is not absorbed by the substrate having a high refractive index, and the light extraction efficiency can be further improved.

In the present invention (claim 25), the selectivity of the surface of the n-type compound semiconductor substrate with respect to the conductivity of the semiconductor layer in which the groove forming portion and the flat portion include a predetermined dopant grown thereon. To form a laminated structure having an active layer on the substrate, and a current path adjusting layer is formed on the laminated structure to form first and second conductive layers having different conductivity types.
Since the current path adjusting layer is formed while being simultaneously doped with the dopant, a current block region is formed at a position corresponding to the groove forming portion, and a current passing region is formed at a position corresponding to the flat portion. . As a result, a semiconductor light emitting device having a current blocking region can be manufactured by one MOCVD growth. In other words, during the crystal growth, it is possible to significantly reduce the cost and improve the yield by removing the substrate from the growth device whose crystal growth surface is exposed to the atmosphere. Sexual problems can be resolved.

In the present invention (claim 26), the p-type compound semiconductor substrate is treated in the same manner as in the method for manufacturing a semiconductor light emitting device according to claim 9 to form a groove forming portion and a flat portion on the surface thereof. Forming a current path adjusting layer on the substrate, and then forming a p-type lower cladding layer on the current path adjusting layer,
Since the active layer and the n-type upper cladding layer are sequentially grown to form a laminated structure, the carrier concentration in the current blocking region and the current passage region of each conductivity type of the current path adjusting layer can be increased.

That is, since the p-type compound semiconductor substrate is used, the current path adjusting layer consisting of the n-type current block region and the p-type current passage region can be formed in the portion near the substrate below the laminated structure. The shape of the groove formed on the substrate is sufficiently reflected in the current path adjusting layer, and the carrier concentration in the current block region and the current passage region of each conductivity type can be controlled with high accuracy.

According to the present invention (claim 27), in the method for manufacturing a semiconductor light-emitting device according to claim 25 or 26, the group II dopant is Zn and the group VI dopant is Se.
Therefore, the conductivity of the p-type current blocking region and the n-type current passage region based on the plane orientation of the substrate can be made to have a high carrier concentration in each region, and the function of the current path adjusting layer can be made more effective. Can be

[0102]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 is a view for explaining a light emitting diode as a semiconductor light emitting device according to a first embodiment of the present invention, and FIG. 1 (a) is a sectional view showing the structure of the light emitting diode. 1 (b) and 1 (c) are a plan view and a cross-sectional view showing the structure of a substrate forming a light emitting diode. 2A and 2B are views for explaining a method for manufacturing the light emitting diode, and FIG. 2A is a diagram showing a step of crystal-growing various semiconductor layers constituting the light emitting diode.
(B) is a figure which shows the process of forming the electrode in a light emitting diode.

In the figure, reference numeral 100a denotes a light emitting diode of this embodiment, in which a p-type lower clad layer 2, an active layer 3 and an n-type upper clad layer 4 are sequentially grown on the surface of the p-type GaAs substrate 1. The laminated structure 110 having a double heterojunction portion is formed. In this embodiment, a p-type semiconductor region (current blocking region) that blocks current is provided on the n-type clad layer 4 of the laminated structure 110.
A current path adjustment layer 5 including an n-type semiconductor region (current passage region) 5b that allows a current to pass therethrough is provided. A p-type GaAs contact layer 7 is provided on the current path adjusting layer 5 via an n-type current diffusion layer 6 so as to be located directly above the current block region 5a of the current path adjusting layer 5, and the contact is formed. An n-type electrode 102 made of AuGe is arranged on the layer 7. Further, on the entire back surface of the p-type GaAs substrate 1, the p-type electrode 1 made of AuZn is formed.
01 is formed.

Here, the p-type GaAs substrate 1 has a circular region (groove forming portion) 1a having a diameter of 200 μm at the center thereof.
A plurality of V-shaped grooves 1a1 having a depth of 4.3 μm and a width of 6 μm are formed in a stripe shape on the substrate 1. Areas of the substrate 1 other than the groove forming portions 1a are flat portions having a flat surface. . The plane direction of the flat portion of the substrate 1 is (10
The surface orientation of the inclined surface of the V-shaped groove 1a1 is the (111) A surface.

The lower clad layer 2, the active layer 3 and the upper clad layer 4 are (Al _x Ga _{1 -x} ) _{1 -y} In _{y, respectively.}
P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and in the lower cladding layer 2 and the upper cladding layer 4, for example, the composition ratio x,
y is x = 0.70, y = 0.50, the layer thickness is 1.0 μ
The lower clad layer 2 has a Zn carrier concentration of 1 × 10 ¹⁸ cm ⁻³ , and the upper clad layer 4 has a Si carrier concentration of 5 × 10 ¹⁷ cm ⁻³ . In the active layer 3, for example, the composition ratios x and y are x = 0.30, y = 0.50, and the layer thickness thereof is 0.50 μm.

The constituent material of the current path adjusting layer 5 is also (Al _x Ga _1-x ) _1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦
1), the composition ratio of x and y is x = 0.70, y =
0.50, and the layer thickness is 0.7 μm. The current path adjusting layer 5 is doped with Zn as a group II dopant and Se as a group V dopant. The current block region 5a of the current path adjusting layer 5 is located right above the groove forming region 1a of the substrate 1, and based on the (111) A plane which is the plane orientation of the slope of the groove 1a1 of the substrate 1, Carrier concentration showing p-type conductivity due to dopant Zn 3 × 10 ¹⁸
The area is cm ^-3 . The current passage region 5b of the current path adjusting layer 5 is located above the flat portion 1b of the substrate 1 and has the plane orientation of the flat portion 1b (10
Based on the (0) plane, the region has a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ , which exhibits an n-type conductivity due to the dopant Se.

Further, the current diffusion layer 6 is made of n-type Al _x G.
a _1-x As (0 ≦ x ≦ 1), and the composition ratio x is x
= 0.70, and the layer thickness is 5 μm.
The n-type current diffusion layer 6 and the n-type GaAs contact layer 7 each have a Si carrier concentration of 5 × 10 ¹⁸ c.
It is m ^-3 .

Next, the manufacturing method will be described.

First, the diameter 20 of the surface of the p-type GaAs substrate 1
In a circular region of 0 μm, grooves having a depth of 4.3 μm and a width of 6 μm in which the plane orientation of the slope is, for example, a (111) A plane are formed in a stripe shape by etching (FIG. 1).
(See (b) and (c)).

Next, the semiconductor layers 2 to 7 are formed on the etched substrate 1 by a single crystal growth step using MOCVD (FIG. 2A).

That is, after the above etching treatment, p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is used as the p-type lower cladding layer 2 on the substrate 1 and the Zn carrier concentration is 1 × 10 ¹⁸ cm 2.
It grows to a thickness of about 1.0 μm to become ⁻³ . continue,
(Al _0.3 Ga _0.7 ) _0.5 In _0.5 P is used as the active layer 3.
It is formed to a thickness of about 50 μm, and n-type (A
l _0.7 Ga _0.3 ) _0.5 In _0.5 P is grown as the n-type upper cladding layer 4 to a layer thickness of about 1 μm so that the Si carrier concentration is 5 × 10 ¹⁷ cm ⁻³ . At this time, the surface shape of the substrate 1 is substantially inherited by the semiconductor layer grown thereon, and the surface of the n-type upper cladding layer 4 has a region corresponding to the groove forming portion 1a of the substrate 1. , A plurality of grooves whose plane orientation of the slope is the (111) A plane are formed, and the region of the surface of the cladding layer 4 corresponding to the flat portion 1b of the substrate 1 has the plane orientation of (100). It is a flat area.

Further, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is used as the current path adjusting layer 5 on the surface of the clad layer 4 as described above, and Zn (group II dopant) and Se are added.
Layer thickness 0.7μ while simultaneously doping (VI group dopant)
Grow about m.

Here, when growing AlGaInP, II
It is known that when Zn, which is a group dopant, and Se, which is a group VI dopant, are simultaneously doped, the conductivity type and the carrier concentration change depending on the plane orientation of the underlying semiconductor crystal. FIG. 3 shows the change in conductivity type and carrier concentration with respect to the off angle from the (100) plane to the (111) A plane direction by the experimental results. The carrier concentration of n and the n-type carrier concentration are shown.

As can be seen from this figure, when AlGaInP is grown by simultaneously doping Zn and Se as dopants by 3 × 10 ¹⁸ cm ⁻³ , the (311) A plane and (11)
1) A p-type semiconductor region having a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ on the A-plane, and a carrier concentration of 3 × 1 on the (100) plane.
A 0 ¹⁸ cm ⁻³ n-type semiconductor region is obtained.

Therefore, as described above, Zn and Se are simultaneously doped by 3 × 10 ¹⁸ cm ⁻³ (Al _0.7 Ga).
_{When 0.3} ) _0.5 In _0.5 P is grown on the clad layer 4, the carrier concentration is 3 in the region where the (111) A plane is exposed on the surface of the clad layer 4, that is, the region corresponding to the groove forming portion 1a of the substrate 1. A p-type semiconductor region of × 10 ¹⁸ cm ^-3 is formed as the current block region 5a, and the cladding layer 4 is formed.
In the region of the surface where the (100) plane is exposed, that is, in the region corresponding to the flat portion 1b of the substrate 1, the carrier concentration is 3 × 1.
An 0 ¹⁸ cm ⁻³ n-type semiconductor region is formed as the current passage region 5b.

Then, n-type A is formed on the current path adjusting layer 5.
l _0.7 Ga _0.3 As is grown as the current diffusion layer 6 to a thickness of about 5 μm, and the n-type GaAs layer 7a is grown to a thickness of about 1 μm so that the Si carrier concentration becomes 5 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 2B, an AuGe layer 102a is formed on the n-type contact layer 7, and an AuZn layer 101 as a p-type electrode is formed on the back surface of the p-type substrate 1. . After that, the n-type GaAs layer 7 a and the AuGe layer 102 are formed on the groove forming portion 1 of the substrate 1.
The n-type GaAs contact layer 7 and the n-type electrode 102 are selectively etched so that the portion immediately above a is left.
To form. As a result, the light emitting diode 100a is completed (see FIG. 1A).

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, an LED having a peak wavelength of 584 nm and a luminous intensity of more than 5 cd was obtained.
The light was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, a luminous intensity of 3 cd at a peak wavelength of 555 nm was obtained. A pure green light emission exceeding that was obtained.

In the semiconductor light emitting device 100a of this embodiment,
Laminated structure 11 including active layer 3 on p-type GaAs substrate 1
0, a current path adjusting layer 5 composed of a current block area 5a and current passing areas 5b on both sides thereof is formed, and an n-type electrode 102 is formed on the current path adjusting layer 5 via a current diffusion layer 6.
Is arranged so as to be located right above the current block region 5a. Therefore, between the active layer 3 and the n-type electrode 102, the current is diffused from the portion directly below the n-type electrode 102 to the both sides thereof by the current diffusion layer 6. Further, in the current path adjusting layer 5, the current blocking region 5a makes it difficult for current to flow in the portion of the active layer 3 immediately below the n-type electrode 102. As a result, the light emitting region in the active layer 3 spreads to both sides thereof so as to avoid the portion directly below the n-type electrode, and the LED light generated in the active layer 3 does not have the n-type electrode 102 on the surface of the light emitting diode. It will be efficiently extracted from the area.

[0122] Also, since the current diffusion layer 6 and the current path adjusting layer 5 each are composed of _{(Al 0.7 Ga 0.3) 0. 5} In 0.5 P, an active layer made of _{(Al 0.3 Ga 0.7) 0.5 In} 0.5 P 3, the bandgap is wider than that of LED 3, and therefore, the LED light from the active layer 3 is not absorbed by the current diffusion layer 6 and the current path adjustment layer 5, and the light extraction efficiency is further improved, and the high efficiency of the light emitting diode 100a. Brightness can be achieved.

Further, in this embodiment, the plane orientation of the surface is (1
The (00) plane p-type GaAs substrate 1 is partially (11)
1) Since the structure has a groove forming portion 1a in which a groove is formed in a stripe shape so that the surface A is exposed, the surface of the laminated structure 110 including the active layer 3 formed on the substrate 1, that is, the upper clad layer 4 On the surface of the (111) A surface and the flat portion 1b (1) exposed on the groove forming portion 1a of the substrate.
The plane orientation of the (00) plane appears.

Moreover, in this embodiment, AlGaI is doped on the clad layer 4 while being doped with the dopants Zn and Se.
Since nP is growing, Se is on the (100) plane.
A current block region 5a having an n-type conductivity type is formed, and a current passage region 5b having a p-type conductivity type of Zn is formed on the (111) A plane. Therefore, in the step of forming the current path adjusting layer 5 having the current block region 5a, the p-type lower cladding layer 4 to the n-type contact layer 7 are formed once by MOCVD without interrupting the crystal growth process.
It is possible to grow in the process, reduce the manufacturing cost, and significantly improve the yield.

In addition, it is possible to avoid the deterioration of the characteristics and reliability due to the crystallinity at the regrowth interface in the semiconductor laminated structure which constitutes the light emitting diode.

That is, in the conventional method for manufacturing a light emitting diode, after a semiconductor layer to be a laminated structure including an active layer and a current blocking layer is grown on a substrate, the substrate (wafer) is once taken out from the growth apparatus and the semiconductor layer is removed. Since the current blocking layer was formed by selective etching, the wafer was then put back into the growth apparatus, and the current spreading layer was regrown on the wafer where the intermediate band gap layer and the current blocking layer above it were exposed. Oxidization of the regrowth interface and mixing of impurities into the regrowth interface are likely to occur, and there is a problem with the crystallinity at the regrowth interface, which adversely affects the characteristics and reliability.

On the other hand, in the method of manufacturing the light emitting diode of this embodiment, each semiconductor layer forming the light emitting diode can be manufactured by one MOCVD growth, and regrowth is not required, so that the characteristics are high and high. Reliable.

(Embodiment 2) FIG. 4 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a second embodiment of the present invention, in which 100b is the light emitting diode of the present embodiment. The same reference numerals as those in FIG. 1 denote the same parts as the light emitting diode 100a of the first embodiment, and the light emitting diode 100b includes a current path adjusting layer 5 and a current spreading layer 6.
And the second n-type upper cladding layer 4a provided between the light emitting diode 100a and the light emitting diode 100a according to the first embodiment.
Is different from

Like the n-type upper clad layer 4 between the active layer 3 and the current path adjusting layer 5, the second n-type upper clad layer 4a has a Si carrier concentration of 5 × 10 ¹⁷ cm ⁻³ . n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P
The layer thickness is about 1 μm.

In the method of manufacturing the light emitting diode 100b of this embodiment, after the current path adjusting layer 5 is formed, the second layer is formed thereon.
The manufacturing method of the light emitting diode 100a is the same as that of the first embodiment except that the n-type upper cladding layer 4a is formed.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device 100b according to this example, LED light having a peak wavelength of 584 nm and a luminous intensity of more than 5.5 cd was obtained.

The composition x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer 3 are x = 0.50 and y = 0.50, respectively.
As a result, the luminous intensity at the peak wavelength of 555 nm is 3.5c.
Pure green light emission exceeding d was obtained.

Since the second n-type upper cladding layer 4a is provided between the current path adjusting layer 5 and the current diffusion layer 6 in this embodiment having such a structure, the current path adjusting layer 5 and the active layer are formed. Three
The layer thickness of the n-type upper cladding layer 4 between and can be reduced to about 0.5 μm. As a result, the current once spread by the current block region 5a of the current path adjusting layer 5 can be suppressed from wrapping around below the current block region 5a, and the n of the active layer 3 can be suppressed.
It is possible to reduce the current flowing into the portion directly below the mold electrode 102. As a result, the amount of light emission in the region other than the portion directly below the n-type electrode of the active layer 3 increases, and the light extraction efficiency can be further improved as compared with the light emitting diode 100a of the first embodiment.

(Embodiment 3) FIG. 5 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a third embodiment of the present invention, in which 100c is the light emitting diode of the present embodiment. In this light emitting diode 100c,
The current spreading layer 6 according to the first embodiment is provided with the second current path adjusting layer 105 formed therein.
06, the second current diffusion layer 105 has a current block region 105a located immediately below the n-type electrode 102, similar to the current path adjustment layer 5 in the first embodiment.
It is composed of current passage regions 105b located on both sides of the current block region 105a.

The second current path adjusting layer 105 is also made of (Al _0.7 G) having a layer thickness of 0.7 μm doped with Zn and Se.
a _0.3 ) _0.5 In _0.5 P layer, and the current path adjusting layer 1
The current blocking region 105a of No. 05 is located directly above the groove forming region 1a of the substrate 1 and is based on the (111) A plane which is the plane orientation of the slope of the groove 1a1 of the substrate 1 and is based on the p-type dopant Zn. Concentration indicating the conductivity type of 3 × 10 ¹⁸
The area is cm ^-3 . In addition, the current passage region 105b of the current path adjusting layer 105 is located above the flat portion 1b of the substrate 1, and based on the (100) plane that is the plane orientation of the flat portion 1b, the n is formed by the dopant Se. It is a region having a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ which indicates the conductivity type of the mold.

Reference numerals 106a and 106b denote the lower and upper parts of the second current path adjusting layer 105 of the current spreading layer 106, respectively.
6 has a layer thickness of 2.5 μm in the lower portion 106a and an upper portion 106b has a layer thickness of 2.5 μm.

Further, the light emitting diode 100c of the present embodiment.
The manufacturing method of is similar to the manufacturing method of the light emitting diode 100a of the first embodiment except that the second current path adjusting layer 105 is formed during the growth of the current diffusion layer.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the light emitting diode 100c according to this example, LED light having a peak wavelength of 584 nm and a luminous intensity of more than 5.1 cd was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 3 .2 cd
A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, in addition to the current path adjusting layer 5 provided between the n-type upper cladding layer 4 and the current diffusion layer 106, it is formed inside the n-type current diffusion layer 106. Since the second current path adjusting layer 105 is provided,
The current flowing between the n-type electrode 102 and the active layer 3 is blocked by the current path adjusting layer 5 and the current blocking regions 5 a and 105 of the second current path adjusting layer 105 at two points, and the n of the active layer 3 is blocked. Since it spreads to the outside of the region directly below the mold electrode, the current flowing into the active layer 3 can be diffused into a wider range. As a result, the amount of light emission in the portion directly below the n-type electrode of the active layer 3 and in the vicinity thereof decreases, and the amount of light emission in the portion apart from the portion directly below the n-type electrode of the active layer 3 increases. The derivation efficiency of can be improved.

(Embodiment 4) FIG. 6 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a fourth embodiment of the present invention, in which 100d is the light emitting diode of the present embodiment. This light emitting diode 100d uses an n-type GaAs substrate 51 as a substrate. On the n-type GaAs substrate 51, a p-type semiconductor region (current block region) 55a that blocks a current and an n-type semiconductor region that allows a current to pass therethrough. A current path adjusting layer 55 including a (current passage region) 55b is provided.

On the current path adjusting layer 55, a laminated structure having a double heterojunction portion, in which an n-type lower clad layer 52, an active layer 53 and a p-type upper clad layer 54 are sequentially grown on the surface of the current path adjusting layer 55. 150 are provided.

An n-type GaAs contact layer 57 is provided on the laminated structure 150 via a p-type current diffusion layer 56, and a p-type electrode 151 made of AuZn is arranged on the contact layer 57. There is. Also, the n-type GaA
An n-type electrode 152 made of AuGe is formed on the entire back surface of the s substrate 51.

Here, the n-type GaAs substrate 51 has a depth of 4 mm in the circular region (groove forming portion) 51a with a diameter of 200 μm at the center thereof, like the p-type GaAs substrate 1 of the first embodiment. A plurality of V-shaped grooves 51a1 each having a width of 3 μm and a width of 6 μm are formed in a stripe shape, and the region other than the groove forming portion 51a of the substrate 51 has a flat portion 51b having a flat surface.
Has become. The flat portion 51b of the substrate 51 has a surface orientation of (100) plane, and the V-shaped groove 5
The plane orientation of the inclined surface of 1a1 is the (111) A plane.

The constituent material of the current path adjusting layer 55 is (Al _x Ga _1-x ) _1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦
1), the composition ratio of x and y is x = 0.70, y =
0.50, and the layer thickness is 0.7 μm. Zn is used as a group II dopant in the current path adjusting layer 55.
Se is doped as a group dopant. The current blocking region 55a of the current path adjusting layer 55 is the substrate 5
1 just above the groove formation region 51a of the substrate 51, and based on the (111) A plane which is the plane orientation of the slope of the groove 51a1 of the substrate 51, the carrier concentration 3 × 10 showing the p-type conductivity due to the dopant Zn. The area is ¹⁸ cm ^-3 . The current passage region 55b of the current path adjusting layer 55 is located on the flat portion 51b of the substrate 51, and the dopant Se is based on the (100) plane that is the plane orientation of the flat portion 51b.
Carrier concentration showing an n-type conductivity by 3 × 10 ¹⁸ cm
^-3 areas.

The lower clad layer 52 and the active layer 53
And the upper clad layer 54 are (Al _x Ga _{1 -x} ), respectively.
_1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and in the lower cladding layer 52 and the upper cladding layer 54, for example, the composition ratios x and y are x = 0.70, y = 0.50, the layer thickness is 1.0 μm, and Si of the lower cladding layer 52 is
The carrier concentration is 5 × 10 ¹⁷ cm ⁻³ , and the Zn carrier concentration of the upper cladding layer 54 is 1 × 10 ¹⁸ cm ⁻³ . In the active layer 53, for example, the composition ratio x, y is x = 0.30,
y = 0.50, and the layer thickness is 0.50 μm.

Further, the current diffusion layer 56 is made of p-type Al _x.
It is made of Ga _1-x As (0 ≦ x ≦ 1), its composition ratio x is x = 0.70, and has a layer thickness of 5 μm. The p-type current diffusion layer 56 and the p-type GaAs
In the contact layer 57, the Zn carrier concentration is 3 ×.
It is 10 ¹⁸ cm ^-3 .

Next, the manufacturing method will be briefly described.

First, similar to the method of manufacturing the light emitting diode of the first embodiment, the diameter 20 of the surface of the n-type GaAs substrate 51 is 20.
A groove 51a1 having a depth of 4.3 μm and a width of 6 μm in which the plane orientation of the slope is, for example, the (111) A plane is formed in a stripe shape in a 0 μm circular region by etching (FIGS. 1B and 1C). )reference).

Next, the semiconductor layers 55, 52 to 54, 56 are formed on the etched substrate 1 by a single crystal growth step using MOCVD.

That is, after the etching process, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is used as the current path adjusting layer 55 on the substrate 51 with Zn (group II dopant) and Se.
Layer thickness 0.7μ while simultaneously doping (VI group dopant)
Grow about m. At this time, (11
1) In a region where the A surface is exposed, that is, on the groove forming portion 51a of the substrate 51, Zn carrier concentration of 3 × 10 ¹⁸ cm ⁻³ p
The type semiconductor region is formed as the current block region 55a, and the region where the (100) plane is exposed on the surface of the substrate 51,
That is, on the flat portion 1b of the substrate 1, an n-type semiconductor region having a Se carrier concentration of 3 × 10 ¹⁸ cm ⁻³ is provided as the current passage region 55.
formed as b.

After that, on the current path adjusting layer 55,
(Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is grown by controlling its conductivity type and layer thickness, thereby growing the n-type lower clad layer 52 to the current diffusion layer 56, and further p-type. Grow a GaAs layer.

Next, an AuZn layer is formed on the p-type GaAs layer, and an AuGe layer 152 as an n-type electrode is formed on the back surface side of the n-type substrate 51. After that, the p-type GaAs layer and the AuZn layer thereon are selectively etched so that the portion directly above the groove forming portion 51a of the substrate 51 remains, and the p-type GaAs contact layer 57 and the p-type electrode are formed. 151 is formed. As a result, the light emitting diode 100d is completed (see FIG. 6).

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, LED light with a peak wavelength of 584 nm and a luminous intensity of more than 5.4 cd was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 3 .3 cd
A pure green light emission of over 10% was obtained.

In the present embodiment having such a structure, as in the first embodiment, the LE is formed by the current path adjusting layer and the current spreading layer.
The derivation efficiency of D light can be improved. Further, since the semiconductor layer forming the light emitting diode can be continuously formed by one crystal growth step, the manufacturing process can be simplified, the cost can be reduced and the yield can be improved, and the crystal growth can be performed by etching treatment or the like. Therefore, there is no interruption, and deterioration of the crystallinity of the regrowth interface can be avoided, and the characteristics and reliability of the light emitting diode can be kept high.

Further, in this embodiment, since the n-type substrate is used as the substrate of the light emitting diode, the current path adjusting layer 55 consisting of the p-type current block region 55a and the n-type current passing region 55b is laminated on the above. Substrate 5 under structure 150
It can be placed on one surface. For this reason, the plane orientation of the underlying crystal does not deviate when the current path adjusting layer 55 is grown, and selective growth of the p-type current block region 55a and the n-type current passage region 55b depending on the plane orientation of the underlying crystal is performed. ,
It can be satisfactorily performed by sufficiently increasing the carrier concentration in each region. As a result, the function of the current path adjusting layer 55 becomes more effective, the amount of light emission other than the portion directly below the p-type electrode 151 of the active layer 55 increases, and the light extraction efficiency can be further improved.

(Embodiment 5) FIG. 7 is a sectional view for explaining a light emitting diode (semiconductor light emitting device) according to a fifth embodiment of the present invention. In the figure, 100e is the light emitting diode of this embodiment, 6 are the same as those of the light emitting diode 100d of the fourth embodiment, and this light emitting diode 100e is the second n provided between the n-type GaAs substrate 51 and the current path adjusting layer 55. The light emitting diode 100d according to the fourth embodiment is different from the light emitting diode 100d in that the lower mold cladding layer 52a is provided.

Like the n-type lower clad layer 52 between the active layer 53 and the current path adjusting layer 55, the second n-type lower clad layer 52a has a Si carrier concentration of 5 × 10 ¹⁷ cm ⁻³ . It is composed of an n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P layer, and its layer thickness is about 0.5 μm.

The method of manufacturing the light emitting diode 100e of this embodiment is the same as the first embodiment except that the second n-type lower cladding layer 52a is formed on the substrate 51 before forming the current path adjusting layer 5. This is the same as the manufacturing method of the example light emitting diode 100d.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, LED light with a peak wavelength of 584 nm and a luminous intensity of more than 5.8 cd was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 3 .5 cd
A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, n-type Ga is used.
Since the second n-type lower clad layer 52a is provided between the As substrate 51 and the current path adjusting layer 55, the layer thickness of the n-type lower clad layer 52 between the current path adjusting layer 55 and the active layer 53. Can be made as thin as 0.5 μm. As a result, the current once spread by the current block region 55a of the current path adjustment layer 55 can be suppressed from wrapping around the upper side of the current block region 55a, and the current flowing into the portion of the active layer 53 immediately below the p-type electrode 151 can be reduced. It becomes possible. As a result, the amount of light emission in the region other than the portion directly below the p-type electrode of the active layer 53 increases, and the light emitting diode 100 according to the fourth embodiment described above.
The light extraction efficiency can be further improved as compared with d.

(Embodiment 6) FIG. 8 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a sixth embodiment of the present invention. In the figure, 100f is the light emitting diode of this embodiment, The same reference numerals as in FIG. 1 denote the same as the light emitting diode 100a of the first embodiment, and the light emitting diode 100f is arranged between the p-type GaAs substrate 1 and the laminated structure 110 having the double hetero junction. ,
The light emitting diode 100a is provided with a p-type reflective layer 120 that reflects the LED light from the active layer 3 toward the p-type substrate 1 to the active layer 3 side, and the other configurations are the same as those of the light emitting diode 100a of the first embodiment.

The p-type reflective layer 120 has a layer thickness of 0.01 μm.
m GaAs layers and 0.005 μm thick AlInP layers are alternately laminated in 10 pairs, and the layer thickness is 0.1.
It is about 5 μm.

In the method of manufacturing the light emitting diode 100f of this embodiment, the p-type Ga is formed before the p-type lower clad layer 2 is formed.
The manufacturing method of the light emitting diode 100a of the first embodiment is the same as that of the first embodiment except that the p-type reflection layer 120 is formed on the As substrate 1.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, the luminous intensity at a peak wavelength of 585 nm exceeded 6 cd LE.
D light was obtained.

When the composition x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 4 cd. A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, LED light traveling from the active layer 3 to the p-type substrate 1 is directed to the active layer 3 side between the p-type substrate 1 and the laminated structure 110 having the double hetero junction. Since the reflective layer 120 that reflects light is provided, the LED light emitted from the active layer, which is directed toward the substrate side, has a higher refractive index than the laminated structure 110.
Therefore, the light extraction efficiency can be further improved as compared with the light emitting diode 100a according to the first embodiment.

In this embodiment, the reflective layer 120 is made of Ga.
Although the As layer and the InAlP layer are combined, the combination of the semiconductor materials forming the reflective layer 120 is not limited to this, and the L from the active layer 3 toward the p-type substrate 1 is not limited to this.
Needless to say, any other semiconductor material may be used as long as it reflects ED light to the active layer 3 side.

(Embodiment 7) FIG. 9 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a seventh embodiment of the present invention. In the figure, 100 g is the light emitting diode of this embodiment, This light emitting diode 100g is the same as Al _0.7 in the light emitting diode 100a of the first embodiment.
An n-type GaP current diffusion layer 76 having a Si carrier concentration of 5 × 10 ¹⁸ cm ⁻³ is used in place of the Ga _0.3 As current diffusion layer 6.
The n-type electrode 102 is arranged directly on the current diffusion layer 76 so as to face the groove forming portion 1a of the substrate 1. The other structure is the same as that of the light emitting diode 100a of the first embodiment shown in FIG.

In the method of manufacturing the light emitting diode 100g of this embodiment, GaP is grown as the current diffusion layer 76 on the current path adjusting layer 5, and the AuGe layer is grown directly on it.
The AuGe layer is selectively etched so that a portion facing the groove forming portion 1a of the substrate 1 remains, and then the n-type electrode 102 is formed.
The point where the light emitting diode 10 of the first embodiment is formed.
0a is different from the manufacturing method.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, light emission with a peak wavelength of 585 nm exceeding 6 cd was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, a luminous intensity of 4 cd at a peak wavelength of 555 nm was obtained. More than pure green light emission was obtained.

In the present embodiment having such a structure, the n-type current diffusion layer 76 is composed of GaP having a bandgap larger than Al _0.7 Ga _0.3 As. Therefore, the n-type current diffusion layer 6 is composed of Al _0.7 Ga _{0.3 As.} Compared with the light emitting diode 100a of the first embodiment 1 made of As, the absorption of light from the active layer in the current diffusion layer is reduced, the light extraction efficiency is further improved, and the high performance of the semiconductor light emitting device is achieved. Brightness can be achieved.

Further, n is directly formed on the GaP current diffusion layer 76.
Since the mold electrode (AuGe) can be provided, the contact layer is unnecessary and the number of steps can be reduced.

(Embodiment 8) FIG. 10 is a view for explaining an LED according to an eighth embodiment of the present invention, and FIG. 10A is a sectional view showing the structure of the LED, FIG. b) is a cross-sectional view showing a structure of a substrate forming the light emitting diode.

In the figure, reference numeral 100h denotes a light emitting diode of this embodiment, on which an n-type lower clad layer 32, an active layer 33 and a p-type upper clad layer 34 are sequentially grown on an n-type GaAs substrate 31. A laminated structure 130 having a double heterojunction is formed. In this embodiment, on the p-type cladding layer 34 of the laminated structure 130, a p-type semiconductor region (current blocking region) 35a that blocks current and an n-type semiconductor region (current passing region) 35b that allows current to pass therethrough. Current path adjusting layer 35 consisting of
And a second p-type upper cladding layer 34a is disposed on the current path adjusting layer 35. This p
A p-type GaAs contact layer 37 is formed on the upper mold cladding layer 34 a, and the current blocking region 3 of the current path adjusting layer 35 is formed.
The contact layer 3 is provided right above the contact layer 3a.
A p-type electrode 131 made of AuZn is arranged on the surface 7. An n-type electrode 132 made of AuGe is formed on the entire back surface of the n-type GaAs substrate 31.

Here, in the n-type GaAs substrate 31, the circular region 31a having a diameter of 200 μm at the center is a flat portion having a flat surface, and the flat portion 31 of the substrate surface is formed.
The region other than a has a groove forming portion 3 in which a plurality of V-shaped grooves 31b1 having a depth of 2.3 μm and a width of 10 μm are formed in stripes.
1b. The flat surface 31a of the substrate 31 has a surface orientation of (100) surface, and the inclined surface of the V-shaped groove 31b1 has a surface orientation of (311) A surface.

Further, the lower clad layer 32 and the active layer 33 are formed.
And the upper clad layer 34 are (Al _x Ga _{1 -x} )
_1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and in the lower cladding layer 32 and the upper cladding layer 34, for example, the composition ratios x and y are x = 0.70, y = 0.50, the layer thickness is 1.0 μm, and Si of the lower cladding layer 32 is
The carrier concentration is 1 × 10 ¹⁸ cm ⁻³ , and the Zn carrier concentration of the upper cladding layer 34 is 1 × 10 ¹⁸ cm ⁻³ . In the active layer 33, for example, the composition ratio x, y is x = 0.30,
y = 0.50, and the layer thickness is 0.50 μm.

The constituent material of the current path adjusting layer 35 is also (Al _x Ga _1-x ) _1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦
1), the composition ratio of x and y is x = 0.70, y =
0.50, and the layer thickness is 0.7 μm. Zn is used as a group II dopant in the current path adjusting layer 35.
Se is doped as a group dopant. The current blocking region 35a of the current path adjusting layer 35 is formed on the substrate 3
1 located directly above the flat portion 31a of the first flat portion 31a.
Based on the (100) plane, which is the plane orientation of a, the carrier concentration showing the n-type conductivity type by the dopant Se is 3 × 10 ^18.
The area is cm ^-3 . The current passage region 35b of the current path adjusting layer 35 is located above the groove forming portion 31b of the substrate 31, and is based on the (311) A plane which is the plane orientation of the slope of the groove 31b1 of the substrate 31. , Carrier concentration 3 × 10 showing p-type conductivity due to dopant Zn
The area is ¹⁸ cm ^-3 .

Further, the second upper clad layer 34a is
Like the upper cladding layer 34 between the current path adjusting layer 35 and the active layer 33, the Zn carrier concentration is 1 × 10 ¹⁸ cm ^−3.
Is a p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P layer, and the layer thickness is about 1 μm. Also, the p-type G
In the aAs contact layer 37, the Zn carrier concentration is 1 ×
It is 10 ¹⁸ cm ⁻³ and the layer thickness is 1 μm.

Next, the manufacturing method will be described.

First, the surface of the n-type GaAs substrate 31 is etched except for the circular region 31a having a diameter of 200 μm, and the plane orientation of the slope is, for example, the (311) A plane, the depth is 2.3 μm, and the width is 2.3 μm. A plurality of 10 μm grooves 31b1 are formed in stripes (see FIG. 10B).

Next, the substrate 31 subjected to the etching treatment
Each of the semiconductor layers 32 to 35, 34a and 37 is formed on the upper surface by a single crystal growth process using the MOCVD method.

[0186] That is, after the etching process, the n-type _{(Al 0.7 Ga 0.3) 0. 5} In 0.5 P a n-type lower cladding layer 32 on the substrate 31, Si carrier concentration of 1 × 10 ¹⁸
It grows to a thickness of about 1.0 μm so that it becomes cm ⁻³ . Subsequently, (Al _0.3 Ga _0.7 ) _0.5 In _0.5 P is formed as the active layer 33 to a thickness of about 0.50 μm, and p is further formed thereon.
Type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is grown as a p-type upper cladding layer 34 with a layer thickness of about 1 μm so that the Zn carrier concentration is 1 × 10 ¹⁸ cm ⁻³ . At this time, the substrate 3
The surface shape of No. 1 is substantially inherited by the semiconductor layer grown thereon, and in the region corresponding to the groove forming portion 31b of the substrate 31 on the surface of the p-type upper cladding layer 34, the plane orientation of the inclined surface is Is a (311) A plane, and a plurality of grooves are formed on the surface of the clad layer 34 on the substrate 31.
The area corresponding to the flat portion 31a of the
It is a flat region which is the (00) plane.

Further, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P was used as the current path adjusting layer 35 on the surface of the p-type cladding layer 34 as described above, and Zn (group II dopant) was used.
And Se (VI group dopant) are simultaneously doped to grow a layer thickness of about 0.7 μm.

At this time, as described in the first embodiment, in the region where the (311) A plane is exposed on the surface of the cladding layer 34, that is, in the region corresponding to the groove forming portion 31b of the substrate 31, the carrier is removed. A p-type semiconductor region having a concentration of 3 × 10 ¹⁸ cm ⁻³ is formed as the current passage region 35b, and in the region of the surface of the cladding layer 34 where the (100) plane is exposed, that is, in the region corresponding to the flat portion 31a of the substrate 31. , An n-type semiconductor region having a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ is formed as the current block region 35a.

Subsequently, p-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is used as the second p-type upper cladding layer 34a on the current path adjusting layer 35, and the Zn carrier concentration is 1 × 10 ¹⁸ cm 2.
^{To a} thickness of ^-3, and grows to a thickness of about 1 μm.
The Zn carrier concentration is 3 × 10 when the As layer has a thickness of about 1 μm.
Grow to ¹⁸ cm ^-3 .

Next, an AuZn layer is formed on the p-type GaAs layer, and an AuGe layer 132 as an n-type electrode is formed on the back surface side of the n-type substrate 31. After that, p
The p-type GaAs contact layer 37 and the p-type electrode 131 are formed by selectively etching the type GaAs layer and the AuZn layer so that the circular portion located right above the flat portion 31a of the substrate 31 remains. As a result, the light emitting diode 100h is completed (see FIG. 10A).

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, the luminous intensity at a peak wavelength of 585 nm was LE exceeding 4 cd.
D light was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 2 cd. A pure green light emission of over 10% was obtained.

In the semiconductor light emitting device 100h of this embodiment,
The current block region 35a and the current passage region 3 are formed on the laminated structure 130 including the active layer 33 on the n-type GaAs substrate 31.
5b is formed, and the second p-type upper cladding layers 34a and p are formed on the current path adjustment layer 35.
Since the p-type electrode 131 is arranged so as to be located right above the current block region 35a via the type contact layer 37, the current block of the current path adjusting layer 35 is provided between the active layer 33 and the p-type electrode 131. Due to the region 35a, it becomes difficult for current to flow in the portion of the active layer 33 immediately below the p-type electrode 131. As a result, the light emitting region in the active layer 33 is
The LED light generated in the active layer 33 will be efficiently extracted from the region on the surface of the light emitting diode where the p-type electrode 131 is not arranged, so as to spread to the peripheral portion so as to avoid the portion directly below the p-type electrode.

Further, the current path adjusting layer 35, the second p-type upper cladding layer 34a, etc. are (Al _0.7 Ga _0.3 ) _0.5 In _0.5
Since it is composed of P, (Al _0.3 Ga _0.7 ) _0.5 I
The bandgap is wider than that of the active layer 33 made of n _0.5 P. Therefore, the LED light from the active layer 33 is not absorbed by the current path adjusting layer 35 or the second upper cladding layer 34a. As a result, the light extraction efficiency can be further improved and the brightness of the light emitting diode 100h can be increased.

Further, in this embodiment, the n-type GaAs substrate 3 is used.
On the (100) plane of No. 1 except the predetermined circular area (31
1) Selective etching is performed to expose surface A,
Since the plurality of grooves 31b1 are formed in stripes, the laminated structure 13 including the active layer 33 formed on the substrate 31 is formed.
On the surface of 0, that is, the surface of the upper cladding layer 34, the plane orientations of the (311) A plane exposed in the groove forming portion 31b of the substrate and the (100) plane of the flat portion 31a appear.

Further, the region of the device surface corresponding to the current passage region 35b of the current path adjusting layer 35 is uneven because the surface shape of the groove forming region 31b of the substrate 31 is reflected, so that the active layer 33 is formed. The ratio of the LED light that enters the device surface at a critical angle or more from the light emitting region, which is a region immediately below the current passage region 35, is reduced, and the light extraction efficiency from the device surface is improved. Further, since the light emitting region of the active layer 33 is also uneven, the light emitting area is increased as compared with the case where the light emitting region is flat, and the light extraction efficiency is increased.

Furthermore, in the groove forming portion 31b of the substrate 31, since the (311) A plane appears on the slope of the groove 31b1, a natural superlattice is formed even if an AlGaInP mixed crystal semiconductor material is grown on this portion 31b. In this embodiment, the current passage region 35b of the current path adjusting layer 35 is located on the groove forming portion 31b. Therefore, as the active layer 33, an AlGaInP mixed crystal semiconductor material is MOCV
Even if grown by the D method, the natural superlattice is not formed in the light emitting region of the active layer corresponding to the current passage region 35b, and the natural superlattice avoids the lengthening of the LED light. You can Therefore, it is not necessary to increase the Al composition ratio so that LED light having a set wavelength can be obtained, and a light emitting diode having high brightness and high reliability can be obtained.

Moreover, in the present embodiment, AlGaI is doped on the clad layer 34 while being doped with the dopants Zn and Se.
Since nP is growing, Se is on the (100) plane.
A current block region 35a having n-type conductivity is formed, and a current passage region 35b having p-type conductivity is formed of Zn on the (311) A plane. Therefore, in the step of forming the current path adjusting layer 35 having the current block region 35a, the n-type lower cladding layer 34 to the n-type contact layer 37 can be formed by one MOCVD step without interrupting the crystal growth process. It is possible to grow, the manufacturing cost can be reduced, and the yield can be significantly improved.

In addition, it is possible to avoid the deterioration of the characteristics and reliability due to the crystallinity at the regrowth interface in the semiconductor laminated structure forming the light emitting diode.

Further, in the present embodiment, unlike the first to seventh embodiments, the portion of the element surface where the electrodes are arranged is flat, so that the surface of the p-type electrode 131 is It becomes flat, and the adhesion between the p-type electrode 131 and the wire bonded to the p-type electrode 131 can be made good with strong adhesion strength.

(Embodiment 9) FIG. 11 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a ninth embodiment of the present invention, in which 100i is the light emitting diode of the present embodiment. This light emitting diode 100i corresponds to the second light emitting diode 100h of the eighth embodiment.
In place of the p-type upper cladding layer 34a, the p-type current spreading layer 1
It is equipped with 56. The p-type current diffusion layer 156 is A
1 _0.7 Ga _0.3 As and has a Zn carrier concentration of 5
The layer thickness is × 10 ¹⁸ cm ^-3 and 5 μm. Further, here, the p-type Ga arranged on the current diffusion layer 156 is used.
The Zn carrier concentration of the As contact layer 37 is 5 × 10 ^18.
It is cm ^-3 .

The other structure is the same as that of the light emitting diode 100h of the eighth embodiment. In the method for manufacturing the light emitting diode 100i of this embodiment, after the current path adjusting layer 35 is formed, the second p-type (Al _0.7 Ga _0.3 ) layer is formed thereon.
_0.5 In _0.5 P, not the upper cladding layer 34a, but p-type Al
_{A 0.7} Ga _0.3 As current diffusion layer 156 is formed. The other steps are the same as the manufacturing method of the light emitting diode 100h of the eighth embodiment.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, the luminous intensity at a peak wavelength of 585 nm was LE exceeding 5 cd.
D light was obtained.

When the composition x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 2 .5 cd
A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, since the p-type current diffusion layer 156 is provided on the current path adjusting layer 35, the current can be spread also by the p-type current diffusion layer 156, and the active layer It is possible to emit light in a wider area than 33 except the portion corresponding to the p-type electrode 131. As a result, the light extraction efficiency can be improved and the brightness of the semiconductor light emitting device can be increased.

Since the Al _0.7 Ga _0.3 As current diffusion layer 156 has a wider bandgap than the (Al _0.3 Ga _0.7 ) _0.5 In _0.5 active layer 33, light from the active layer is transmitted through the current diffusion layer 156. It is possible to avoid absorption, further improve the light extraction efficiency, and increase the brightness of the semiconductor light emitting device.

(Embodiment 10) FIG. 12 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a tenth embodiment of the present invention. In the figure, 100j is the light emitting diode of this embodiment, This light emitting diode 100j
Then, the current diffusion layer 156 in the ninth embodiment is used as the current diffusion layer 136 having the second current path adjustment layer 135 formed therein, and the second current path adjustment layer 1 is formed.
35 is the current path adjusting layer 35 in the ninth embodiment.
Similarly to the above, the current block region 135a is located immediately below the p-type electrode 131, and the current passage region 135b is located around the current block region 135a.
Further, here, the groove forming portion 31 of the n-type GaAs substrate 31 is formed.
The plane orientation of the slope of the groove 31b1 formed in b is (111) A
It's a face.

[0208] the second current path adjusting layer 135 is also made of doped Zn and _{Se (Al 0.7 Ga 0 .3)} 0.5 In 0.5 P layer, the current passing through region 13 of the current path adjusting layer 135
5b is located above the groove forming portion 31b of the substrate 31 and is the plane orientation of the slope of the groove 31b1 of the substrate 31 (1
11) Based on the A-plane, the region has a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ that exhibits p-type conductivity due to the dopant Zn. The current blocking region 135a of the current path adjusting layer 135 is located right above the flat portion 31a of the substrate 31 and has the plane orientation of the flat portion 31a (10).
Based on the (0) plane, the region has a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ , which exhibits an n-type conductivity due to the dopant Se.

Reference numerals 136a and 136b are the lower and upper parts of the second current path adjusting layer 135 of the current spreading layer 136, respectively.
The layer thickness of the lower portion 136a of the No. 6 is 2.5 μm, and the layer thickness of the upper portion 136b thereof is 2.5 μm.

In addition, the light emitting diode 100j of the present embodiment.
In the manufacturing method of No. 9, except that the second current path adjusting layer 135 is formed during the growth of the current diffusion layer 136,
This is the same as the method for manufacturing the light emitting diode 100i according to the embodiment.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, the luminous intensity at a peak wavelength of 585 nm was LE exceeding 6 cd.
D light was obtained.

When the composition x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 3 cd. A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, in addition to the current path adjusting layer 35 provided between the p-type upper cladding layer 34 and the p-type current diffusion layer 136, the p-type current diffusion layer 136 is also provided.
Since the second current path adjusting layer 135 formed inside is included, the current flowing between the p-type electrode 131 and the active layer 33 is the same as the current path adjusting layer 35 and the second current path adjusting layer 13.
The current blocking regions 35a and 135a of No. 5 are blocked and spread outside the region immediately below the p-type electrode of the active layer 33, so that the current flowing into the active layer 33 can be diffused to a wider range. . As a result, the amount of light emission in the portion directly below the p-type electrode of the active layer 33 and in the vicinity thereof decreases, and the amount of light emission in the portion apart from the portion directly below the p-type electrode of the active layer 33 increases, and the amount of light emission increases. The derivation efficiency of can be improved.

In the method of manufacturing a light emitting diode of this embodiment, since a plurality of semiconductor layers forming the light emitting diode are grown by one MOCVD growth step, re-growth is performed during the growth of the semiconductor layer. There is no such thing. Therefore, a light emitting diode having three or more current path adjusting layers can be easily realized. At this time, the current path adjusting layer may be provided in any portion above the active layer 33.

(Embodiment 11) FIG. 13 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to an eleventh embodiment of the present invention, and FIG. 14 shows a part of a manufacturing process of the light emitting diode. FIG. 14 is a diagram for explaining FIG.
14A is a sectional view of the substrate of the light emitting diode, FIG.
(B) is a cross-sectional view showing a state in which a current path adjusting layer is formed on the substrate. In the figure, reference numeral 100k denotes a light emitting diode of this embodiment, and in this light emitting diode 100k, a p-type GaAs substrate 71 is used as a substrate.
n-type semiconductor regions (current blocking regions) 75a, 75b2, 75b3 that block current on the aAs substrate 71,
P-type semiconductor region (current passage region) 75 for passing an electric current
A current path adjusting layer 75 including b1 is provided.

On this current path adjusting layer 75, a laminated structure having a double heterojunction portion, in which a p-type lower clad layer 74, an active layer 73 and an n-type upper clad layer 72 are sequentially grown on the surface thereof, is formed. 170 is provided.

On this laminated structure 170, n-type Ga is formed.
An As contact layer 77 is provided, and the contact layer 77 is provided.
An n-type electrode 132 made of AuGe is arranged on the top. A p-type electrode 131 made of AuZn is formed on the entire back surface of the p-type GaAs substrate 71.

Here, the p-type GaAs substrate 71 is the same as the n-type GaAs substrate 31 of the eighth embodiment, except for the circular flat portion 71a having a diameter of 200 μm at the center, and the bottom surface of the groove forming portion 71b. A plurality of grooves 71b0 having a depth of 5 μm and a width of 15 μm, each having a 71b1 and a sloped surface 71b2, are formed in stripes at predetermined intervals. The flat portion 71a of the substrate 71, the bottom surface of the groove 71b0, and the adjacent groove 71
The surface portion 71b3 between b0 has a surface orientation of (10
The surface direction of the inclined surface 71b1 of the groove 71b0 is the (111) A surface.

The constituent material of the current path adjusting layer 75 is (Al _x Ga _1-x ) _1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦
1), the composition ratio is x, y is x = 0.70, y = 0.
50, and the layer thickness is 1 μm. The current path adjusting layer 75 is doped with Zn as a group II dopant and Se as a group V dopant. The current blocking region 75a of the current path adjusting layer 75 is formed on the substrate 71.
Of the dopant Se based on the (100) plane which is located directly above the flat portion 75a of the flat portion 75a and is the plane orientation of the flat portion 71a.
Carrier concentration showing an n-type conductivity by 3 × 10 ¹⁸ cm
^-3 areas. Further, the current blocking regions 75b2 and 75b3 of the current path adjusting layer 75 are formed in the grooves 71b, respectively.
Bottom surface of 0 and surface portion 71b3 between adjacent grooves 71b0
Which is located immediately above, and has a carrier concentration of 3 × 10 ¹⁸ cm ⁻³ showing an n-type conductivity type due to the dopant Se based on the plane orientation (100) of these planes.

The current passage region 75b1 of the current path adjusting layer 75 has a slope 71b1 of the groove 71b0 of the substrate 71.
Based on the (111) A plane, which is the plane orientation of, the carrier concentration of 3 × 10 ¹⁸ showing the p-type conductivity type by the dopant Zn.
The area is cm ^-3 .

The lower clad layer 74 and the active layer 73 are also
And the upper clad layer 72 are (Al _x Ga _{1 -x} )
_1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and in the lower cladding layer 74 and the upper cladding layer 72, for example, the composition ratios x and y are x = 0.70, y = 0.50 and the layer thicknesses thereof are 1.0 μm and 3.0 μm, respectively, and the Zn carrier concentration of the lower cladding layer 74 is 1 × 10 ¹⁸ c.
m ⁻³ , the Si carrier concentration of the upper cladding layer 72 is 1 × 10
^{It is 18} cm ^-3 . In the active layer 73, for example, the composition ratios x and y are x = 0.30, y = 0.50, and the layer thickness thereof is 0.50 μm.

Further, the n-type GaAs contact layer 7 is formed.
7, the Si carrier concentration was 3 × 10 ¹⁸ cm ⁻³ and the layer thickness was 1
μm.

Next, the manufacturing method will be briefly described.

First, the surface of the p-type GaAs substrate 71 is etched except for the circular region 71a having a diameter of 200 μm, so that the plane orientation of the slope 71b1 is, for example, (11
1) Depth 5μ with plane orientation of (100) A and bottom
Grooves 71b0 having a width of m and a width of 15 μm are formed in a plurality of stripes (see FIG. 14A).

Next, the substrate 71 subjected to the etching treatment
Each of the semiconductor layers 75, 72 to 74, 77 is formed on the top by a single crystal growth step using the MOCVD method.

That is, after the etching process, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is used as the current path adjusting layer 75 on the substrate 71, and Zn (group II dopant) and Se are added.
A layer thickness of about 1 μm is grown while simultaneously doping (VI group dopant). At this time, in the region where the (100) plane is exposed on the surface of the substrate 71, that is, on the flat portion 71a of the substrate 71, the bottom surface 71b2 of the groove 71b0, and the surface portion 71b3 between the adjacent grooves 71b0, the Se carrier concentration 3 × 10 ¹⁸ c
The n − type semiconductor region of m ⁻³ is the current block regions 75a, 75
b2, 75b3, and (1
11) Area where surface A is exposed, that is, groove 71b0 of substrate 1
Zn carrier concentration 3 × 10 ¹⁸ c on the slope 71 b 1 of
The m ⁻³ p-type semiconductor region is formed as the current passage region 75b1.

After that, on the current path adjusting layer 75,
(Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is grown by controlling its conductivity type and layer thickness, thereby growing the p-type lower clad layer 74 to the n-type upper clad layer 72, and further on that. An n-type GaAs layer is grown.

Next, an AuGe layer is formed on the n-type GaAs layer, and an AuZn layer 131 as a p-type electrode is formed on the back surface side of the p-type substrate 71. After that, the n-type GaAs layer and the AuGe layer on the n-type GaAs layer are selectively etched so that a portion directly above the flat portion 71a of the substrate 71 remains, and the n-type GaAs contact layer 77 and the n-type electrode 132 are formed. To form. As a result, the light emitting diode 100k is completed (see FIG. 13).

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, the luminous intensity at a peak wavelength of 584 nm was LE exceeding 7 cd.
D light was obtained.

When the composition x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 3 .5 cd
A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, as in the above-mentioned embodiments, the LE is constituted by the current path adjusting layer and the current diffusion layer.
The derivation efficiency of D light can be improved. Further, since the semiconductor layer forming the light emitting diode can be continuously formed by one crystal growth step, the manufacturing process can be simplified, the cost can be reduced and the yield can be improved, and the crystal growth can be performed by etching treatment or the like. Therefore, there is no interruption, and deterioration of the crystallinity of the regrowth interface can be avoided, and the characteristics and reliability of the light emitting diode can be kept high.

Further, in this embodiment, since the p-type substrate is used as the substrate of the light emitting diode, the current path adjusting layer 75 composed of the n-type current block regions 75a, 75b2, 75b3 and the p-type current passage region 75b1. Can be disposed on the surface of the substrate 71 below the laminated structure 170. For this reason, the plane orientation of the underlying crystal during the growth of the current path adjusting layer 75 does not deviate, and selective growth of the current blocking regions 75a, 75b2, 75b3 and the current passage region 75b1 depending on the plane orientation of the underlying crystal is performed. The carrier concentration in each region can be made sufficiently high to achieve good performance. As a result, the function of the current path adjusting layer 75 becomes more effective, the amount of light emission other than the portion directly below the n-type electrode 132 of the active layer 73 increases, and the light extraction efficiency can be further improved.

Further, in this embodiment, the groove 71b0 on the surface of the p-type substrate 71 has a structure having a bottom surface 71b2 having a plane orientation of (100), and a region 7 between the adjacent grooves 71b0.
1b3 is also exposed on the (100) plane, and the current path adjusting layer 75 is formed not only in the n-type current block region 75a immediately below the n-type electrode 132 but also in the n-type region around the n-type electrode 132. Since the current block regions 75b2 and 75b3 are arranged in a dispersed manner, the current blocked by the current block region 75a immediately below the p-type electrode and spread to the periphery is expanded to a wider range by the peripheral current block regions 75b2 and 75b3. Can be expanded.

(Embodiment 12) FIG. 15 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a twelfth embodiment of the present invention, in which 100 m is the light emitting diode of the present embodiment. This light emitting diode 100m
Uses an n-type GaAs substrate 81 as a substrate, and on this n-type GaAs substrate 81, an n-type semiconductor region (current block region) 85a that blocks a current and a p-type semiconductor region (current passage region) that allows a current to pass therethrough. ) 85b and a current path adjusting layer 85 are provided.

On the current path adjusting layer 85, a laminated structure having a double heterojunction portion, in which a p-type lower clad layer 84, an active layer 83 and an n-type upper clad layer 82 are sequentially grown on the surface thereof. 180 is provided.

An n-type GaAs contact layer 77 is provided on the laminated structure 180 via an n-type current diffusion layer 86, and an n-type electrode 132 made of AuGe is arranged on the contact layer 77. There is. In addition, the above-mentioned p-type GaA
A p-type electrode 131 made of AuZn is formed on the entire back surface of the s substrate 81.

Here, in the p-type GaAs substrate 81,
Similar to the n-type GaAs substrate 31 of the eighth embodiment, the central circular region 81a with a diameter of 200 μm is a flat surface having a flat surface, and the region other than the flat portion of the substrate surface has a depth. V-shaped groove 81b1 of 2.3 μm and width of 10 μm
Is a groove forming portion 81b formed in a plurality of stripes. The plane portion 81a of the substrate 81 has a surface orientation of (100), and the V-shaped groove 81b1
The plane orientation of the inclined surface is (311) A plane.

The constituent material of the current path adjusting layer 85 is (Al _x Ga _1-x ) _1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦
1), the composition ratio is x, y is x = 0.70, y = 0.
50, and the layer thickness is 1 μm. The current path adjusting layer 85 is doped with Zn as a group II dopant and Se as a group V dopant. The current block region 85a of the current path adjusting layer 85 is formed on the substrate 81.
Of the dopant Se based on the (100) plane that is located directly above the flat portion 81a of the
Carrier concentration showing an n-type conductivity by 3 × 10 ¹⁸ cm
^-3 areas. In addition, the current path adjusting layer 85
The current passage region 85b of the groove 81 is the groove forming portion 8 of the substrate 81.
The dopant Z is located on the upper side of 1b and is based on the (311) A plane which is the plane orientation of the slope of the groove 81b1 of the substrate 81.
Carrier concentration 3 × 10 ¹⁸ c showing p-type conductivity by n
The area is m ^-3 .

Further, the lower clad layer 84 and the active layer 83
And the upper clad layer 82 are (Al _x Ga _{1 -x} ), respectively.
_1-y In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and in the lower cladding layer 84 and the upper cladding layer 82, for example, the composition ratios x and y are x = 0.70, y = 0.50, the layer thickness is 1.0 μm, and Zn of the lower cladding layer 84 is
The carrier concentration is 1 × 10 ¹⁸ cm ⁻³ , and the Si carrier concentration of the upper cladding layer 82 is 1 × 10 ¹⁸ cm ⁻³ . In the active layer 83, for example, the composition ratio x, y is x = 0.30,
y = 0.50, and the layer thickness is 0.50 μm.

Further, the current diffusion layer 86 is made of n-type Al _x.
It is made of Ga _1-x As (0 ≦ x ≦ 1), its composition ratio x is x = 0.70, and has a layer thickness of 5 μm. The n-type current diffusion layer 86 and the n-type GaAs
The contact layer 77 has a Si carrier concentration of 5 ×.
It is 10 ¹⁸ cm ^-3 .

Next, the manufacturing method will be briefly described.

First, as in the eighth embodiment, p
The surface of the type GaAs substrate 81 is etched except for the circular region 81a having a diameter of 200 μm, and the plane orientation of the slope is, for example, the (311) A plane and the depth is 2.3 μm.
Grooves 81b1 having a width of 10 μm are formed in a plurality of stripes (see FIG. 10B).

Next, the substrate 81 subjected to the etching treatment
The semiconductor layers 85, 84, 83, 82, 86, 77 are sequentially formed on the upper surface by a single crystal growth process using the MOCVD method.

That is, after the etching process, (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is used as the current path adjusting layer 85 on the substrate 81, and Zn (group II dopant) and Se are added.
A layer thickness of about 1 μm is grown while simultaneously doping (VI group dopant).

At this time, (100) on the surface of the substrate 81
In the region where the surface is exposed, that is, in the flat portion 81a of the substrate 81, an n-type semiconductor region having a Se carrier concentration of 3 × 10 ¹⁸ cm ⁻³ is formed as the current block region 85a, and the substrate 8
In the region where the (311) A plane is exposed on one surface, that is, in the groove forming portion 81b of the substrate 81, the Zn carrier concentration is 3 × 1.
A 0 ¹⁸ cm ^-3 p-type semiconductor region is formed as the current passage region 85b.

After that, on the current path adjusting layer 85,
(Al _0.7 Ga _0.3 ) _0.5 In _0.5 P is grown by controlling its conductivity and layer thickness, thereby forming the p-type lower clad layer 84 to the n-type upper clad layer 82, and further on that. n-type Al _{0. 7} Ga _0.3 as layer and respectively Si carrier concentration n-type GaAs layer having a thickness of 1μm thickness 5μm is grown so as to be 5 × 10 ¹⁸ cm ^-3.

Next, an AuGe layer is formed on the n-type GaAs layer, and an AuZn layer 131 as a p-type electrode is formed on the back surface side of the p-type substrate 81. Then, the above n
The n-type GaAs contact layer 77 and the n-type electrode 132 are formed by selectively etching the type GaAs layer and the AuGe layer so that the circular portion located right above the flat portion 81a of the substrate 81 remains. As a result, the light emitting diode 100m is completed (see FIG. 15).

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, the luminous intensity at a peak wavelength of 584 nm was LE exceeding 8 cd.
D light was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 4 cd. A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, as in the ninth embodiment, the current path adjusting layer 85 and the current diffusion layer 86 can improve the LED light extraction efficiency. Further, the semiconductor laminated structure in the light emitting diode having the current block region 85a can be continuously formed by one crystal growth step.

Further, in this embodiment, since the p-type substrate is used as the substrate of the light emitting diode, the current path adjusting layer 85 composed of the n-type current block region 85a and the p-type current passing region 85b is laminated as described above. It can be located on the surface of the substrate beneath the structure 180. For this reason, the plane orientation of the underlying crystal on which the current path adjusting layer 85 is grown does not deviate, and the selective growth of the current block region 85a and the current passage region 85b depending on the plane orientation of the underlying crystal is carried out, and the carrier concentration Can be satisfactorily performed by sufficiently increasing As a result, the function of the current path adjusting layer 85 becomes more effective, the amount of light emission other than the portion directly below the n-type electrode of the active layer 83 increases, and the light extraction efficiency can be further improved.

In this embodiment, the current spreading layer 86 is n
Type conductivity type, the mobility is larger than that of the p-type current diffusion layer, and the resistance is reduced, so that the current flows to the n-type of the active layer.
It is possible to expand the portion directly below the mold electrode to a portion further away, and it is possible to further improve the light extraction efficiency.

(Embodiment 13) FIG. 16 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a thirteenth embodiment of the present invention, in which 100n is a light emitting diode of the present embodiment, This light emitting diode 100n
Then, instead of the Al _0.7 Ga _0.3 As current diffusion layer 156 in the ninth embodiment, the Zn carrier concentration is 3 × 10 ¹⁸ c.
A GaP current diffusion layer 97 having a thickness of m ⁻³ and a layer thickness of 5 μm is used.
The p-type electrode 131 is arranged directly on the aP current diffusion layer 97 so as to be located on the flat portion 31 a of the substrate 31. Further, here, the plane orientation of the slope of the groove 31b1 formed in the groove forming portion 31b of the n-type GaAs substrate 31 is (1
11) It is the A side.

In addition, the light emitting diode 100n of this embodiment is
In the manufacturing method of (3), GaP is grown as the current diffusion layer 97 on the current path adjusting layer 35, the AuZn layer is grown directly on it, and the AuZn layer is formed on the flat portion 31a of the substrate 31.
This is different from the manufacturing method of the light emitting diode of the ninth embodiment in that the p-type electrode 131 is selectively etched so that the portion facing to is left.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, LE having a luminous intensity of more than 9 cd at a peak wavelength of 584 nm was obtained.
D light was obtained.

When the composition x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 4 .5 cd
A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, since the n-type current diffusion layer 97 is made of GaP having a large band gap of Al _0.7 Ga _0.3 As, the n-type current diffusion layer is made of Al _0.7 Ga _0.3 As. As compared with the light emitting diode 100j of the ninth embodiment, the absorption of light from the active layer in the current diffusion layer is reduced, the light extraction efficiency is further improved, and the brightness of the semiconductor light emitting device is increased. be able to.

Also, p is directly formed on the GaP current diffusion layer 97.
Since the mold electrode can be provided, the contact layer is not required and the manufacturing process can be simplified.

(Embodiment 14) FIG. 17 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a fourteenth embodiment of the present invention, in which 100p is a light emitting diode of the present embodiment. This light emitting diode 100p
Is disposed between the n-type GaAs substrate 31 and the laminated structure 130 having a double heterojunction portion, and reflects the LED light traveling from the active layer 33 toward the n-type substrate 31 to the active layer 33 side. Is equipped with. The other structure is the same as that of the light emitting diode 100i of the ninth embodiment.

The n-type reflection layer 109 has a layer thickness of 0.01 μm.
m GaAs layers and 0.005 μm thick AlInP layers are alternately laminated in 10 pairs, and the layer thickness is 0.1.
It is about 5 μm.

According to the method of manufacturing the light emitting diode 100p of the present embodiment, the n-type G cladding layer is formed before the n-type lower cladding layer 32 is formed.
The manufacturing method of the light emitting diode 100i according to the ninth embodiment is the same as that of the ninth embodiment except that the n-type reflection layer 109 is formed on the aAs substrate 31.

When a voltage (2 V) was applied in the forward direction and a current (20 mA) was applied to the semiconductor light emitting device according to this example, light emission with a peak wavelength of 585 nm exceeding 10 cd was obtained.

When the compositions x and y of the (Al _x Ga _1-x ) _1-y In _y P active layer were set to x = 0.50 and y = 0.50, respectively, the luminous intensity at a peak wavelength of 555 nm was 5 cd. A pure green light emission of over 10% was obtained.

In this embodiment having such a structure, LED light traveling from the active layer 33 to the n-type substrate 31 is directed to the active layer 33 side between the n-type substrate 31 and the laminated structure 130 having the double heterojunction portion. Since the reflective layer 109 that reflects light is provided, the LED light emitted from the active layer, which is directed toward the substrate, has a higher refractive index than the laminated structure 130.
The light is not absorbed by the s substrate 31 and the light extraction efficiency can be further improved as compared with the light emitting diode 100i of the ninth embodiment.

In the present embodiment, the reflective layer 109 is made of Ga.
Although the As layer and the InAlP layer are combined, the combination of the semiconductor materials forming the reflective layer 109 is not limited to this, and LED light traveling from the active layer 33 to the p-type substrate 31 is reflected to the active layer 33 side. It goes without saying that any other semiconductor material may be used as long as it does.

(Embodiment 15) FIG. 18 is a sectional view for explaining a light emitting diode (semiconductor light emitting element) according to a fifteenth embodiment of the present invention, in which 100q denotes a light emitting diode of the present embodiment. The same reference numerals as those in FIG. 11 denote the same parts as the light emitting diode 100i of the ninth embodiment. In this light emitting diode 100q, a laminated structure 160 having a double heterojunction portion is used in the ninth embodiment.
Instead of the 1GaInP-based mixed crystal semiconductor, it is composed of an AlGaAs-based mixed crystal semiconductor.

That is, n which constitutes the laminated structure 160.
The lower clad layer 62, the active layer 63, and the p-type upper clad layer 64 are each made of Al _x Ga _1-x As (0 ≦ x ≦ 1). In the lower clad layer 62 and the upper clad layer 64, for example, The composition ratio x is x = 0.70, the layer thickness is 1.0 μm, the Si carrier concentration in the lower cladding layer 62 is 1 × 10 ¹⁸ cm ⁻³ , and the Zn in the upper cladding layer 64 is Zn.
The carrier concentration is 1 × 10 ¹⁸ cm ⁻³ . Further, in the active layer 63, for example, the composition ratio x is x = 0.30, and the layer thickness thereof is 0.50 μm.

The other structure is the same as that of the light emitting diode 100i of the ninth embodiment. A voltage (2 V) is applied to the semiconductor light emitting device according to the present embodiment in the forward direction and a current (20 V) is applied.
mA) was emitted, and light emission with a peak wavelength of 660 nm exceeding 30 cd was obtained.

In this embodiment, the laminated structure having the double heterojunction portion is formed by using the AlGaAs mixed crystal semiconductor. However, in the current path adjusting layer made of the AlGaInP semiconductor, the LED emitting light in the active layer is used. No light is absorbed, and the same effect as the ninth embodiment is obtained.

Even if the laminated structure including the double hetero junction is made of a semiconductor material other than AlGaAs or AlGaInP, such as GaInN semiconductor, the same effect as in the above embodiment can be obtained.

The present invention is not limited to the light emitting diodes of the above embodiments. For example, in each of the above embodiments, the AlGaInP layer or the AlGaAs layer whose Al composition is 0.3 or 0.5 is used as the active layer, but by changing this Al composition,
As the LED light emitted from the light emitting diode, it is possible to obtain light emission in the visible light region extending from red to green region.
It goes without saying that the effect of the present invention can be obtained even if the l composition is changed.

The semiconductor material of the active layer is made of AlG.
By changing to another material such as an aInN-based mixed crystal semiconductor, it is possible to obtain light emission in the visible light range from red to blue. In addition, A such as AlGaInN-based mixed crystal semiconductor
By changing the l composition as well, it is possible to obtain light emission in the visible light region ranging from red to blue. Further, the composition ratio and materials of the other semiconductor layers constituting the light emitting diode of each of the above embodiments, that is, the cladding layer, the current path adjusting layer, and the current diffusion layer can be changed, as in the case of the active layer. .

Further, in each of the above-mentioned embodiments, the plane orientation of the inclined surface of the groove is the (311) A plane or the (111) A plane, but as shown in FIG. However, it is needless to say that the conductivity can be controlled to be p-type, and the effect of the present invention can be obtained even if other plane orientations of the A plane are adopted.

Furthermore, in each of the above embodiments, the (100) plane was used as the plane orientation of the flat portion of the substrate for forming the current block region thereon, but as shown in FIG.
Even if the plane is a plane orientation in which the semiconductor layer grown thereon has no p-type conductivity, for example, an n-type or a plane orientation having high resistance, even if it is the A-plane, it is effective. Needless to say. For example, if a high resistance region is formed as the current blocking region, one of the p-type and n-type dopants with which the current path adjusting layer is doped can be reduced. Further, it is needless to say that the shape of the groove forming portion or the flat portion corresponding to the current block region in the center of the substrate is not limited to the circular shape, and the effect of the present invention can be obtained with other shapes.

In each of the above embodiments, the current spreading layer is made of A
l _x Ga _1-x As (0 ≦ x ≦ 1) or (Al _x Ga _1-x ) _1-y
The In _y P (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) layer is adopted,
Other materials may be used as long as they have a band gap that makes them transparent to the light generated in the active layer.

In each of the above embodiments, the GaAs substrate is used as the substrate of the semiconductor light emitting element, but the material of the substrate is G
Not limited to aAs, AlGaAs such as AlGaAs system and GaP
Any compound semiconductor material such as InP-based material and AlGaInN-based material such as GaN may be used, and the effects of the present invention can be obtained for all compound semiconductor materials.

In addition, various modifications can be made without departing from the gist of the present invention.

[0278]

As described above, according to the semiconductor light emitting device of the present invention (Claim 1), the current path adjusting layer is provided between the laminated structure including the active layer and the n-type electrode. Since it is located right under the n-type electrode, the current spreads around the part of the active layer directly under the n-type electrode, reducing the LED light from the active layer that is blocked by the n-type electrode and improving the light extraction efficiency. Therefore, the brightness of the light emitting semiconductor element can be increased.

Further, the p-type compound semiconductor substrate has a groove forming portion in which a groove is formed on the surface thereof, and the plane orientation of the slope of the groove is relative to the plane orientation of the flat portion of the substrate surface. Since the structure has selectivity for the conductivity of the current path adjusting layer containing a predetermined dopant grown on the substrate, the current path adjusting layer is divided into a current block region and a current passing region having different conductivity by selecting the dopant. Therefore, it can be formed in a single crystal growth step.

According to the present invention (claim 2), in the semiconductor light emitting device according to claim 1, the plane orientation of the flat portion of the surface of the compound semiconductor substrate is the (100) plane, and the slope of the groove in the groove forming portion is Since the plane orientation of A is the A plane and the current path adjusting layer has a structure in which the current block region has a p-type conductivity type and the current passage region has an n-type conductivity type, Zn as the p-type dopant of the layer,
By using Se as the n-type dopant, the conductivity of the p-type current block region and the n-type current passage region based on the plane orientation of the substrate can be made to have a high carrier concentration in each region, and the function of the current path adjusting layer can be obtained. Can be made more effective.

According to the present invention (Claim 3), in the semiconductor light emitting device according to Claim 1, an n-type upper cladding layer is also provided between the laminated structure and the current path adjusting layer.
The layer thickness of the n-type upper clad layer forming the double heterojunction portion in the laminated structure can be made thin, and the current flowing into the portion directly below the n-type electrode of the active layer by bypassing the current block region of the current path adjusting layer can be reduced. It will be possible. Therefore,
The amount of light emission in the peripheral region immediately below the n-type electrode of the active layer increases, and the light extraction efficiency can be further improved.

According to the present invention (claim 4), in the semiconductor light emitting device according to claim 1, the current path adjusting layer and n
Since the current diffusion layer is provided between the type electrodes, the current can be spread over a wider range between the n-type electrode arranged on a part of the device surface and the active layer, and the light extraction efficiency can be further improved. Can be improved.

According to the present invention (claim 5), in the semiconductor effect element according to claim 4, in addition to the current path adjusting layer between the laminated structure and the n-type current diffusion layer, Since the current path adjusting layer is also provided inside, it is possible to block the current flowing directly under the n-type electrode of the active layer at two locations, that is, the current blocking areas of the two current path adjusting layers. It is possible to further reduce the current flowing into the portion directly below the n-type electrode of and to spread the current to a wider range outside the portion immediately below the n-type electrode of the active layer. As a result, the light extraction efficiency can be further improved.

According to the present invention (claim 6), in the semiconductor light emitting device according to claim 1, the compound semiconductor substrate having the groove forming portion and the flat portion is made to have n-type conductivity, and the double heterojunction portion is provided. Since the conductivity types of the lower clad layer and the upper clad layer in the laminated structure having the above are n-type and p-type, respectively, the p-type current block region and the n-type lower clad layer are provided between the n-type substrate and the n-type lower clad layer of the laminated structure. It becomes possible to arrange a current path adjusting layer having a mold current passage region. Therefore, the crystal plane of the underlayer does not sag when growing the current path adjusting layer, and the carrier concentration in each region of the current path adjusting layer whose conductivity depends on the plane orientation of the underlayer crystal Can be set to a large value, and the function of the current path adjusting layer can be made effective.

According to the present invention (Claim 7), in the semiconductor light emitting device according to Claim 1 or 6, the current blocking region of the current path adjusting layer is a high resistance region. The doping amount of one of the dopants can be reduced.

According to the present invention (claim 8), in the semiconductor light emitting device according to claim 6, since the n-type cladding layer is provided between the n-type substrate and the current path adjusting layer, the double hetero structure in the laminated structure is provided. The layer thickness of the n-type upper cladding layer forming the junction can be reduced, and the current flowing into the portion directly below the n-type electrode of the active layer can be reduced by bypassing the current block region of the current path adjustment layer. Thereby, the light extraction efficiency can be improved.

According to the present invention (Claim 9), in the semiconductor light emitting device according to Claim 8, a current path adjusting layer and p
Since the current diffusion layer is provided between the type electrodes, the current can be spread over a wider range between the p-type electrode formed on a part of the device surface and the active layer, and the light extraction efficiency can be further improved. It is possible to improve the brightness of the semiconductor light emitting device.

According to the present invention (Claim 10), in the semiconductor light emitting device according to each of the above claims, a reflection layer for reflecting LED light from the active layer is provided between the compound semiconductor substrate and the laminated structure. LED that emits light in the active layer
Of the light, the light traveling toward the substrate side is not absorbed by the substrate having a higher refractive index than the laminated structure, and the light extraction efficiency can be greatly improved.

According to the present invention (Claim 11), in the semiconductor light emitting device according to each of the above claims, a laminated structure having a double heterojunction portion is formed into an (Al _x Ga _1-x ) _1-y In _y P layer. Since it is composed of (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), A
By adjusting the l composition, the LED light can be changed from red to green in the visible light region.

According to the present invention (claim 12), in the semiconductor light emitting device according to any one of claims 1 to 10, the current path adjusting layer is (Al _x Ga _1-x ) _1-y In _y
Since it is composed of the P layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), it is possible to prevent the LED light emitted from the active layer from being absorbed by the current path adjusting layer.

According to the present invention (Claim 13), in the semiconductor light-emitting device according to any one of Claims 1 to 10, the current diffusion layer is made of Al _x Ga _1-x As. LED emitting light from the active layer in the current spreading layer
Light absorption is small, and since the current diffusion layer and the GaAs substrate are lattice-matched, strain due to lattice mismatch is not applied to the laminated structure having the double heterojunction portion, and the semiconductor layer constituting the laminated structure is formed. Also has good crystallinity.

According to the present invention (Claim 14), in the semiconductor light-emitting device according to any one of Claims 1 to 10, the current diffusion layer has a wider bandgap than the Al _x Ga _1-x As. So that (Al _x Ga _1-x ) _1-y In _y
Since it is composed of the P layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1), it is possible to further reduce the absorption of LED light from the active layer in the current diffusion layer and further improve the light extraction efficiency. be able to.

According to the method of manufacturing a semiconductor light-emitting device according to the present invention (claim 15), a groove is formed in a predetermined region of a p-type compound semiconductor substrate, and the conductivity of a semiconductor layer grown on the substrate is improved. , After forming a laminated structure having a double heterojunction portion on the substrate so as to be different depending on the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate,
A current path adjusting layer is grown on the laminated structure so that the current block region and the current passage region are formed depending on the plane orientation of the crystal plane exposed in the groove forming portion and the flat portion. A semiconductor laminated structure of a semiconductor light emitting device having a region can be manufactured by one MOCVD growth step.

Therefore, not only the cost can be reduced and the yield can be improved by simplifying the process, but also
It is possible to eliminate the regrowth interface in the above semiconductor laminated structure, eliminate the problem of crystallinity at the regrowth interface due to oxidation of the regrowth interface, mixing of impurities, etc., and improve the characteristics and reliability of the semiconductor light emitting device. It can be anything.

According to the method of manufacturing a semiconductor light emitting device according to the present invention (claim 16), a groove is formed in a predetermined region of an n-type compound semiconductor substrate, and the conductivity of a semiconductor layer grown on the substrate is improved. , And the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate are made different, and then the current path adjusting layer is formed between the p-type current block region and the n-type current passage region. Since it grows so as to be formed based on the plane orientation of each part of the substrate, a current path adjusting layer in which the carrier concentration of each conductive region depends on the plane orientation of the substrate surface By disposing it on the surface, the carrier concentration of the required conductivity type region can be increased, and the function of the current path adjusting layer can be made effective.

According to the present invention (Claim 17), in the method for manufacturing a semiconductor light emitting device, since Zn is used as the II group dopant and Se is used as the VI group dopant, a current path depending on the plane orientation of the substrate surface is used. The carrier concentration in the p-type current block region and the n-type current passage region of the adjustment layer can be set to be large.

According to the semiconductor light emitting device of the present invention (claim 18), the current path adjusting layer is located on the flat portion of the substrate on the n-type substrate having the groove forming portion and the flat portion. Since the p-type electrode is arranged right above the current block region, the current flowing into the part directly below the p-type electrode of the active layer can be reduced and the current can be widened to a wide range. The efficiency can be improved and the brightness of the semiconductor light emitting device can be increased.

Since the region on the surface of the substrate corresponding to the portion where the p-type electrode is arranged is a flat portion, and the other substrate surface is the groove forming region, the portion where the p-type electrode is arranged on the element surface is formed. Areas other than the area become uneven by reflecting the uneven shape of the groove forming area on the substrate surface. Therefore, in the region where the LED light can be led out on the element surface, the proportion of the LED light incident on the element surface at a critical angle or more is reduced, and the light lead-out efficiency is improved.

Further, since the light emitting region of the active layer, that is, the portion where the current bypasses the current block region is located on the groove forming portion of the substrate, the light emitting region also becomes uneven, and the light emitting region is flat. As compared with the above case, the light emitting area is increased and the light extraction efficiency is increased.

In addition, since the light emitting region of the active layer is located on the groove forming portion on the surface of the substrate where the plane A is exposed, even if an AlGaInP mixed crystal semiconductor system is grown by MOCVD at this portion, GaAs is formed. The formation of a natural superlattice as on the (100) plane of the substrate is suppressed, and the increase in the emission wavelength due to the natural superlattice is suppressed. Therefore, the increase in Al composition for obtaining the set wavelength is reduced, and high brightness is obtained.
A highly reliable semiconductor light emitting device can be realized.

According to the present invention (claim 19), claim 1
In the semiconductor light emitting device according to No. 8, the current path adjusting layer and p
Since the p-type current diffusion layer is provided between the p-type electrode and the p-type electrode, the current can be widely spread around the part directly below the p-type electrode of the active layer, the light extraction efficiency is further improved, and the semiconductor light emitting element Higher brightness can be achieved.

According to the present invention (claim 20), claim 1
In the semiconductor light emitting device according to No. 9, the current path adjusting layer is p
Since it is provided not only on the p-type clad layer but also inside the p-type current diffusion layer, the effect of blocking the current flowing into the part directly below the p-type electrode of the active layer is increased, and the light extraction efficiency is further improved. You can

According to the present invention (claim 21), claim 1
In the semiconductor light emitting device according to No. 8, the compound semiconductor substrate having the groove forming portion and the flat portion has p-type conductivity, and the conductivity types of the lower clad layer and the upper clad layer in the laminated structure having the double hetero junction are set. Each p
Since the p-type substrate and the n-type are used, it is possible to arrange the current path adjusting layer having the n-type current blocking region and the p-type current passage region between the p-type substrate and the p-type lower clad layer of the laminated structure. Therefore, the crystal plane of the underlayer does not sag when growing the current path adjusting layer, and the carrier concentration in each region of the current path adjusting layer whose conductivity depends on the plane orientation of the underlayer crystal Can be set to a large value, and the function of the current path adjusting layer can be made effective.

According to the present invention (claim 22), claim 1
In the semiconductor light emitting device according to 8 or 21, since the current blocking region of the current path adjusting layer is a high resistance region,
The doping amount of one of the first and second dopants can be reduced.

According to the present invention (claim 23), claim 2
In the semiconductor light emitting device according to No. 1, since the current diffusion layer is provided between the laminated structure having the double heterojunction portion and the n-type electrode, the n-type electrode and the active layer formed on a part of the device surface are formed. The current can be spread over a wider range during this period, the light extraction efficiency can be further improved, and the brightness of the semiconductor light emitting device can be increased.

Further, since the conductivity of the current diffusion layer is n-type, the mobility of carriers can be increased as compared with the p-type current diffusion layer, the current spread becomes large, and a portion other than the portion directly under the n-type electrode of the active layer is obtained. In this case, the amount of light emitted from the device increases, and the light extraction efficiency can be further improved.

According to the present invention (claim 24), claim 1
In the semiconductor light-emitting element of any one of 8 to 23, since the light reflection layer is provided between the substrate and the laminated structure having the double heterojunction portion, the light emitted to the substrate side out of the light emitted from the active layer. However, it is possible to avoid absorption by the substrate having a higher refractive index than that of the above laminated structure, and it is possible to further improve the light extraction efficiency.

According to the method for manufacturing a semiconductor light emitting device according to the present invention (claim 25), the surface of the n-type compound semiconductor substrate is processed so as to have selectivity for the conductivity of the semiconductor layer grown thereon. Then, a current path adjusting layer is grown on the substrate so that a current blocking region and a current passing region are formed due to the difference in the plane orientation of the crystal planes exposed on the substrate surface. The device can be manufactured by MOCVD growth once, and problems such as crystallinity at the regrowth interface can be avoided, and significant cost reduction and yield improvement can be achieved.

In addition, a flat surface is exposed in the surface region of the substrate where the current block region is formed, and a slope of the groove formed in the substrate surface is exposed in the portion where the current passing region is formed. Therefore, in the light emitting region of the active layer corresponding to the current passage region, AlGaInP is formed on the GaAs substrate.
The formation of the natural superlattice in the case of growing Cd is suppressed, and it is possible to prevent the emission wavelength from becoming longer due to the natural superlattice.

According to the method for manufacturing a semiconductor light emitting device according to the present invention (claim 26), a groove is selectively formed on the surface of a p-type substrate, and the conductivity of the semiconductor layer grown on the surface of the substrate is increased. Since a current path adjusting layer is formed on the surface of the substrate so as to form a current passage region corresponding to the groove forming portion and a current blocking region corresponding to the flat portion, It is possible to increase the carrier concentration in each conductive type region of the current path adjusting layer without sagging the plane orientation of the underlying layer of the current path adjusting layer, and to make the function of the current path adjusting layer effective. .

According to the present invention (claim 27), in the method for manufacturing a semiconductor light emitting device according to claim 25 or 26, the group II dopant is Zn and the group VI dopant is Se.
Therefore, it is possible to set a large carrier concentration in the p-type current block region and the n-type current passage region of the current path adjustment layer, which depends on the plane orientation of the substrate surface.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a semiconductor light emitting device (light emitting diode) according to a first embodiment of the present invention.
1A is a diagram showing a cross-sectional structure of the light emitting diode, FIG.
1B and 1C are a plan view and a cross-sectional view showing the structure of a substrate that constitutes the light emitting diode.

2 (a) and 2 (b) are views showing a crystal growth step and a metal layer forming step of an electrode in the method for manufacturing the light emitting diode according to the first embodiment.

FIG. 3 is a graph showing the dependence of the carrier concentration of an InGaAlP layer grown by simultaneous doping with Zn and Se on the plane orientation of the underlying surface, as a basic principle of the present invention, by a graph of experimental results.

FIG. 4 is a sectional view showing a structure of a light emitting diode according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a structure of a light emitting diode according to a third embodiment of the present invention.

FIG. 6 is a sectional view showing a structure of a light emitting diode according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view showing a structure of a light emitting diode according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view showing a structure of a light emitting diode according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a light emitting diode according to a seventh embodiment of the present invention.

FIG. 10 is a view for explaining the structure of the light emitting diode and the method for manufacturing the same according to the eighth embodiment of the present invention;
FIG. 10A shows the cross-sectional structure of this light emitting diode as shown in FIG.
Reference numeral 0 (b) shows a cross-sectional structure of a substrate forming the light emitting diode.

FIG. 11 is a sectional view showing a structure of a light emitting diode according to a ninth embodiment of the present invention.

FIG. 12 is a sectional view showing a structure of a light emitting diode according to a tenth embodiment of the present invention.

FIG. 13 is a sectional view showing a structure of a light emitting diode according to an eleventh embodiment of the present invention.

14A and 14B are views for explaining a method for manufacturing a light emitting diode according to the eleventh embodiment, FIG. 14A is a sectional view showing a structure of a substrate used for the light emitting diode, and FIG. It is sectional drawing which shows the state which formed the electric current path adjustment layer on this board | substrate.

FIG. 15 is a sectional view showing a structure of a light emitting diode according to a twelfth embodiment of the present invention.

FIG. 16 is a sectional view showing a structure of a light emitting diode according to a thirteenth embodiment of the present invention.

FIG. 17 is a sectional view showing a structure of a light emitting diode according to a fourteenth embodiment of the present invention.

FIG. 18 is a sectional view showing a structure of a light emitting diode according to a fifteenth embodiment of the present invention.

FIG. 19 is a cross-sectional view for explaining a conventional pn junction type light emitting diode (LED element), FIG. 19 (a) shows a current distribution in the LED element, and FIG. 19 (b) shows the LE.
It shows how to emit light inside the D element.

FIG. 20 is a cross-sectional view showing the structure of a conventional LED element having a current spreading layer.

[Explanation of symbols]

1, 71, 81 p-type GaAs substrate 1a, 31b, 51a, 71b, 81b Groove forming portion 1b, 31a, 51b, 71a, 81a Flat portion 2, 74, 84 p-AlGaInP lower cladding layer 3, 33, 53, 73 , 83 AlGaInP active layer 4, 72, 82 n-AlGaInP upper clad layer 4a n-AlGaInP second upper clad layer 5, 35, 55, 75, 85 Current path adjusting layer 5a, 35a, 55a, 75a, 75b2, 75b3,
85a, 105a, 135a Current block area 5b, 35b, 55b, 75b1, 85b, 105b,
135b Current passage area 6,106 n-AlGaAs current diffusion layer 7,77 n-GaAs contact layer 31,51 n-type GaAs substrate 32,52 n-AlGaInP lower clad layer 34,54 p-AlGaInP upper clad layer 34a p-AlGaInP Second upper cladding layer 37, 57 p-GaAs contact layer 52a n-AlGaInP second lower cladding layer 56, 136, 156 p-AlGaAs current spreading layer 62 n-AlGaAs lower cladding layer 63 AlGaAs active layer 64 p-AlGaAs upper cladding layer Layer 76 n-GaP current diffusion layer 97 p-GaP current diffusion layer 100a to 100k, 100m, 100n, 100p,
100q semiconductor light emitting device 101,131,151 p-type electrode 102,132,152 n-type electrode 105,135 second current path adjusting layer 106a, 136a current diffusion layer lower portion 106b, 136b current diffusion layer upper portion 110, 130, 150, 160, 170, 180 Laminated structure 109, 120 Light reflection layer

Claims (27)

[Claims] 1. A p-type compound semiconductor substrate, and a laminated structure having a double heterojunction portion in which a p-type lower clad layer, an active layer and an n-type upper clad layer are sequentially laminated on the front surface side of the substrate, A current path adjusting layer formed on a laminated structure, comprising a current blocking area for blocking a current and a current passing area for allowing a current to pass therethrough, the current path adjusting layer including first and second dopants having different conductivity types, and the current path adjusting layer. An n-type electrode formed on the upper side of the layer so as to face the current block region, and a p-type electrode formed on the back surface side of the p-type compound semiconductor substrate, the p-type compound semiconductor substrate being A groove forming portion having one or a plurality of grooves formed on the surface, and the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface include a predetermined dopant grown on the substrate. The conductivity of the semiconductor region The current blocking region of the current path adjusting layer is a region formed to have conductivity due to the first dopant due to the plane orientation of the slope of the groove, and the current passing area of the current path adjusting layer The region is a semiconductor light emitting device which is a region formed so as to have conductivity by the second dopant depending on the plane orientation of the flat portion of the substrate. 2. The semiconductor light emitting device according to claim 1, wherein the p-type compound semiconductor substrate has a plane orientation of a flat portion on a surface thereof as a (100) plane, and a plane orientation of a slope of a groove in a groove forming portion thereof. A semiconductor light emitting element in which the current path adjusting layer has a p-type conductivity type and the current passage area has an n-type conductivity type. 3. The semiconductor light emitting device according to claim 1, wherein the second light emitting device is formed between the current path adjusting layer and the n-type electrode.
A semiconductor light emitting device having an n-type upper clad layer. 4. The semiconductor light emitting device according to claim 1, wherein the current path adjusting layer is formed between the current path adjusting layer and the n-type electrode, and the cross-sectional area of the current path on the current path adjusting layer side is on the n-type electrode side. A semiconductor light emitting device having an n-type current diffusion layer that diffuses a current so as to be larger than that of the semiconductor light emitting device. 5. The semiconductor light emitting device according to claim 4, wherein the n-type current diffusion layer has a second current path adjustment layer formed therein, and the second current path adjustment layer. Is a current block region formed so as to have conductivity by the first dopant due to the plane orientation of the slope of the groove in the groove formation region of the p-type compound semiconductor substrate, and a second direction depending on the plane orientation of the flat portion of the substrate. A semiconductor light emitting device comprising a current passage region formed so as to have conductivity by a dopant. 6. An n-type compound semiconductor substrate, first and second conductive types having different conductivity types, which are formed on the front surface side of the substrate and have a current blocking region for blocking a current and a current passing region for passing a current. And a laminated structure having a double heterojunction part, in which an n-type clad layer, an active layer and a p-type clad layer are sequentially laminated on the current path adjustment layer, and a laminated structure of the laminated structure. The n-type compound semiconductor substrate is provided with a p-type electrode formed on the upper side so as to face the current block region of the current path adjusting layer, and an n-type electrode formed on the back surface side of the n-type compound semiconductor substrate. , A groove forming portion having one or more grooves formed on the surface thereof, and the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface are the predetermined dopants grown on the substrate. Of the semiconductor area containing The current blocking region of the current path adjusting layer is a region formed so as to have conductivity by the first dopant due to the plane orientation of the slope of the groove. The current passing region is a region formed so as to have conductivity by the second dopant due to the plane orientation of the flat portion of the substrate. 7. The semiconductor light emitting device according to claim 1, wherein the current blocking region of the current path adjusting layer is a high resistance region. 8. The semiconductor light emitting device according to claim 6, further comprising a second n-type lower clad layer formed between the n-type compound semiconductor substrate and the current path adjusting layer. 9. The semiconductor light emitting device according to claim 8, wherein the cross-sectional area of the current path provided between the laminated structure and the p-type electrode is larger than that on the p-type electrode side. A semiconductor light emitting device having a p-type current diffusion layer for diffusing a current. 10. The semiconductor light emitting device according to claim 1, further comprising a reflective layer formed on the surface of the compound semiconductor substrate and configured to reflect light generated in the active layer. 11. The semiconductor light emitting device according to claim 1, wherein the laminated structure having the double hetero junction is (Al _x
Ga _1-x ) _1-y In _y P semiconductor light-emitting element composed of a P layer (0 ≦ x ≦ 1, 0 ≦ y ≦ 1). 12. The semiconductor light emitting device according to claim 1, wherein the current path adjusting layer is an (Al _x Ga _1-x ) _1-y In _y P layer (0 ≦ x ≦ 1, A semiconductor light emitting device composed of 0 ≦ y ≦ 1). 13. The semiconductor light emitting device according to claim 1, wherein the current diffusion layer is made of Al _x Ga _1-x As (0 ≦ x ≦ 1). 14. The semiconductor light emitting device according to claim 1, wherein the current diffusion layer is an In _y (Ga _1-x Al _x ) _1-y P layer (0.
≦ x ≦ 1, 0 ≦ y ≦ 1) A semiconductor light emitting device. 15. A groove is formed on a predetermined region of a p-type compound semiconductor substrate, and the conductivity of the semiconductor region containing a predetermined dopant grown on the substrate is determined by the plane orientation of the slope of the groove and the substrate. A step of processing the surface of the substrate so that it becomes different depending on the plane orientation of the flat part of the surface, and a p-type lower clad layer, an active layer, and an n-type upper clad layer are sequentially grown on the surface side of the substrate. And forming a laminated structure having a double heterojunction portion, and forming a current path adjusting layer on the laminated structure with a first conductive layer having a different conductivity type.
And a step of growing while simultaneously doping the second dopant, wherein a current blocking region for blocking a current is formed in the current path adjusting layer by the first dopant due to the plane orientation of the slope of the groove. Is formed in a portion of the substrate facing the groove forming portion, and has a current passage region for passing a current,
A method of manufacturing a semiconductor light emitting device, which is formed on a portion of a substrate facing a flat portion other than a groove forming portion so as to have conductivity by a second dopant depending on a plane orientation of the flat portion. 16. A groove is formed on a predetermined region of an n-type compound semiconductor substrate, and the conductivity of the semiconductor region containing a predetermined dopant grown on the substrate is determined by the plane orientation of the slope of the groove and the substrate. A step of processing the surface of the substrate so as to be different depending on the plane orientation of the flat part of the surface; a current path adjusting layer on the surface side of the substrate; and first and second dopants having different conductivity types. Forming a p-type lower clad layer, an active layer, and an n-type upper clad layer in sequence on the current path adjusting layer to form a laminated structure having a double heterojunction. In the current path adjusting layer, a current blocking region for blocking current is provided in a portion facing the groove forming portion of the substrate so as to have conductivity by the first dopant due to the plane orientation of the slope of the groove. Formed and passed through the current The current passage area
A method of manufacturing a semiconductor light emitting device, which is formed on a portion of a substrate facing a flat portion other than a groove forming portion so as to have conductivity by a second dopant depending on a plane orientation of the flat portion. 17. The method for manufacturing a semiconductor light emitting device according to claim 15, wherein the p-type dopant of the first and second dopants is Zn, and the n-type dopant of the both dopants is Zn. Is a method for manufacturing a semiconductor light emitting device, which is Se. 18. An n-type compound semiconductor substrate, and a laminated structure having a double heterojunction portion in which an n-type lower clad layer, an active layer and a p-type upper clad layer are sequentially grown on the front surface side of the substrate, A current path adjusting layer formed on a laminated structure, comprising a current blocking area for blocking a current and a current passing area for allowing a current to pass therethrough, the current path adjusting layer including first and second dopants having different conductivity types, and the current path adjusting layer. A p-type electrode formed on the upper side of the layer so as to face the current blocking region, and an n-type electrode formed on the back side of the n-type compound semiconductor substrate, the n-type compound semiconductor substrate having a surface thereof. Has a groove forming portion in which a groove is formed, and the plane orientation of the inclined surface of the groove and the plane orientation of the flat portion of the substrate surface make the conductivity of the semiconductor region containing a predetermined dopant grown on the substrate. To rule The current blocking region of the current path adjusting layer is a region formed to have conductivity by the first dopant due to the plane orientation of the flat portion of the substrate, and the current passing region of the current path adjusting layer is the groove. A semiconductor light emitting device, which is a region formed so as to have conductivity by the second dopant depending on the plane orientation of the slope. 19. The semiconductor light emitting device according to claim 18, wherein the current path adjusting layer is formed between the current path adjusting layer and the p-type electrode, and a cross-sectional area of the current path on the current path adjusting layer side is on the p-type electrode side. A semiconductor light emitting device having a p-type current diffusion layer that diffuses a current so as to be larger than that of the semiconductor light emitting device. 20. The semiconductor light emitting device according to claim 19, wherein the p-type current diffusion layer has a second current path adjusting layer formed therein, and the second current path adjusting layer. Is a current block region formed so as to have conductivity by the first dopant due to the plane orientation of the flat portion of the n-type compound semiconductor substrate, and a second direction depending on the plane orientation of the slope of the groove in the groove formation region of the substrate. A semiconductor light emitting device comprising a current passage region formed so as to have conductivity by a dopant. 21. A first and second p-type compound semiconductor substrate, different in conductivity type, each of which is composed of a p-type compound semiconductor substrate, a current block region formed on the front surface side of the substrate for blocking a current, and a current passage region for allowing a current to pass therethrough. And a p-type lower cladding layer, an active layer, and an n-type current path adjusting layer on the current path adjusting layer.
A laminated structure having a double heterojunction part formed by sequentially growing an upper cladding layer, an n-type electrode formed on the upper side of the laminated structure so as to face the current block region of the current path adjusting layer, and the p-type A p-type electrode formed on the back surface side of the compound semiconductor substrate, wherein the p-type compound semiconductor substrate has a groove formation portion in which a groove is formed on the surface thereof, and the plane orientation of the inclined surface of the groove and the substrate. The plane orientation of the flat portion of the surface governs the conductivity of the semiconductor region containing a predetermined dopant grown on the substrate, and the current blocking region of the current path adjusting layer is the flat portion of the substrate. It is a region formed so as to have conductivity by the first dopant depending on the plane orientation, and the current passage region of the current path adjusting layer is formed so as to have conductivity by the second dopant depending on the plane orientation of the slope of the groove. In the area Semiconductor light emitting device. 22. The semiconductor light emitting device according to claim 18, wherein the current blocking region of the current path adjusting layer is a high resistance region. 23. The semiconductor light emitting device according to claim 21, wherein the cross-sectional area of the current path provided between the laminated structure and the n-type electrode is larger than that on the n-type electrode side. A semiconductor light emitting device having an n-type current diffusion layer for diffusing a current. 24. The semiconductor light emitting device according to claim 18, further comprising a reflective layer formed on the surface of the compound semiconductor substrate and configured to reflect the light generated in the active layer. 25. A groove is formed on a predetermined region of an n-type compound semiconductor substrate, and the conductivity of a semiconductor region containing a predetermined dopant grown on the substrate has a conductivity of the slope of the groove and the substrate. A step of processing the surface of the substrate so as to be different depending on the plane orientation of the flat part of the surface, and an n-type lower clad layer, an active layer, and a p-type upper clad layer are sequentially grown on the surface side of the substrate. And forming a laminated structure having a double heterojunction portion, and forming a current path adjusting layer on the laminated structure with a first conductive layer having a different conductivity type.
And a step of simultaneously forming a second dopant while forming a current blocking region in the current path adjusting layer, the current blocking region having conductivity of the first dopant due to the plane orientation of the flat portion. It is formed in a portion of the substrate that faces the flat portion other than the groove forming portion, and the current passage region through which the current is passed has conductivity of the second dopant due to the plane orientation of the slope of the groove. A method for manufacturing a semiconductor light emitting device, which is formed in a portion facing a groove forming portion. 26. A groove is formed on a predetermined region of a p-type compound semiconductor substrate, and the conductivity of the semiconductor region containing a predetermined dopant grown on the substrate has a plane orientation of a slope of the groove and a surface of the substrate. And a current path adjusting layer is formed on the surface side of the substrate while simultaneously doping the first and second dopants having different conductivity types. And a step of sequentially growing a p-type lower clad layer, an active layer, and an n-type upper clad layer on the current path adjusting layer to form a laminated structure having a double heterojunction portion. A current blocking region for blocking current is formed in the path adjusting layer in a portion facing the flat portion other than the groove forming portion of the substrate so as to have conductivity by the first dopant due to the plane orientation of the flat portion. Passed through the current A method for manufacturing a semiconductor light emitting device, wherein a current passage region to be formed is formed in a portion facing the groove forming portion of the substrate so as to have conductivity by the second dopant due to the plane orientation of the slope of the groove. 27. The method for manufacturing a semiconductor light emitting device according to claim 25, wherein the p-type dopant of the first and second dopants is Zn, and the n-type dopant of the two dopants is Se. And a method for manufacturing a semiconductor light emitting device.