JPH06151714A - Supplying circuit for bias voltage of active device - Google Patents

Abstract

PURPOSE:To miniaturize a circuit by reducing the kinds of electrodes by a method wherein a via hole is provided as far as to the surface of a dielectric substrate from the electrode of an active device, an earthing surface is formed by laminating a dielectric layer on the end part of the via hole, the earthing surface is earthed, and a self-bias application structure is formed. CONSTITUTION:The first via hole 21 is provided from directly below the source electrode S of the FET 13 provided on one surface of a dielectric substrate 41 to the other surface of the dielectric substrate. A dielectric layer 31 is laminated on the end part of the first via hole on the other surface, the first metal layer is laminated on the above-mentioned laminated layer, and an earthing surface 51 is formed. As a result, the source electrode is earthed at high frequencies and at the same time, it is connected to the earthing surface through the intermediary of a self-biasing drain resistor R. Drain voltage is applied to a drain D through a choke, a gate G is earthed through a resistor, and as the FET is self-biased by the resistor R1 the use of one electrode is enough, and the circuit can be made small in size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias voltage supply circuit for active devices used in radio equipment.

Generally, a device, a circuit pattern, an input / output matching circuit, etc. are formed on a dielectric substrate using GaAs to make functional parts such as amplification and frequency conversion. In the case of an amplification circuit using FET, , When using the configuration in which voltage is applied to the gate and drain and the source is grounded, two power supplies are required, the circuit configuration becomes complicated, and operating point adjustment for setting the operating point of the FET is required. Becomes

Therefore, it is necessary to reduce the size of the circuit by using one power source.

[0004]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example. (A) is a cross-sectional view of an essential part of a pattern including an FET formed on a dielectric substrate cut in parallel with an input / output terminal of the FET, (b) is Via hole (V
An enlarged cross-sectional view near IA), and (c) is an example of a circuit diagram of the main part.

Hereinafter, FIG. 5 will be described. First, in order to miniaturize the active device used in the conventional monolithic microwave integrated circuit (MMIC), Japanese Patent Laid-Open No. 63-244
As shown in FIG. 1 of 761, the structure is such that a capacitor is formed under a pattern formed on a dielectric substrate (GaAs substrate).

On the other hand, in the case of an amplifier using a FET, for example, as shown in FIG. 5 (c), the source is grounded, and the gate voltage and the drain are connected to the gate voltage via a choke ch whose one end is grounded by a capacitor C. A dual power supply system having a configuration of applying a drain voltage may be adopted.

At this time, as shown in FIGS. 5A and 5B, the source (S) of the FET 13 provided on the GaAs dielectric substrate 11 is the via holes 14 and 16 and the dielectric substrate dielectric. It is connected to the ground plane 12 through the dielectric layers 15 and 17 having a dielectric constant larger than the dielectric constant, but in the super high frequency band such as the millimeter wave band, the source electrode
(S) - mounting portion 18a, 18B- parasitic inductances L _14, L ₁₆ (not shown) occurs for consisting the through hole line, via the capacitance of the parasitic inductance component (not shown) and the dielectric layer contacting Connected to the ground 12.

Therefore, the grounding is incomplete and the gain is lowered. In addition, FE is applied by applying voltage to the gate and drain separately.
Since the operating point of T is determined, it is necessary to adjust it so that it becomes a predetermined operating point.

Since the through holes 14 and 16 are formed by etching, the lower portion is wider than the upper portion as shown in the figure, and the inner surface is metalized to connect the front surface and the back surface of the dielectric substrate. In addition, if the upper outline of the via hole is, for example, 100 microns, the lower outline is 20
It becomes about 0 micron, and a certain amount of space is required to provide another via hole near the via hole.

[0010]

As described above, in the super high frequency band, a parasitic inductance is generated in the line from the source electrode (S) to the via hole exit, resulting in incomplete grounding.

Further, when the gate voltage and the drain voltage are supplied from different power sources, a certain space is required so that the two via holes do not overlap each other, and it is difficult to miniaturize the circuit. Therefore, there are two problems that the types of power sources must be reduced in order to miniaturize the circuit.

[0012]

According to the first aspect of the present invention, a first via hole is provided from directly below an electrode (S) to be grounded of an active device to the other surface of the dielectric substrate. A dielectric layer is laminated on the end portion of the electrode, a first metal layer is further laminated on the laminated dielectric layer to form a ground plane, and the electrode is grounded at high frequency and a self-bias voltage is applied It was configured to do. As a result, there is only one type of power source, and the size of the circuit can be reduced.

In a second aspect of the present invention, the first surface of the dielectric substrate is directly below the electrode (S) to be grounded of the active device and the first surface of the dielectric substrate is separated from the electrode by a predetermined distance or more. , The second via hole is provided, and the first and second surfaces of the other surface are provided.
Connecting the ends of the via holes to each other with a laminated second metal film, laminating a dielectric layer on the first and second via holes and the laminated second metal film, and laminating the laminated dielectric. A third metal layer is further laminated on the layer to form a ground plane, which is grounded at a high frequency with respect to the electrode, and a self-bias voltage is applied through the second via hole.

In the third aspect of the present invention, by connecting the first and second via holes with a resistance element, the attenuation amount in the required band is made larger than that in the case of the first via hole. In the fourth invention, diamond is used as the laminated dielectric.

In the fifth aspect of the present invention, the ground plane on which the third metal layer is laminated is raised to shorten the through hole length of the first and second via holes to a predetermined value or less to reduce the parasitic inductance. Reduced.

[0016]

According to the first aspect of the present invention, an active device such as an FET is provided.
A first via hole is provided under the source electrode of, a dielectric layer is laminated on the end of the first via hole on the opposite side of the source electrode, and a first metal layer is further formed on the laminated dielectric layer. The grounded surface is formed by stacking and the source electrode is grounded at high frequency. In addition, a resistance is added to the source electrode of the FET to give it a higher DC potential than the gate to operate the FET (apply a self-bias voltage).

That is, since the bias circuit is connected to a place which is grounded in terms of high frequency, it is less susceptible to the bias power supply connection. In the second aspect of the present invention, first and second via holes are provided from directly below the source electrode of the FET and from the dielectric substrate on the side of the source electrode which is separated from the electrode by a predetermined distance or more to the other surface of the dielectric substrate.

Then, the first and second via holes provided on the other surface are connected to each other by a laminated second metal film, and the first and second via holes and the formed second metal are formed. A dielectric layer is laminated on the film, and a third metal layer is further laminated on the laminated dielectric layer to form a ground plane. As a result, the electrode is grounded at a high frequency, but in terms of direct current, a self-bias voltage can be applied via the second via hole.

In the third aspect of the present invention, the attenuation amount in the required band is made larger than that in the case of the first via hole by connecting the first and second via holes with the resistance element. In the fourth aspect of the present invention, diamond is used as the laminated dielectric. Furthermore, in the fifth aspect of the present invention, the ground plane on which a metal layer is laminated is raised to shorten the through hole length of the first and second via holes to a predetermined value or less to reduce the parasitic inductance.

[0020]

FIG. 1 is a block diagram of the first embodiment of the present invention.
(a) is a pattern including a FET formed on a dielectric substrate
FIG. 3B is a cross-sectional view of a main part cut in parallel with the input / output terminal of, and FIG. FIG. 2 is a block diagram of a second embodiment of the present invention, in which (a) is a cross-sectional view of a main part of a pattern including an FET formed on a dielectric substrate cut in parallel with the input / output terminals of the FET, (b). Is an example of an equivalent circuit diagram.

FIG. 3 is a block diagram of the third and fourth embodiments of the present invention, in which (a) is a main part obtained by cutting a pattern including an FET formed on a dielectric substrate in parallel with the input / output terminals of the FET. Cross section,
(b) is an example of an equivalent circuit diagram. FIG. 4 is a block diagram of the fifth embodiment of the present invention, in which a FET formed on a dielectric substrate is used.
FIG. 4 is a cross-sectional view of a main part, in which a pattern including is cut parallel to the input / output terminals of the FET.

The same reference numerals denote the same objects throughout the drawings. Hereinafter, FIGS. 1 to 4 will be sequentially described. Figure 1 (a)
In, for example, a first via hole 21 is provided from directly below the source electrode (S) of the FET 13 provided on one surface of the dielectric substrate 41 using GaAs to the other surface of the dielectric substrate.
Then, the dielectric layer 31 is laminated on the end portion of the first via hole on the other surface, and the first dielectric layer 31 is further formed on the laminated dielectric layer.
The metal layers are laminated to form the ground plane 51.

As a result, the source electrode is grounded at a high frequency and is also connected to the ground plane via the resistor R for self-bias. Here, FIG. 1 (b) shows the equivalent circuit of FIG. 1 (a), but as shown in FIG. 1 (b), a parasitic inductance L ₂₁ is generated by the first via hole (directly on the source electrode, Since it is connected, it is smaller than the conventional example), and is grounded via the capacitance C ₃₁ of the laminated dielectric layers.
Complete grounding is difficult in the millimeter wave band.

The drain voltage is applied to the drain (D) via the choke, the gate (G) is grounded via the resistor, and the FET is self-biased by the resistor R _1, so only one power supply is required. The circuit is miniaturized.

FIG. 2 (a) shows directly below the source electrode of the FET 13,
The first and second via holes 22, from one surface of the dielectric substrate 42 separated from the source electrode by a predetermined distance to the other surface,
23 is provided, and the end portions of the first and second via holes on the other surface are connected to each other by a second metal film 24 that is laminated.

Then, a dielectric layer 32 is laminated on the first and second via holes and the formed second metal film, and a third metal layer is laminated on the laminated dielectric to form the ground plane 52. Form. 2 (b) is an equivalent circuit of the configuration of FIG. 2 (a). By providing the second metal film 24, the inductance L ₂₄ is equivalently provided. The inductance due to the two via holes is shown in FIG. capacity by dielectric layer laminated with L _22, L ₂₃
A low-pass filter is formed by C ₃₂₁ and C _322, and the cutoff frequency becomes low and the attenuation amount at the time of high-frequency grounding becomes large.

In the case of a circuit with a large source current, MM
The amount of heat generated by the resistor R ₂ included in the IC may be large and burned. In such a case, the large amount of heat generated can be dealt with by providing the resistor R ₂ outside through the second via hole.

2 (a) and 2 (b), the metal film 24
Although the ends of the first and second via holes on the other surface were connected to each other via, the first and second via holes were connected by the resistor R ₃ as shown in Fig. 3 (a).
The second via hole is connected. Equivalent circuit at this time is shown in FIG. 3 (b), the capacitor C ₃₃₂ is a capacitor
Since the capacitance value than C ₃₃₁ is very large, when the frequency is high is grounded by the capacitor C _331, when a low resistance R ₃
Grounded at.

Further, since heat is cut off in the dielectric layer, heat is accumulated. Therefore, if the dielectric layer is composed of diamond, since diamond has a high withstand voltage and high purity, ionized substances do not flow in, and the advantage that the required grounding capacitance can be obtained is obtained.

FIG. 4 shows that by raising the ground plane 53,
The parasitic inductance due to the via hole is suppressed. As mentioned above, since there is a via hole directly under the source of the FET, it contributes to the stable operation of the circuit by reducing the parasitic inductance and reliable high-frequency grounding as compared with the past. Moreover, since only one power supply is required, the size of the entire device can be reduced.

[0031]

As described above in detail, according to the present invention, it is possible to reduce the kinds of power sources.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention, in which (a) is a cross-sectional view of a main part obtained by cutting a pattern including an FET formed on a dielectric substrate in parallel with an input / output terminal of the FET, ) Is an example of an equivalent circuit diagram.

FIG. 2 is a configuration diagram of a second embodiment of the present invention, (a) is a cross-sectional view of a main part of a pattern including a FET formed on a dielectric substrate cut in parallel with an input / output terminal of the FET, ) Is an example of an equivalent circuit diagram.

FIG. 3 is a configuration diagram of the third and fourth embodiments of the present invention, (a)
Is a cross-sectional view of a main part in which a pattern including a FET formed on a dielectric substrate is cut parallel to the input / output terminals of the FET, and (b) is an example of an equivalent circuit diagram.

FIG. 4 is a constitutional view of a fifth embodiment of the present invention, which is a cross-sectional view of essential parts in which a pattern including an FET formed on a dielectric substrate is cut in parallel with an input / output terminal of the FET.

FIG. 5 is a configuration diagram of a conventional example, in which (a) is a cross-sectional view of an essential part obtained by cutting a pattern including an FET formed on a dielectric substrate in parallel with the input / output terminals of the FET, and (b) is a via hole (VIA). ) Is an enlarged cross-sectional view of the vicinity, and (c) is an example of a main circuit diagram.

[Explanation of symbols]

13 Active device 21, 22 First via hole 23 Second via hole 31, 32, 33 Dielectric layer 41 Dielectric substrate 51, 52, 53 Ground plane

Claims (5)

[Claims] 1. A bias voltage supply circuit for an active device (13) formed on one surface of a dielectric substrate (41), wherein from the position directly below an electrode (S) to be grounded of the active device, to the other side of the dielectric substrate. First via hole (21) is provided up to
A dielectric layer (31) is laminated on the end of the first via hole on the other surface, and a first metal layer is further laminated on the laminated dielectric layer to form a ground plane (51), A bias voltage supply circuit for an active device, wherein the electrode is grounded at a high frequency through the laminated dielectric layers and a self-bias voltage is applied. 2. In the bias circuit for an active device as described above, from directly below an electrode (S) to be grounded of the active device and from one surface of the dielectric substrate separated from the electrode by a predetermined distance or more,
On the other surface of the dielectric substrate, first and second via holes (2
2, 23) are provided, the end portions of the first and second via holes on the other surface are connected to each other by a laminated second metal film (24), and
A dielectric layer (32) is laminated on the second via hole and the laminated second metal film, and a third metal layer is further laminated on the laminated dielectric layer to form a ground plane (52). A bias voltage supply circuit for an active device configured to apply high-frequency ground to the electrode via the laminated dielectric layers and to apply a self-bias voltage via the second via hole. 3. A bias voltage supply for an active device according to claim 2, wherein the first and second via hole ends of the other surface of the dielectric substrate are connected to each other by a resistance element (R ₃ ). circuit. 4. A bias voltage supply circuit for an active device according to claim 1, wherein the laminated dielectric layers are formed of diamond. 5. The grounding surface (53) is raised to make
5. A bias voltage supply circuit for an active device according to claim 2, wherein the length of the second via hole is shortened to a predetermined value or less.