JPH06151711A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06151711A
JPH06151711A JP4316610A JP31661092A JPH06151711A JP H06151711 A JPH06151711 A JP H06151711A JP 4316610 A JP4316610 A JP 4316610A JP 31661092 A JP31661092 A JP 31661092A JP H06151711 A JPH06151711 A JP H06151711A
Authority
JP
Japan
Prior art keywords
storage electrode
etching
polycrystalline
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4316610A
Other languages
Japanese (ja)
Inventor
Takeshi Tokashiki
健 渡嘉敷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4316610A priority Critical patent/JPH06151711A/en
Publication of JPH06151711A publication Critical patent/JPH06151711A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a polycrystalline Si storage electrode with a roughened surface. CONSTITUTION:An oxide film 2 and a polycrystalline Si layer 3 are successively grown on an Si substrate 1, and after a mask 4 has been formed by optical lithography, an anisotropic storage electrode 5 is formed by dry-etching. Then, the surface of the anisotropically etched storage electrode can be reprocessed into a storage electrode 6 having semispherical rugged shape by making accumulation reaction of dry etching compete with reaction of etching.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置、特に蓄積
電極の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method of forming a storage electrode.

【0002】[0002]

【従来の技術】従来、DRAMの蓄積電極部、またはキ
ャパシタの構造の代表例として、積み上げ型蓄積電極が
ある。限られた面積内に多数の十分大きな蓄積容量を確
保するためのひとつに、電極面積を利用する方法がある
が、面積を確保するためには、蓄積電極を高くしなけれ
ばならない。
2. Description of the Related Art Conventionally, there is a stack type storage electrode as a typical example of the structure of a storage electrode portion of a DRAM or a capacitor. One way to secure a large number of sufficiently large storage capacitors in a limited area is to use the electrode area, but in order to secure the area, the storage electrode must be made high.

【0003】しかし、単純にこの方法を使うと、メモリ
セル部と周辺回路部との間に大きな段差が生じ、これが
光リソグラフィー工程でのフォーカスマージンより大き
くなると、精度の高いマスク形成ができないという問題
が生じる。よって、むやみに蓄積電極の高さを増すこと
はできない。
However, if this method is simply used, a large step is formed between the memory cell section and the peripheral circuit section, and if this step becomes larger than the focus margin in the photolithography process, it is impossible to form a mask with high accuracy. Occurs. Therefore, the height of the storage electrode cannot be unnecessarily increased.

【0004】そこで、次のように蓄積電極の形状を工夫
して表面積を増やす方法が考えられる。LPCVD法を
用い、積み上げ型蓄積電極全面に半球状の凹凸形状を有
する多結晶Siを成長させて表面を凹凸形状とし、蓄積
電極の凹凸形状を保ちながら、この多結晶Siをドライ
エッチングし、それぞれの蓄積電極を分離する。
Therefore, a method of increasing the surface area by devising the shape of the storage electrode can be considered as follows. Using the LPCVD method, polycrystalline Si having a hemispherical uneven shape is grown on the entire surface of the stacked storage electrode to form an uneven surface, and the polycrystalline Si is dry-etched while maintaining the uneven shape of the storage electrode. Separate the storage electrodes of.

【0005】しかしながら、この半球状の凹凸形状を有
する多結晶Siの成長温度は、550℃と極めて温度範
囲が限られているので、再現性に関して問題がある。
However, the growth temperature of the polycrystalline Si having the hemispherical concavo-convex shape is extremely limited to 550 ° C., so that there is a problem in reproducibility.

【0006】図1に多結晶Si堆積温度と多結晶Siで
積み上げ型蓄積電極の下部電極に用いた時の蓄積電荷量
の関係を示す。550℃付近で堆積し、多結晶Siを下
部電極に使用すると、蓄積電荷量が2倍程度増えている
が、その温度範囲は極めて狭い。
FIG. 1 shows the relationship between the polycrystalline Si deposition temperature and the amount of accumulated charge when the polycrystalline Si is used for the lower electrode of the stack type accumulation electrode. When polycrystal Si is deposited at around 550 ° C. and polycrystalline Si is used for the lower electrode, the accumulated charge amount is about doubled, but the temperature range is extremely narrow.

【0007】[0007]

【発明が解決しようとする課題】以上述べたように、L
PCVD法では、半球状の凹凸形状を有する多結晶Si
を成長させる温度は、極めて限られている。そのため、
高精度の温度制御が必要とされるが、シリコン基板面積
の大口径化に伴い、基板面内での均一な温度制御が難し
くなる。その結果、大きな蓄積容量をもつ半導体装置の
製造の歩留りが低下する可能性がある。
As mentioned above, L
In the PCVD method, polycrystalline Si having a hemispherical uneven shape is used.
The temperature at which to grow is very limited. for that reason,
Although highly accurate temperature control is required, it becomes difficult to control the temperature uniformly in the substrate surface as the silicon substrate area increases. As a result, the manufacturing yield of a semiconductor device having a large storage capacity may decrease.

【0008】本発明の目的は、従来のLPCVD法を用
いず、ドライエッチングによる半球状の凹凸形状を有す
る多結晶Siを形成し、大きな蓄積容量をもつ半導体装
置の製造方法を提供することにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device having a large storage capacity by forming polycrystalline Si having a hemispherical uneven shape by dry etching without using the conventional LPCVD method. .

【0009】[0009]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体装置の製造方法は、電極形成工
程とエッチング加工工程とを有する半導体装置の製造方
法であって、電極形成工程は、半導体基板上に異方性形
状の蓄積電極を形成するものであり、エッチング加工工
程は、上記蓄積電極表面を半球状の凹凸形状にドライエ
ッチング加工するものである。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an electrode forming step and an etching processing step, wherein the electrode forming step is The anisotropic storage electrode is formed on the semiconductor substrate, and the etching process is a dry etching process of the storage electrode surface into a hemispherical uneven shape.

【0010】[0010]

【作用】異方的に蓄積電極をドライエッチングした後、
ドライエッチングの堆積反応とエッチング反応とを競合
させることにより、異方的にエッチングされた蓄積電極
の表面を、半球状の凹凸形状を有する蓄積電極に再加工
することができる。
[Function] After anisotropically dry-etching the storage electrode,
By competing the deposition reaction and the etching reaction of dry etching, the surface of the anisotropically etched storage electrode can be reprocessed into a storage electrode having a hemispherical uneven shape.

【0011】[0011]

【実施例】以下、本発明の実施例を図面を用いて説明す
る。図2(a)〜(c)は、本発明の一実施例を説明す
るための半導体チップの断面図である。
Embodiments of the present invention will be described below with reference to the drawings. 2A to 2C are sectional views of a semiconductor chip for explaining one embodiment of the present invention.

【0012】まず、半導体基板上の蓄積電極の形成方法
について述べる。図2(a)に示すように、Si基板1
上にSiO2膜2を形成した後、LPCVD法にて多結
晶Si層3をSiO2膜2上に形成し、続いてリンを熱
拡散して、多結晶Si層3のシート抵抗を600Ω/□
とする。その後、フォトレジスト層を形成した後、光リ
ソグラフィー技術によりパターニングしマスク4を形成
する。ドライエッチング装置は、13.56MHzの高
周波放電を利用したカソードカップル方式の平行平板型
バッチ式エッチャーを用いる。エッチングガスとしてH
Brガスを用い、マスフローコントローラーにより60
SCCM流し、圧力100mTorr,RFパワーは1
50Wの条件で、蓄積電極のエッチング形状が垂直にな
るようにエッチングする。エッチング終了後、さらに3
0%の追加エッチングを加えることによって、多結晶S
i層3のエッチング残しがないようにする。その後、マ
イクロ波励起型のアッシング装置により、CF4(2
%)+O2放電で20秒間,引続き、O2放電により90
秒間晒してレジストを剥離し、図2(b)に示すよう
に、異方性形状の蓄積電極5を多数形成する。
First, a method of forming a storage electrode on a semiconductor substrate will be described. As shown in FIG. 2A, the Si substrate 1
After forming the SiO 2 film 2 thereon, a polycrystalline Si layer 3 is formed on the SiO 2 film 2 by the LPCVD method, and then phosphorus is thermally diffused to reduce the sheet resistance of the polycrystalline Si layer 3 to 600Ω / □
And Then, after forming a photoresist layer, patterning is performed by a photolithography technique to form a mask 4. The dry etching apparatus uses a cathode-coupled parallel plate type batch-type etcher that uses 13.56 MHz high-frequency discharge. H as etching gas
60 with a mass flow controller using Br gas
SCCM flow, pressure 100mTorr, RF power is 1
Etching is performed under the condition of 50 W so that the etching shape of the storage electrode becomes vertical. 3 more after etching
By adding 0% additional etching, polycrystalline S
Make sure that there is no etching residue on the i layer 3. After that, a CF 4 (2
%) + O 2 discharge for 20 seconds, followed by O 2 discharge to 90
The resist is peeled off by exposing for 2 seconds, and a large number of anisotropic storage electrodes 5 are formed as shown in FIG.

【0013】次に、HBr+N2の混合ガスの流量比を
変え(N217%,50%,83%)、総流量が60s
ccmになるようにマスフローコントローラーで制御す
る。圧力,RFパワーは、共に上記条件と同一とする。
以上の条件でエッチングした結果を図3(a)〜(c)
に示す。N2添加量17%でシリコン表面に凹凸が発生
し始め、添加量50%においてシリコン表面は、直径2
00Å程度の半球状凹凸形状に加工される。
Next, the flow rate of the mixed gas of HBr + N 2 was changed (N 2 17%, 50%, 83%) and the total flow rate was 60 s.
It is controlled by a mass flow controller so that it becomes ccm. Both the pressure and the RF power are the same as the above conditions.
The results of etching under the above conditions are shown in FIGS.
Shown in. When the amount of N 2 added was 17%, irregularities began to appear on the silicon surface, and when the amount of added N was 50%, the silicon surface had
It is processed into a hemispherical irregular shape of about 00Å.

【0014】しかしながら、添加量83%では、エッチ
ングは進行せず、表面は平坦である。N2添加量が約3
0%以上から60%の範囲でシリコン表面は、半球状の
凹凸形状に加工される。この機構は、N2を添加して多
結晶Siをエッチングすると、プラズマ中でシリコン窒
化物が生成され、これが多結晶Si表面に堆積する。ま
たHBrは、シリコンをエッチングするため、堆積反応
とエッチング反応とが競合し、多結晶Siの表面を凹凸
形状に加工する。そこで、HBr(50%)+N2(5
0%)混合ガスで、蓄積電極5をエッチングすると、図
2(c)に示すように半球状の凹凸形状を有する蓄積電
極6が形成できる。
However, when the addition amount is 83%, etching does not proceed and the surface is flat. N 2 addition amount is about 3
In the range of 0% to 60%, the silicon surface is processed into a hemispherical uneven shape. According to this mechanism, when N 2 is added and polycrystalline Si is etched, silicon nitride is generated in plasma, and this is deposited on the surface of polycrystalline Si. Since HBr etches silicon, the deposition reaction and the etching reaction compete with each other to process the surface of polycrystalline Si into an uneven shape. Therefore, HBr (50%) + N 2 (5
When the storage electrode 5 is etched with (0%) mixed gas, a storage electrode 6 having a hemispherical uneven shape can be formed as shown in FIG.

【0015】本発明では、エッチングガスにHBr+N
2を用いたが、Siをエッチングするガスであれば、堆
積反応を引き起こすガスを添加することにより、多結晶
Siの表面を半球状の凹凸形状に加工することができ、
大きな蓄積容量をもつ半導体装置を製造することができ
る。また、実施例にはエッチング装置に13.56MH
zの高周波放電を利用したカソードカップル方式の平行
平板型バッチ式エッチャーを用いたが、同じ平行平板型
エッチング装置で枚葉式のものや、電子サイクロトロン
共鳴を利用したエッチング装置等にもこの形成方法を適
用できることはいうまでもない。
In the present invention, the etching gas is HBr + N.
2 was used, but if it is a gas that etches Si, by adding a gas that causes a deposition reaction, the surface of polycrystalline Si can be processed into a hemispherical uneven shape,
It is possible to manufacture a semiconductor device having a large storage capacity. In addition, in the embodiment, the etching device has 13.56 MH.
Although the cathode-coupled parallel plate type batch etcher utilizing the high frequency discharge of z was used, the same parallel plate type etching apparatus using a single-wafer type, the etching method using electron cyclotron resonance, etc. Needless to say, can be applied.

【0016】[0016]

【発明の効果】以上説明したように本発明によれば、L
PCVD法を用いることなく、ドライエッチングで多結
晶Si表面を半球状の凹凸形状に加工でき、蓄積電極を
極めて再現性良く形成することができる。従って大きな
蓄積容量を有する半導体装置が得られる。
As described above, according to the present invention, L
The polycrystalline Si surface can be processed into a hemispherical uneven shape by dry etching without using the PCVD method, and the storage electrode can be formed with extremely good reproducibility. Therefore, a semiconductor device having a large storage capacity can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】LPCVD法で表面に凹凸形状を有する多結晶
Siの形成温度と蓄積容量の関係を示す図である。
FIG. 1 is a diagram showing a relationship between a formation temperature of polycrystalline Si having an uneven surface on the surface by an LPCVD method and a storage capacitance.

【図2】本発明の一実施例を説明するための半導体チッ
プの断面図である。
FIG. 2 is a sectional view of a semiconductor chip for explaining one embodiment of the present invention.

【図3】HBrガスへのN2添加率とシリコン表面の凹
凸形状度合いを示す顕微鏡写真である。
FIG. 3 is a micrograph showing the N 2 addition rate to HBr gas and the degree of unevenness of the silicon surface.

【符号の説明】[Explanation of symbols]

1 Si基板 2 SiO2膜 3 多結晶Si層 4 マスク 5 蓄積電極 6 半球状の凹凸形状を有する蓄積電極1 Si substrate 2 SiO 2 film 3 polycrystalline Si layer 4 mask 5 storage electrode 6 storage electrode having a hemispherical uneven shape

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年7月19日[Submission date] July 19, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】図3[Name of item to be corrected] Figure 3

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図3】HBrガスへのN2添加率とシリコン表面の凹
凸形状度合いを示す結晶構造の顕微鏡写真である。
FIG. 3 is a micrograph of a crystal structure showing the N 2 addition rate to HBr gas and the degree of uneven shape of the silicon surface.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電極形成工程とエッチング加工工程とを
有する半導体装置の製造方法であって、 電極形成工程は、半導体基板上に異方性形状の蓄積電極
を形成するものであり、 エッチング加工工程は、上記蓄積電極表面を半球状の凹
凸形状にドライエッチング加工するものであることを特
徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device comprising an electrode forming step and an etching processing step, wherein the electrode forming step forms an anisotropic storage electrode on a semiconductor substrate. Is a method for manufacturing a semiconductor device, characterized in that the surface of the storage electrode is dry-etched into a hemispherical uneven shape.
JP4316610A 1992-10-30 1992-10-30 Manufacture of semiconductor device Pending JPH06151711A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4316610A JPH06151711A (en) 1992-10-30 1992-10-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4316610A JPH06151711A (en) 1992-10-30 1992-10-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06151711A true JPH06151711A (en) 1994-05-31

Family

ID=18078988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4316610A Pending JPH06151711A (en) 1992-10-30 1992-10-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06151711A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332130B1 (en) * 1995-12-12 2002-08-21 주식회사 하이닉스반도체 Method for forming storage electrode in semiconductor device
US6686234B1 (en) 1999-12-24 2004-02-03 Fujitsu Limited Semiconductor device and method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332130B1 (en) * 1995-12-12 2002-08-21 주식회사 하이닉스반도체 Method for forming storage electrode in semiconductor device
US6686234B1 (en) 1999-12-24 2004-02-03 Fujitsu Limited Semiconductor device and method for fabricating the same

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