JP3149478B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3149478B2 JP3149478B2 JP27952991A JP27952991A JP3149478B2 JP 3149478 B2 JP3149478 B2 JP 3149478B2 JP 27952991 A JP27952991 A JP 27952991A JP 27952991 A JP27952991 A JP 27952991A JP 3149478 B2 JP3149478 B2 JP 3149478B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- polysilicon film
- lower electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000000034 method Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 54
- 229920005591 polysilicon Polymers 0.000 claims description 54
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 150000008064 anhydrides Chemical class 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に容量部の下部電極の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a lower electrode of a capacitor.
【０００２】[0002]
【従来の技術】従来半導体装置における容量部の下部電
極の形成は、以下の様に行われていた。半導体基板上に
絶縁膜を介してポリシリコン膜を成長させた後、リン等
の不純物をポリシリコン膜中に導入する。次でフォトレ
ジスト膜を用いてこのポリシリコン膜のパターニングを
行い、下部電極を形成する。2. Description of the Related Art Conventionally, formation of a lower electrode of a capacitance section in a semiconductor device has been performed as follows. After growing a polysilicon film on a semiconductor substrate via an insulating film, an impurity such as phosphorus is introduced into the polysilicon film. Next, the polysilicon film is patterned using a photoresist film to form a lower electrode.
【０００３】しかしながら、６４ＭＤＲＡＭの様に、デ
バイスの微細化が進むと、ポリシリコンの凹凸を利用し
て下部電極の表面積を大きくする方法が、例えばＭ．サ
カオ（Ｓａｋａｏ）らにより、１９９０ インターナシ
ョナル エレクトロン デバイセス ミーティング テ
クニカル ダイジェスト（Ｉｎｔｅｒｎａｔｉｏｎａｌ
Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅｓ Ｍｅｅｔｉｎｇ
ＴＥＣＨＮＩＣＡＬＤＩＧＥＳＴ）６５５頁に報告さ
れている。However, as devices become finer, such as 64M DRAM, a method of increasing the surface area of the lower electrode by using the unevenness of polysilicon has been proposed by, for example, M.A. Sakao et al., 1990 International Electron Devices Meeting Technical Digest (International)
Electron Devices Meeting
TECHNICALIGEST) page 655.
【０００４】この方法は、まず図２（ａ）に示すよう
に、シリコン基板１上にＳｉＯ2 膜２を設け、開口部を
形成する。次で全面にポリシリコン膜１３を６００〜６
５０℃の成長温度で成長し、フォトレジスト膜を用い
て、下部電極の形にパターニングする。次に図２（ｂ）
に示すように、５３０〜５８０℃の成長温度で表面が凹
凸のポリシリコン膜１３Ａを成長させる。さらに図２
（ｃ）に示すように、このポリシリコン膜１３Ａをエッ
チバックしてポリシリコン膜１３，１３Ａからなる表面
積の大きな下部電極を形成する。In this method, first, as shown in FIG. 2A, an SiO 2 film 2 is provided on a silicon substrate 1 to form an opening. Next, a polysilicon film 13 is formed on the entire surface in the range of 600 to 6.
It is grown at a growth temperature of 50 ° C., and is patterned into a lower electrode using a photoresist film. Next, FIG.
As shown in FIG. 5, a polysilicon film 13A having an uneven surface is grown at a growth temperature of 530 to 580 ° C. Further FIG.
As shown in FIG. 3C, the polysilicon film 13A is etched back to form a lower electrode having a large surface area composed of the polysilicon films 13 and 13A.
【０００５】また、上記文献の６６３頁には、ピーレ
Ｃ ファゼン（Ｐｉｅｒｒｅ ＣＦａｚａｎ）等により
別の方法が報告されている。On page 663 of the above document,
Another method has been reported by Pierre CFazan et al.
【０００６】この方法は図３（ａ）に示すように、シリ
コン基板１上にＳｉＯ2 膜２を介してポリシリコン膜１
３を６００〜６５０℃の成長温度で成長、リン等の不純
物を導入後、フォトレジスト膜を用いて下部電極の形に
パターニングする。次に図３（ｂ）に示すように、酸化
性雰囲気中で熱処理を行う。この時ポリシリコン膜１３
の結晶粒界が特に酸化されるので、ポリシリコン膜１３
の表面の凹凸が大きくなる、次に図３（ｃ）に示すよう
に、ふっ酸を含む水溶液を用いて、ポリシリコン膜１３
上のＳｉＯ2 膜４Ａを除去し、表面積の大きな下部電極
を形成する。In this method, as shown in FIG. 3A, a polysilicon film 1 is formed on a silicon substrate 1 via an SiO 2 film 2.
3 is grown at a growth temperature of 600 to 650 ° C., and after introducing impurities such as phosphorus, it is patterned into the shape of a lower electrode using a photoresist film. Next, as shown in FIG. 3B, heat treatment is performed in an oxidizing atmosphere. At this time, the polysilicon film 13 is formed.
Is particularly oxidized, so that the polysilicon film 13
Then, as shown in FIG. 3C, the polysilicon film 13 is formed using an aqueous solution containing hydrofluoric acid.
The upper SiO 2 film 4A is removed, and a lower electrode having a large surface area is formed.
【０００７】これらの方法で形成された下部電極の表面
積は、通常の場合に比較して、約１．３〜２．５倍程度
大きくなっている。The surface area of the lower electrode formed by these methods is about 1.3 to 2.5 times as large as that of a normal case.
【０００８】[0008]
【発明が解決しようとする課題】上述した従来の下部電
極の製造方法のうち前者の方法では、ポリシリコンの異
常成長による結晶粒の大きさを利用し、また後者の方法
では、結晶粒界付近の酸化速度がポリシリコン膜表面の
それより大きいことを利用しているので、ポリシリコン
膜表面の凹凸の度合いには限界がある。このため、通常
の方法に比較して表面積の増加は約２．５倍程度にしか
ならず、さらなるデバイスの微細化には対応できにくい
という問題点がある。In the above-mentioned conventional method for manufacturing a lower electrode, the former method utilizes the size of crystal grains caused by abnormal growth of polysilicon, and the latter method uses the vicinity of a crystal grain boundary. Utilizing the fact that the oxidation rate is higher than that of the polysilicon film surface, there is a limit to the degree of unevenness of the polysilicon film surface. For this reason, there is a problem that the increase in the surface area is only about 2.5 times as compared with the ordinary method, and it is difficult to cope with further miniaturization of the device.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に絶縁膜を形成したのちパター
ニングし開口部を形成する工程と、この開口部を含む全
面に容量部の下部電極となる表面が凹凸状でかつ不純物
を含むポリシリコン層を形成したのちパターニングする
工程と、前記ポリシリコン層の表面を酸化したのちエッ
チバックしポリシリコン層の凸部を露出させる工程と、
前記ポリシリコンの凹部に残された酸化膜をマスクとし
前記露出したポリシリコン層の凸部をエッチングして溝
を形成する工程と、マスクとして用いた前記酸化膜を除
去したのち全面に容量絶縁膜と上部電極となるポリシリ
コン層を順次形成する工程とを含むものである。According to a method of manufacturing a semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate and then patterned to form an opening. A step of patterning after forming a polysilicon layer having an uneven surface and an impurity containing electrodes, and a step of exposing a surface of the polysilicon layer by oxidizing the surface of the polysilicon layer and then exposing the polysilicon layer,
Forming a groove by etching the exposed convex portion of the polysilicon layer using the oxide film remaining in the concave portion of the polysilicon as a mask, and removing the oxide film used as the mask and removing a capacitor insulating film over the entire surface. And a step of sequentially forming a polysilicon layer to be an upper electrode.
【００１０】[0010]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）〜（ｄ）は本発明の第１の実施例を説明
するための半導体チップの断面図であり、特にスタック
型容量部に適用した場合である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A to 1D are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, particularly when the present invention is applied to a stacked capacitor.
【００１１】まず、図１（ａ）のように、シリコン基板
１上にＳｉＯ2 膜２を形成したのち開口部を形成する。
次でリン等の不純物が導入されているポリシリコン膜３
を形成したのち下部電極の形にパターニングする。First, as shown in FIG. 1A, an SiO 2 film 2 is formed on a silicon substrate 1, and then an opening is formed.
Next, a polysilicon film 3 into which impurities such as phosphorus are introduced.
Is formed and then patterned into the shape of a lower electrode.
【００１２】次に図１（ｂ）に示すように、酸化性雰囲
気中でポリシリコン膜３を酸化して、厚さ３０〜１００
ｎｍのＳｉＯ2 膜４を形成する。この際、ポリシリコン
膜３の凹凸を形成する結晶粒界付近では酸化速度が大き
く、表面に比較して厚いＳｉＯ2 膜４が形成される。Next, as shown in FIG. 1B, the polysilicon film 3 is oxidized in an oxidizing atmosphere to a thickness of 30 to 100.
An SiO 2 film 4 of nm is formed. At this time, the oxidation rate is high in the vicinity of the crystal grain boundary forming the irregularities of the polysilicon film 3, and the SiO 2 film 4 thicker than the surface is formed.
【００１３】次に図１（ｃ）に示すように、ＣＦ4 , Ｃ
Ｈ3 等のガスを用いるドライエッチング法によりポリシ
リコン膜３上のＳｉＯ2 膜４をエッチングする。この
時、ポリシリコン膜３の表面が現われた段階でＳｉＯ2
膜４のエッチングを止め、ポリシリコン膜３の凹部のＳ
ｉＯ2 膜４を残す。次でこのポリシリコン膜３の凹部に
残されたＳｉＯ2 膜４をマスクにして、ＨＢｒ等のガス
を用いて、ポリシリコン膜３をドライエッチングで除去
し溝５を形成する。ただしポリシリコン膜３のエッチン
グ量としては、ＳｉＯ2 膜２が現われないままである。Next, as shown in FIG. 1C, CF 4 , C
The SiO 2 film 4 on the polysilicon film 3 is etched by a dry etching method using a gas such as H 3 . In this, it SiO 2 at the stage when the surface of the polysilicon film 3 appeared
The etching of the film 4 is stopped, and the S
The iO 2 film 4 is left. Next, using the SiO 2 film 4 left in the concave portion of the polysilicon film 3 as a mask, the polysilicon film 3 is removed by dry etching using a gas such as HBr to form a groove 5. However, as for the etching amount of the polysilicon film 3, the SiO 2 film 2 does not appear.
【００１４】次に図１（ｄ）に示すように、ふっ酸を含
む水溶液を用いてポリシリコン膜３上のマスクとして用
いたＳｉＯ2 膜４を除去する。Next, as shown in FIG. 1D, the SiO 2 film 4 used as a mask on the polysilicon film 3 is removed using an aqueous solution containing hydrofluoric acid.
【００１５】以下従来と同様に全面にＬＰ−ＣＶＤ法で
シリコン窒化膜を成長し、酸化性雰囲気中でその表面を
酸化して容量絶縁膜を形成する。さらにポリシリコン膜
を成長させ、リン等の不純物導入後、フォトレジスト膜
を用いパターニングして上部電極を形成し、スタック容
量部を完成させる。A silicon nitride film is grown on the entire surface by LP-CVD in the same manner as in the prior art, and its surface is oxidized in an oxidizing atmosphere to form a capacitive insulating film. Further, a polysilicon film is grown, and after introducing impurities such as phosphorus, patterning is performed using a photoresist film to form an upper electrode, thereby completing a stack capacitor portion.
【００１６】以上の様に、溝５を形成し下部電極となる
ポリシリコン膜３の表面の凹凸を大きくすることで、表
面積が大きくなるため、同じ換算膜厚の容量絶縁膜を用
いても従来のポリシリコン膜の凹凸表面を利用したスタ
ック容量部に比べ２〜３倍程度の容量値が得られる。つ
まり、デバイスが微細になり下部電極の占める平面スペ
ースが小さくなっても、本発明を用いると、十分な容量
値を持つ容量部が形成できる。As described above, the surface area is increased by forming the grooves 5 and increasing the unevenness of the surface of the polysilicon film 3 serving as the lower electrode. About 2 to 3 times the capacitance value of the stack capacitance portion using the uneven surface of the polysilicon film. That is, even if the device becomes finer and the plane space occupied by the lower electrode is reduced, a capacitor portion having a sufficient capacitance value can be formed by using the present invention.
【００１７】次に、本発明の第２の実施例を説明する。
第１の実施例では、図１（ｃ）で説明したように、ポリ
シリコン膜３のエッチングを行った後、ポリシリコン膜
３の凹部、すなわち結晶粒界付近に残っているＳｉＯ2
膜４を除去するためにふっ酸水溶液を用いたが、第２の
実施例では、無水ふっ酸（ＨＦ）ガスを用いるドライエ
ッチングを行い、ＳｉＯ2 膜４を除去する。その他の製
造方法は、第１の実施例と同じである。Next, a second embodiment of the present invention will be described.
In the first embodiment, as described with reference to FIG. 1C, after the polysilicon film 3 is etched, the SiO 2 remaining in the recesses of the polysilicon film 3, that is, in the vicinity of the crystal grain boundaries.
Although the hydrofluoric acid aqueous solution is used to remove the film 4, in the second embodiment, dry etching using hydrofluoric anhydride (HF) gas is performed to remove the SiO 2 film 4. Other manufacturing methods are the same as in the first embodiment.
【００１８】この第２の実施例で、無水ふっ酸ガスを用
いる理由は以下の通りである。第１の実施例の様に、ふ
っ酸を含む水溶液を用いると、ＳｉＯ2 膜をエッチング
した後の水洗を行う際に、ポリシリコン膜３の表面に自
然酸化膜が成長する。そのため容量絶縁膜用のシリコン
窒化膜を成長した場合、下部電極としてのポリシリコン
膜とシリコン窒化膜の間に自然酸化膜が存在することと
なり、高い容量値が得られなくなる。そのため、第２の
実施例の様に、無水ふっ酸（ＨＦ）ガスを用いること、
下部電極用のポリシリコン膜表面の自然酸化膜の成長が
抑えられるので、高い容量値をもつ容量絶縁膜が形成で
きる。The reason for using hydrofluoric anhydride gas in the second embodiment is as follows. When an aqueous solution containing hydrofluoric acid is used as in the first embodiment, a natural oxide film grows on the surface of the polysilicon film 3 when washing with water after etching the SiO 2 film. Therefore, when a silicon nitride film for a capacitor insulating film is grown, a natural oxide film exists between the polysilicon film as the lower electrode and the silicon nitride film, and a high capacitance value cannot be obtained. Therefore, using hydrofluoric anhydride (HF) gas as in the second embodiment,
Since the growth of the natural oxide film on the surface of the polysilicon film for the lower electrode is suppressed, a capacitive insulating film having a high capacitance value can be formed.
【００１９】以上、第１及び第２の実施例では容量絶縁
膜としてシリコン窒化膜を用いて説明したが、Ｔａ2 Ｏ
5 ，ＨｆＯ2 等の高誘電率の金属酸化膜を用いても、本
発明の効果は変わらない。[0019] As described above, in the first and second embodiments have been described with reference to a silicon nitride film as a capacitor insulating film, Ta 2 O
5. Even if a metal oxide film having a high dielectric constant such as HfO 2 is used, the effect of the present invention is not changed.
【００２０】また、上記実施例では下部電極用ポリシリ
コン膜に通常の方法で成長したポリシリコン膜を用いた
が、従来技術で説明した５３０〜５８０℃で形成する表
面凹凸の大きなポリシリコン膜を用いたり、リンドープ
ポリシリコン膜やリンドープアモルファスシリコン膜等
を用いても本発明の効果は変わらない。なお、上部電極
にポリシリコン膜以外の電極材，例えばシリサイドある
いはタングステン等の高融点金属を用いるのも自由であ
る。In the above embodiment, the polysilicon film for the lower electrode is a polysilicon film grown by an ordinary method. However, the polysilicon film having a large surface irregularity formed at 530 to 580 ° C. described in the prior art is used. The effect of the present invention does not change even if it is used, or if a phosphorus-doped polysilicon film or a phosphorus-doped amorphous silicon film is used. In addition, an electrode material other than the polysilicon film, for example, a refractory metal such as silicide or tungsten may be freely used for the upper electrode.
【００２１】[0021]
【発明の効果】以上説明したように本発明によれば、従
来に比較して下部電極用のポリシリコン膜の表面形状
を、微細で凹凸の度合いを大きくできるため、従来の製
造方法に比べ２〜３倍程度の表面積をもつ下部電極が形
成できるという効果がある。それによって、容量絶縁膜
の薄膜化をあまり行わなくても、高容量値が確保できる
ので、スタック容量部の微細デバイスへの応用が容易に
なるという効果がある。As described above, according to the present invention, since the surface shape of the polysilicon film for the lower electrode can be made finer and the degree of unevenness can be increased as compared with the conventional method, it is possible to reduce the surface roughness of the polysilicon film. There is an effect that a lower electrode having a surface area of about 3 times can be formed. Accordingly, a high capacitance value can be secured without reducing the thickness of the capacitance insulating film, so that the effect of facilitating the application of the stack capacitance portion to a fine device is facilitated.
【図１】本発明の第１の実施例を説明するための半導体
チップの断面図。FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図２】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。FIG. 2 is a cross-sectional view of a semiconductor chip for describing a conventional method of manufacturing a semiconductor device.
【図３】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。FIG. 3 is a cross-sectional view of a semiconductor chip for describing a conventional method for manufacturing a semiconductor device.
１ シリコン基板 ２ ＳｉＯ2 膜 ３，１３，１３Ａ ポリシリコン膜 ４，４Ａ ＳｉＯ2 膜 ５ 溝1 silicon substrate 2 SiO 2 film 3,13,13A polysilicon film 4, 4A SiO 2 film 5 grooves
Claims (2)
ターニングし開口部を形成する工程と、この開口部を含
む全面に容量部の下部電極となる表面が凹凸状でかつ不
純物を含むポリシリコン層を形成したのちパターニング
する工程と、前記ポリシリコン層の表面を酸化したのち
エッチバックしポリシリコン層の凸部を露出させる工程
と、前記ポリシリコンの凹部に残された酸化膜をマスク
とし前記露出したポリシリコン層の凸部をエッチングし
て溝を形成する工程と、マスクとして用いた前記酸化膜
を除去したのち全面に容量絶縁膜と上部電極となるポリ
シリコン層を順次形成する工程とを含むことを特徴とす
る半導体装置の製造方法。An insulating film is formed on a semiconductor substrate and then patterned to form an opening, and the entire surface including the opening is made of polysilicon having an uneven surface and an impurity. Patterning after forming a layer, oxidizing the surface of the polysilicon layer and then etching back to expose the convex portion of the polysilicon layer, and using the oxide film remaining in the concave portion of the polysilicon as a mask, A step of forming a groove by etching the convex portion of the exposed polysilicon layer, and a step of sequentially forming a capacitor insulating film and a polysilicon layer to be an upper electrode on the entire surface after removing the oxide film used as a mask. A method for manufacturing a semiconductor device, comprising:
水ふっ酸ガスを用いる請求項１記載の半導体装置の製造
方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein hydrofluoric acid gas is used for etching the convex portion of the polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27952991A JP3149478B2 (en) | 1991-10-25 | 1991-10-25 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27952991A JP3149478B2 (en) | 1991-10-25 | 1991-10-25 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05121656A JPH05121656A (en) | 1993-05-18 |
| JP3149478B2 true JP3149478B2 (en) | 2001-03-26 |
Family
ID=17612283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27952991A Expired - Fee Related JP3149478B2 (en) | 1991-10-25 | 1991-10-25 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3149478B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960002097B1 (en) * | 1992-02-28 | 1996-02-10 | 삼성전자주식회사 | Method of making a capacitor for a semiconductor device |
| US5254503A (en) * | 1992-06-02 | 1993-10-19 | International Business Machines Corporation | Process of making and using micro mask |
| JP2697645B2 (en) * | 1994-10-31 | 1998-01-14 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| CN110391317B (en) * | 2019-07-29 | 2021-03-09 | 通威太阳能（成都）有限公司 | Textured surface preparation method of monocrystalline silicon wafer |
-
1991
- 1991-10-25 JP JP27952991A patent/JP3149478B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05121656A (en) | 1993-05-18 |
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