JPH06151633A - Semiconductor package - Google Patents

Abstract

PURPOSE:To easily suppress the crosstalk between signal lines by without lowering the wiring pattern density within a semiconductor package which enables high-density wiring. CONSTITUTION:The wiring patterns to the same signal lines are divided each into plural, and the divided wiring patterns 41 and 42 are stacked to lie one upon another in thickness direction through a dielectric 31, which constitutes one part of the structure, and also the plural divided wiring patterns 41 and 42 and a ground 2 are connected by printed resistor patterns 81 and 82, thus the potential of the plural divided wiring patterns 41 and 42 are divided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mounts a semiconductor element in a cavity provided in the center of a structure made of a dielectric material, and connects the semiconductor element and an external connection terminal arranged on the outer edge side of the structure to the structure. The present invention relates to a semiconductor package in which a large number of wiring patterns to be connected are formed, and particularly to a semiconductor package that enables a high wiring density.

[0002]

2. Description of the Related Art In recent years, the development of semiconductor technology has been remarkable, and IC chips and L
A semiconductor element called an SI chip is used. Since it is necessary to protect the semiconductor element from the environment and it is troublesome to handle, the semiconductor element may be first mounted in a package formed of a structure such as ceramic or synthetic resin, and then mounted on an electric circuit board. Many.

5A and 5B are schematic views of a conventional multi-pin IC package, in which an outer shape is formed on a square metal plate 2 in the same shape as the metal plate 2, and a square space (cavity) is formed in the center. A rectangular substrate 3 made of a ceramic or synthetic resin insulator (dielectric) material having C) is bonded by brazing or the like, and copper or the like is radially formed on the substrate 3 from the cavity C toward the outer peripheral side. The conductive wiring pattern 4 is printed. Then, the rectangular IC chip 1 is mounted in the cavity C, and the IC chip 1 and the wiring pattern 4 are electrically connected by a bonding wire 6 or the like. A lead pin 7 (external connection terminal) is electrically and mechanically connected to the outer peripheral portion of the substrate 3 on the wiring pattern 4 by means such as brazing. When the package P is mounted on the external electronic circuit board, the lead pins 7 are fixed on the wiring pattern of the circuit board by soldering or the like. Since the metal plate 2 is adhered to the back surface of the package P as described above, the plate 2 functions as a ground by the mounting. On the other hand, on the upper surface side of the rectangular substrate 3, a second rectangular substrate 5 made of an insulating (dielectric) material of ceramic or synthetic resin for concealing the wiring pattern 4 is bonded, and further the substrate 5 A cap 9 is adhered to the upper surface side of the above, and the cavity C space is sealed together with the IC chip 1.

According to such a conventional technique, a large number of lead pins 7 are required in proportion to the improvement in the degree of integration of the IC chip 1, and the more the package P is miniaturized,
The wiring density of the wiring pattern 4 becomes high, the distance between the wiring patterns 4 approaches to 1 mm or less, and electrical interference occurs. In particular, although an electric signal on a certain wiring pattern is not directly connected, a so-called crosstalk phenomenon occurs, which is magnetically coupled to an adjacent wiring pattern and leaks, and the frequency of the electric signal is high. As the connection becomes stronger, the black stroke also becomes larger, which causes a serious problem such as deterioration of the frequency characteristic of the semiconductor package.

In order to solve such a drawback, Japanese Patent Laid-Open No. 61-61
No. 182247, there is proposed a package in which a through hole for filling a conductor is provided in the IC chip mounting portion and a grounding wire is inserted between the signal lines to seal the wirings. (First conventional technology)

There is also a proposal for a high-frequency circuit package for the purpose of improving reliability by mounting a large number of high-frequency circuits in one package at high density and reducing the number of wiring connections (JP-A-3-212006). . This high-frequency circuit package uses a plurality of shield chambers, which are covered with shield cases, on both sides of a conductive substrate, and stores a high-frequency circuit having a different function in each shield chamber. It is designed so that the influence on other circuits and the influence from other circuits are not mutually affected.
(Second prior art)

[0007]

However, the above-mentioned first problem
In the related art, since the wiring pattern 4 laid on the insulating substrate forming the package is used alternately for the ground pattern and the signal line, the actual number of signal lines is halved, resulting in high-density wiring. Will not be satisfied.
The second prior art is a shield package that shields electromagnetic waves radiated from a high frequency circuit and cannot be a solution to crosstalk between wirings in which high frequency signals are highly mounted.

In view of the drawbacks of the prior art, the present invention has
Without reducing the wiring pattern density in the package,
An object of the present invention is to provide a semiconductor package capable of easily suppressing crosstalk between signal lines.

[0009]

In order to solve the problems of the present invention, a semiconductor element is mounted in a cavity C provided in the center of a structure made of a dielectric material, and the semiconductor is attached to the structure. In a semiconductor package in which a large number of wiring patterns for connecting elements and external connection terminals arranged on the outer peripheral side of the structure are formed, each of the wiring patterns 4 for the same signal line is divided into a plurality of wiring patterns 41,
42 are stacked and arranged so as to overlap each other in the thickness direction via the dielectric 31 forming a part of the structure, and the plurality of divided wiring patterns 41, 42 and the ground 2 are connected by the print resistance patterns 81, 82. The present invention proposes a semiconductor package characterized in that the plurality of divided wiring patterns 41, 42 are potential-divided.

In this case, as a specific configuration, the ground 2 is the conductive plate 2 disposed on the bottom side of the structure and the semiconductor element 1, and the printed resistance patterns 81 and 82 are the divided wiring patterns 41, Although it is configured to be connected to the conductive plate 2 at the start end side and the end side of 42, the present invention is not limited to this. The divided wiring patterns 41 and 42 do not necessarily have to have the same pattern width and the same shape, and may be changed. Also the potential division is naturally 1:
It does not have to be 1, and the number of divisions is not limited to two and may be three or four.

[0011]

According to such a technical means, since the wiring patterns 4 for the same signal line are respectively divided into a plurality of pieces, the divided wiring patterns 41, 42 have the same pattern width as the conventional wiring pattern width. Since it can be maintained, potential division is performed without increasing the characteristic impedance, and as a result, the current value for each wiring pattern 41, 42 can be reduced, and thus the cross stroke can be reduced. Further, since the wiring patterns 41 and 42 are divided and arranged so as to overlap each other in the thickness direction via the dielectric 31 which is a part of the structure, the divided wiring patterns 41 and 42 have the same pattern width as the conventional wiring. Even when the width of the pattern 4 is set to be the same, the occupied area per signal line does not increase, and high-density wiring can be realized.

Further, in the signal division into the wiring patterns 41 and 42, the plurality of divided wiring patterns 41 and 42 and the ground 2 are connected by the printed resistance patterns 81 and 82, and the plurality of divided wiring patterns 41 and 42 are connected. In the present invention, the printed resistance patterns 81 and 82 function as the ground 2 on the starting end side and the terminating side of the divided wiring patterns 41 and 42 in order to divide the potentials at an appropriate ratio. When viewed from the outside of the package, the divided wiring patterns 41 and 42 are configured to be terminated by the printed resistance patterns 81 and 82. By matching the resistance value to the characteristic impedance of the signal line, electrical matching can be maintained and reflection loss can be prevented. Further, the wiring patterns 41 and 42 divided inside the package are combined into one signal line (bonding) on the semiconductor element 1 side in the center of the package by the printed resistor patterns 81 and 82, and therefore, the same electrical principle is applied as described above. Consistency can be easily achieved.

Next, the operation of the present invention will be described in detail. The main cause of black stroke is magnetic coupling between wirings. For example, when an AC current I ₀ flows through a wiring, an AC magnetic field H is generated around the wiring. At this time, if adjacent wirings are close to each other, the wirings block the AC magnetic field H. At this time, an induced current I _e flows through the adjacent wiring. At this time, it is known that a proportional relationship such as I ₀ ∝ H ∝ I _e occurs between the alternating current I ₀ , the alternating magnetic field H, and the induced current I _e . Therefore, in order to reduce the induced current I _e , the current I ₀ flowing through the first wiring may be lowered. However, if the current value is attempted to be lowered carelessly by increasing the characteristic impedance of the signal line or the like, reflection loss occurs due to electrical mismatching, and the amount of signal transmission decreases. Therefore, the first feature of the present invention is to divide the wiring patterns 41 and 42 for the same signal line into a plurality of parts. Therefore, the current I ₀ flowing around each of the wiring patterns 41 and 42 is reduced, and thereby the cross stroke can be reduced.

Further, since the wiring patterns 41 and 42 are arranged on different layers so as to overlap each other in the thickness direction with the dielectric 31 interposed therebetween, even if the area of the current path is increased, one signal line is provided. High density wiring can be realized without increasing the occupied area. In particular, at a high frequency, when the wiring is divided, unless carefully designed, the electrical compatibility is lost and the reflection loss of the electric signal occurs. Therefore, in the present invention, in the signal division into each wiring, the printed resistance pattern 81 is provided between the plurality of divided wiring patterns 41 and 42 and the ground 2.
It is connected by 82 and the potential is divided at an appropriate ratio. Moreover, in the present invention, the printed resistor pattern 8 is used.
Since the wiring patterns 1 and 82 are connected to the conductive plate 2 that functions as the ground 2 on the start side and the termination side of the divided wiring patterns 41 and 42, the divided wiring patterns 41 and 42 are printed resistors when viewed from the outside of the package. Since the structure ends with the patterns 81 and 82, if the resistance value of the printed resistance patterns 81 and 82 is matched with the characteristic impedance of the signal line (for example, 50 Ω · cm) at this time, electrical matching is maintained. It is known that no spill signal reflection occurs.
Therefore, it is easy to suppress the reflection loss in the divided portions of the wiring patterns 41 and 42 by the above method. Further, the wirings divided inside the package are combined into one signal line (bonding) on the side of the semiconductor element 1 in the center of the package by the printed resistor patterns 81 and 82, so that the electrical matching is easy by the same principle as described above. Can be realized.

Next, the present invention and the prior art will be described with reference to an equivalent circuit. FIG. 6 shows the equivalent circuit according to the prior art shown in FIG. 5, in which a signal line (wiring pattern 4) and a ground potential line in a package. The (metal plate 2) is the semiconductor element 1 and the external circuit 10.
And are connected. In such an equivalent circuit, if the characteristic impedance Z1 of the signal line is increased, the current value will decrease, but the amount of signal transmission will decrease as described above. On the other hand, as shown in FIG. 4, the signal line is divided into two, and the plurality of divided signal lines 41 and 42 and the ground potential line 2 are connected to the resistance lines 81 and 82 at the start end side and the end side. Therefore, it can be understood that the potential is divided and the current value decreases without increasing the characteristic impedance Z2 of the signal line.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below as an example with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention thereto, unless otherwise specified, and are simply It is only an example of explanation. 1 is a semiconductor package according to an embodiment of the present invention, FIG. 2 is a central sectional view of FIG. 1, and FIG. 3 is an enlarged perspective view of a main part of FIG. As in the prior art, a rectangular substrate 3 made of a dielectric material having a rectangular space (cavity C) in the center is adhered on the metal plate 2, and the substrate 3 is divided into upper and lower two-layer substrates 31 and 32. The conductive wiring patterns 41 and 42 having the same shape and the same layout are radially printed from the cavity C toward the outer peripheral side on the divided upper layer substrate 31 and lower layer substrate 32, respectively. The two divided wiring patterns 41 and 42 are provided on the outer peripheral portion and the inner peripheral side (cavity C) of the package, which correspond to the starting end side and the terminating end side of the divided wiring patterns 41 and 42 respectively arranged above and below.
Printed resistance patterns 81 and 82 for electrically connecting the wiring and the ground (metal plate) 2 are printed. The resistance values of the printed resistance patterns 81 and 82 are divided at an appropriate ratio by the characteristic impedance of the wiring patterns 41 and 42.

According to this embodiment, when the semiconductor package P is mounted on an external circuit, the signal current input into the package P via the lead pins 7 is divided into the divided wiring patterns via the printed resistance patterns 81 and 82. 41, 4
2 and the potential is divided and transmitted, and the divided wiring pattern 4 is transmitted.
The current values of 1 and 42 are reduced. Therefore, the magnetic field coupling between the adjacent wiring patterns 41 and 42 in the package is weakened, and the occurrence of crosstalk is suppressed. The current division ratio is determined by the division ratio of the printed resistance patterns 81 and 82 by the divided wiring patterns 41 and 42, and is always 1 :.
It does not have to be 1. Further, since the divided wiring patterns 41 and 42 are laminated and arranged so as to overlap with each other with the upper substrate 31 interposed therebetween, the area occupied by the divided wiring patterns 41 and 42 is not increased, and therefore high density wiring is possible. on the other hand,
When viewed from outside the package, the divided wiring pattern 4
Since 1 and 42 are configured to be terminated by the printed resistance patterns 81 and 82, if the resistance value of the printed resistance patterns 81 and 82 is matched with the characteristic impedance of the signal line (for example, 50 Ω · cm) at this time, Electrical matching is maintained and signal reflection does not occur.

[0018]

As described above, according to the present invention,
Even in a semiconductor package having a large number of pins and a large number of wiring patterns, a package with a small cross stroke can be realized without reducing the wiring density. At that time, the electrical matching is kept good and the reflection loss does not increase. And so on.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a semiconductor package according to an embodiment of the present invention.

FIG. 2 is a central sectional view of FIG.

FIG. 3 is an enlarged perspective view of a main part showing a divided wiring pattern and a printed resistance pattern.

FIG. 4 shows an equivalent circuit of FIG.

FIG. 5 shows a conventional multi-pin semiconductor package, (A).
Is a schematic plan view, and (B) is a central sectional view.

FIG. 6 is an equivalent circuit diagram of FIG.

[Explanation of symbols]

 1 Semiconductor Element 2 Metal Plate (Conductive Plate, Ground) 3, 31, 32 Substrate (Dielectric) 4, 41, 42 Wiring Pattern 6 Bonding Line 7 Lead Pin 81, 82 Printing Resistance Pattern C Cavity P Package

Claims (2)

[Claims] 1. A semiconductor element is mounted in a cavity provided at the center of a structure made of a dielectric material, and the structure is provided with:
In a semiconductor package in which a plurality of wiring patterns for connecting between the semiconductor element and external connection terminals arranged on the outer edge side of the structure are formed, each of the wiring patterns for the same signal line is divided into a plurality of wiring patterns, Along with a part of the dielectric, they are stacked so that they overlap in the thickness direction,
A semiconductor package characterized in that the plurality of divided wiring patterns and the ground are connected by a printed resistance pattern, and the plurality of divided wiring patterns are potential-divided. 2. A semiconductor in which the ground is a conductive plate disposed on a bottom surface side of a structure and a semiconductor element, and the printed resistance pattern is connected to the conductive plate on a start end side and a terminal end side of a divided wiring pattern. package