JPH06151631A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06151631A JPH06151631A JP4292821A JP29282192A JPH06151631A JP H06151631 A JPH06151631 A JP H06151631A JP 4292821 A JP4292821 A JP 4292821A JP 29282192 A JP29282192 A JP 29282192A JP H06151631 A JPH06151631 A JP H06151631A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- holding plate
- lead
- inductance
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に高周波高出力用半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device for high frequency and high output.
【０００２】[0002]
【従来の技術】従来の半導体装置は、図３（ａ），
（ｂ），（ｃ）に示すように、銅よりなる金属放熱板１
の上に、絶縁性がありかつ熱伝導度の高い材質（例えば
ベリリアセラミック）から成る半導体保持板７が接合さ
れ、この半導体保持板７上にメタライズ層４が施され、
このメタライズ層４上に半導体素子８が搭載されてい
る。2. Description of the Related Art A conventional semiconductor device is shown in FIG.
As shown in (b) and (c), a metal radiator plate 1 made of copper is used.
A semiconductor holding plate 7 made of a material having an insulating property and a high thermal conductivity (for example, beryllia ceramic) is bonded onto the above, and a metallization layer 4 is provided on the semiconductor holding plate 7.
A semiconductor element 8 is mounted on the metallized layer 4.
【０００３】半導体素子８がバイポーラトランジスタの
場合、この半導体素子８の裏面は一般にコレクタになっ
ており、メタライズ層４はコレクタと接続され、更にこ
のメタライズ層４はボンディングワイヤ１０によりコレ
クタリード６と電気的に接続されている。一方エミッタ
側は、半導体素子８の表面上の入力電極とエミッタ接地
電極３，５へボンディングワイヤ１０により電気的に接
続されて半導体保持板７へ接地されている。また半導体
素子８もボンディングワイヤ１０によりベースリード２
と電気的に接続されている。When the semiconductor element 8 is a bipolar transistor, the back surface of the semiconductor element 8 is generally a collector, the metallization layer 4 is connected to the collector, and the metallization layer 4 is electrically connected to the collector lead 6 by a bonding wire 10. Connected to each other. On the other hand, the emitter side is electrically connected to the input electrode on the surface of the semiconductor element 8 and the grounded emitter electrodes 3, 5 by the bonding wire 10 and grounded to the semiconductor holding plate 7. The semiconductor element 8 is also connected to the base lead 2 by the bonding wire 10.
Is electrically connected to.
【０００４】[0004]
【発明が解決しようとする課題】上述した半導体装置で
は、図３に示されるように、エミッタ接地電極３，また
は５が経路Ａ→Ｂ→Ｃを通り金属放熱板１へ接地される
ために、エミッタ接地電極３，５の経路Ａ→Ｂ間の距離
が長くなる。そのため図３（ｄ）に示すように、ベー
ス，コレクタおよびエミッタのボンディングワイヤイン
ダクタンスＬ１，Ｌ２，Ｌ３およびエミッタ電極インダ
クタンスＬ４があるが、エミッタ電極インダクタンスＬ
４が大きくなり、ＲＦ特性が低下するという問題点があ
った。In the above-described semiconductor device, as shown in FIG. 3, since the grounded emitter electrode 3 or 5 is grounded to the metal heat sink 1 through the route A → B → C, The distance between the routes A → B of the grounded-emitter electrodes 3, 5 becomes longer. Therefore, as shown in FIG. 3D, although there are bonding wire inductances L1, L2, L3 and an emitter electrode inductance L4 for the base, the collector and the emitter, the emitter electrode inductance L
4 becomes large and the RF characteristics deteriorate.
【０００５】本発明の目的は、このような問題を解決
し、エミッタ電極のインダクタンスを小さくし、高周波
特性を改善した半導体装置を提供することにある。An object of the present invention is to solve the above problems, to provide a semiconductor device in which the inductance of the emitter electrode is reduced and the high frequency characteristics are improved.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置の構
成は、金属放熱板上に絶縁半導体保持板が接合され、こ
の半導体保持板上に島状に形成された複数のメタライズ
層を設け、これらメタライズ層の１つに半導体素子が搭
載され、前記メタライズ層のうち接地電極となるメタラ
イズ層が入力部、出力部または両方のリード中央部に開
孔部を有し、前記半導体保持板の端面を経由して前記金
属放熱板へ接地されていることを特徴とする。A semiconductor device according to the present invention has a structure in which an insulating semiconductor holding plate is joined to a metal heat dissipation plate, and a plurality of island-shaped metallized layers are provided on the semiconductor holding plate. A semiconductor element is mounted on one of the metallized layers, and the metallized layer serving as a ground electrode of the metallized layer has an opening portion in the lead central portion of the input portion, the output portion or both, and the end face of the semiconductor holding plate. It is characterized in that it is grounded to the metal heat dissipation plate via.
【０００７】[0007]
【実施例】図１（ａ），（ｂ），（ｃ）は、本発明の第
１の実施例の平面図および側面図を示している。図に示
す様に、本実施例も、銅よりなる金属放熱板１の上に、
絶縁性がありかつ熱伝導度の高い材質（例えばベリリア
セラミック）から成る半導体保持板７が接合され、この
半導体保持板７上にメタライズ層４が施され、このメタ
ライズ層４上に半導体素子８が搭載され、エミッタ接地
電極３，５へボンディングワイヤ１０で電気的に接続さ
れている。1 (a), 1 (b) and 1 (c) show a plan view and a side view of a first embodiment of the present invention. As shown in the figure, in the present embodiment as well, on the metal heat dissipation plate 1 made of copper,
A semiconductor holding plate 7 made of a material having an insulating property and a high thermal conductivity (for example, beryllia ceramic) is bonded, a metallization layer 4 is formed on the semiconductor holding plate 7, and a semiconductor element 8 is formed on the metallization layer 4. Is mounted and electrically connected to the grounded emitter electrodes 3 and 5 by a bonding wire 10.
【０００８】この場合、図１（ｂ）に示すように、エミ
ッタ接地電極３（入力側）を一部ベースリード側へ伸ば
し、ベースリード中央部に開孔部（３×２ｍｍ）を設
け、この開孔部を介し半導体保持板７の端面を経由して
金属放熱板１へ接地される。この方法を行う事で、半導
体素子８と金属放熱板１間の距離が短くなる。In this case, as shown in FIG. 1B, the grounded emitter electrode 3 (input side) is partially extended to the base lead side, and an opening (3 × 2 mm) is provided at the center of the base lead. It is grounded to the metal heat dissipation plate 1 via the end face of the semiconductor holding plate 7 through the opening. By performing this method, the distance between the semiconductor element 8 and the metal heat sink 1 is shortened.
【０００９】そこで具体例について説明する。従来例と
して、エミッタ接地電極３の幅Ｗ＝１．５ｍｍ，厚さｄ
＝０．１ｍｍとし、図中の最長経路Ａ→Ｂ→Ｃをｌ＝１
０ｍｍとする。この時のエミッタ電極のインダクタンス
Ｌ４は６．１２〔ｎＨ〕となる。次に、本実施例として
幅Ｗ＝１．５ｍｍ，厚さｄ＝０．１ｍｍとし、図中の最
長経路Ｆ→Ａ→Ｄ→Ｅをｌ＝９ｍｍとする。この時のエ
ミッタ電極インダクタンスＬ４は５．３３〔ｎＨ〕とな
る。この結果、従来エミッタ電極インダクタンスＬ４が
６．１２〔ｎＨ〕だったものが、本実施例では５．３３
〔ｎＨ〕（約８７％）まで低下することがわかる。A specific example will be described. As a conventional example, the width W of the grounded-emitter electrode 3 is 1.5 mm and the thickness d is
= 0.1 mm, and the longest route A → B → C in the figure is 1 = 1
0 mm. The inductance L4 of the emitter electrode at this time is 6.12 [nH]. Next, in this embodiment, the width W is 1.5 mm, the thickness d is 0.1 mm, and the longest route F → A → D → E in the figure is 1 = 9 mm. At this time, the emitter electrode inductance L4 is 5.33 [nH]. As a result, the conventional emitter electrode inductance L4 of 6.12 [nH] is 5.33 in the present embodiment.
It can be seen that the value decreases to [nH] (about 87%).
【００１０】図２は本発明の第２の実施例の平面図であ
る。図に示すように、エミッタ電極３（入力側）と５
（出力側）をそれぞれベースリード側，コレクタリード
側へ一部伸ばし、リード中央部に開孔部（３×２ｍｍ）
を設け、この開孔部を介して半導体保持板７の端面を経
由して金属放熱板１へ接地する。この方法でさらに、エ
ミッタ接地電極インダクタンスＬ４を小さくできる。FIG. 2 is a plan view of the second embodiment of the present invention. As shown in the figure, the emitter electrodes 3 (input side) and 5
Partly extend the (output side) to the base lead side and collector lead side respectively, and make an opening (3 x 2 mm) in the center of the lead.
Is provided, and is grounded to the metal radiator plate 1 via the end face of the semiconductor holding plate 7 through this opening. This method can further reduce the grounded-emitter electrode inductance L4.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、エミッタ
接地電極を一部ベースリード側へ伸ばし、ベースリード
中央部へ開孔部を設け、この開孔を介し、半導体保持板
の端面を経由し、金属放熱板へ接地しているので、エミ
ッタ接地電極インダクタンスが小さくなり、ＲＦ特性が
改善されるという効果を有する。As described above, according to the present invention, the grounded-emitter electrode is partially extended to the side of the base lead, an opening is provided in the center of the base lead, and the end face of the semiconductor holding plate is passed through this opening. However, since it is grounded to the metal heat sink, the grounded emitter electrode inductance is reduced and the RF characteristics are improved.
【図１】本発明の第１の実施例の平面図および側面図。FIG. 1 is a plan view and a side view of a first embodiment of the present invention.
【図２】本発明の第２の実施例の平面図。FIG. 2 is a plan view of the second embodiment of the present invention.
【図３】従来例の半導体装置の平面図、側面図およびそ
の等価回路図。FIG. 3 is a plan view, a side view, and an equivalent circuit diagram of a conventional semiconductor device.
１ 金属放熱板 ２ エミッタリード（入力側） ３ エミッタ電極 ４ メタライズ層 ５ エミッタ電極 ６ コレクタリード（出力側） ７ 半導体保持板 ８ 半導体素子 １０ ボンディングワイヤ Ｌ１ ベースボンディングワイヤインダクタンス Ｌ２ コレクタボンディングワイヤインダクタンス Ｌ３ エミッタボンディングワイヤインダクタンス Ｌ４ エミッタ電極インダクタンス 1 Metal Heat Dissipator 2 Emitter Lead (Input Side) 3 Emitter Electrode 4 Metallization Layer 5 Emitter Electrode 6 Collector Lead (Output Side) 7 Semiconductor Holding Plate 8 Semiconductor Element 10 Bonding Wire L1 Base Bonding Wire Inductance L2 Collector Bonding Wire Inductance L3 Emitter Bonding Wire inductance L4 Emitter electrode inductance
Claims (1)
され、この半導体保持板上に島状に形成された複数のメ
タライズ層を設け、これらメタライズ層の１つに半導体
素子が搭載され、前記メタライズ層のうち接地電極とな
るメタライズ層が入力部、出力部または両方のリード中
央部に開孔部を有し、前記半導体保持板の端面を経由し
て前記金属放熱板へ接地されていることを特徴とする半
導体装置。1. An insulating semiconductor holding plate is bonded onto a metal heat dissipation plate, a plurality of island-shaped metallization layers are provided on the semiconductor holding plate, and a semiconductor element is mounted on one of these metallization layers. Of the metallized layers, the metallized layer serving as a ground electrode has an opening in the center of the lead of the input part, the output part, or both, and is grounded to the metal heat dissipation plate via the end face of the semiconductor holding plate. A semiconductor device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4292821A JP2812107B2 (en) | 1992-10-30 | 1992-10-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4292821A JP2812107B2 (en) | 1992-10-30 | 1992-10-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06151631A true JPH06151631A (en) | 1994-05-31 |
| JP2812107B2 JP2812107B2 (en) | 1998-10-22 |
Family
ID=17786786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4292821A Expired - Fee Related JP2812107B2 (en) | 1992-10-30 | 1992-10-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2812107B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6188127B1 (en) | 1995-02-24 | 2001-02-13 | Nec Corporation | Semiconductor packing stack module and method of producing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0452746U (en) * | 1990-09-11 | 1992-05-06 |
-
1992
- 1992-10-30 JP JP4292821A patent/JP2812107B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0452746U (en) * | 1990-09-11 | 1992-05-06 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6188127B1 (en) | 1995-02-24 | 2001-02-13 | Nec Corporation | Semiconductor packing stack module and method of producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2812107B2 (en) | 1998-10-22 |
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