JPH06151584A - Method for dicing semiconductor device - Google Patents
Method for dicing semiconductor deviceInfo
- Publication number
- JPH06151584A JPH06151584A JP32129792A JP32129792A JPH06151584A JP H06151584 A JPH06151584 A JP H06151584A JP 32129792 A JP32129792 A JP 32129792A JP 32129792 A JP32129792 A JP 32129792A JP H06151584 A JPH06151584 A JP H06151584A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- protective film
- dicing
- cutting path
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置のダイシング
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device dicing method.
【0002】[0002]
【従来の技術】従来、半導体ウエハーをチップに切断す
る(ダイシングする)際に、チップ固定テープをチップ
のパターン面とは反対側のウェハー裏面にはりつけ、パ
ターン面側からダイシングソーを当てるようにしている
が、チップとチップとの間の切断経路領域上には保護膜
は付けないのが普通である。また例えば特公平3-43785
号公報に見られるごとく、チップの電極以外の部分に第
一の保護膜を形成し、さらに、チップの端からの水分の
侵入防止や防湿等のために第二の有機樹脂保護膜を第一
の保護膜上に被覆する場合があるが、その場合でも切断
経路上は保護膜を被覆していなかった。また、チップ固
定テープをチップパターン面側に貼りつける場合もある
が、その場合にはテープの接着を良くするために、チッ
プとチップとの間の切断経路上に樹脂をチップ上とほぼ
同じ高さまで充填するようにして被覆して、その上にテ
ープを貼るようにしている。2. Description of the Related Art Conventionally, when cutting (dicing) a semiconductor wafer into chips, a chip fixing tape is attached to the back surface of the wafer opposite to the pattern surface of the chips, and a dicing saw is applied from the pattern surface side. However, a protective film is not usually provided on the cutting path region between chips. Also, for example, Japanese Examined Patent Publication 3-43785
As seen in Japanese Patent Publication No. JP-A-2004-96242, a first protective film is formed on a portion other than the electrodes of the chip, and a second organic resin protective film is first formed to prevent intrusion of moisture from the edge of the chip and to prevent moisture. In some cases, the protective film was not coated on the cutting path. There is also a case where a chip fixing tape is attached to the chip pattern surface side. In that case, in order to improve the adhesiveness of the tape, the resin is placed on the cutting path between the chips at the same height as that on the chips. It covers so that it may be filled up, and the tape may be stuck on it.
【0003】[0003]
【発明が解決しようとする課題】ここで、切断経路上に
保護膜が無いとチップダイシング時に基板に欠けが発生
するため、チップパターンが破壊されないよう余裕をも
って切断経路領域を設定する必要がある。また通常、第
一の保護膜はパッシベーション保護膜と言われ、無機性
絶縁膜の固い材料で形成される。そのため、これが切断
経路上にあるとカッターの刃が破損しやすいという問題
があり、やはり切断経路上には被覆されていない。さら
に、図3に示すように、第一の保護膜の保護のために第
二の保護膜として樹脂膜を形成する場合でも、切断経路
上に樹脂膜を形成した例はなく、むしろそのためにかえ
って切断経路幅は広がっていた。また、チップ固定テー
プをチップ側に貼りつける場合には、サンドイッチ構造
で基板を保護するのではなく元々テープの接着性を良く
するためのものであり、また有機物保護膜がチップ上と
同じ高さまで被覆されているため、保護膜が薄い場合に
比べて剥がれやすいという問題があった。Here, if there is no protective film on the cutting path, the substrate will be chipped during chip dicing, so it is necessary to set the cutting path region with a margin so that the chip pattern is not destroyed. Further, usually, the first protective film is called a passivation protective film and is formed of a hard material of an inorganic insulating film. Therefore, there is a problem that the blade of the cutter is easily damaged when it is on the cutting path, and again, the cutting path is not covered. Further, as shown in FIG. 3, even when the resin film is formed as the second protective film for protecting the first protective film, there is no example in which the resin film is formed on the cutting path, and rather, for that reason. The cutting path width was wide. Also, when sticking the chip fixing tape to the chip side, it is not intended to protect the substrate with a sandwich structure but to improve the adhesiveness of the tape originally, and the organic protective film is up to the same height as the chip. Since it is covered, there is a problem that it is easier to peel off than when the protective film is thin.
【0004】[0004]
【課題を解決するための手段】上記の問題を解決するた
めの本発明の構成は、所定の半導体素子パターンが形成
されたウェハーを各チップごとにダイシングソーで切断
するダイシング方法において、ウェハーの切断経路上で
ダイシングソーが直接基板に接触しない様に切断経路上
の一部またはすべてを有機保護膜で被覆し、パターンの
形成されていないウェハー裏面にチップ固定テープを貼
付し、前記切断経路上に於いてダイシングソーを移動さ
せてダイシングすることを特徴とする。The structure of the present invention for solving the above problems is a dicing method in which a wafer on which a predetermined semiconductor element pattern is formed is cut with a dicing saw for each chip. A part or all of the cutting path is covered with an organic protective film so that the dicing saw does not directly contact the substrate on the path, and a chip fixing tape is attached to the back surface of the wafer on which no pattern is formed. It is characterized in that the dicing saw is moved to perform dicing.
【0005】[0005]
【作用】以上の構成のため、チップ固定テープと有機樹
脂保護膜とで、切断経路領域で基板をサンドイッチ状に
保護し、ダイシングソーが直接基板に当たらないで切断
が始まる。切断中は基板より柔らかな有機樹脂保護膜が
ダイシングソーと基板との間に細かくなって入り込む。With the above structure, the chip fixing tape and the organic resin protective film protect the substrate in a sandwiched manner in the cutting path region, and the dicing saw does not directly contact the substrate to start cutting. During the cutting, the organic resin protective film, which is softer than the substrate, becomes finely inserted between the dicing saw and the substrate.
【0006】[0006]
【発明の効果】切断経路領域の基板を保護することで基
板の欠けが抑えられるので、安全のために余分に取って
いた切断経路領域を狭くすることができ、その分ウエハ
ー上のチップ占有率が増え、また、有機樹脂保護膜がチ
ップの保護になるので、パッケージ組付け時にも欠けな
どが防げる。さらに、有機樹脂が潤滑材の役割を果た
し、カッターの振れが弱まり、切りしろがわずかながら
狭く抑えられてダイシングソーの寿命が延び、半導体装
置の歩留りが向上しコストダウンがはかれる。By protecting the substrate in the cutting path region, chipping of the substrate can be suppressed, so that the cutting path region, which has been taken extra for safety, can be narrowed, and the chip occupancy ratio on the wafer can be reduced accordingly. In addition, since the organic resin protective film protects the chip, chipping and the like can be prevented even when assembling the package. Further, the organic resin plays the role of a lubricant, the shake of the cutter is weakened, the cutting margin is slightly narrowed, the life of the dicing saw is extended, the yield of semiconductor devices is improved, and the cost is reduced.
【0007】[0007]
【実施例】以下、本発明を具体的な実施例に基づいて説
明する。図1は、本発明を施した一実施例を示す。基板
101の下側にチップ固定テープ107があり、それと
ともに基板を挟み込む形で切断経路部分に樹脂膜106
を形成する。105はチップの第一の保護膜、即ちPS
G(リンガラス)などの無機質パッシベーション膜であ
り、チップを形成している酸化絶縁膜102、層間絶縁
膜103、チップの電極取出し端子104の一部を保護
している。樹脂膜106は、元々第一の保護膜105の
保護膜として利用されている材料であり、本発明のため
には切断経路上にわずかに保護膜が存在するだけで効果
があるので、その設計は第一の保護膜105の保護を主
として形成される。樹脂膜材としてはポリイミド系樹脂
を用いた。なお、チップ固定テープ107は切断後に各
チップがバラバラにならないためのもので、図1の (b)
のように、テープの全てを切ってしまわないようにダイ
シングソーを制御する。EXAMPLES The present invention will be described below based on specific examples. FIG. 1 shows an embodiment of the present invention. There is a chip fixing tape 107 on the lower side of the substrate 101, and the resin film 106 is provided on the cutting path portion so as to sandwich the substrate with the chip fixing tape 107.
To form. 105 is the first protective film of the chip, namely PS
It is an inorganic passivation film such as G (phosphorus glass), and protects a part of the oxide insulating film 102, the interlayer insulating film 103, and the electrode lead-out terminal 104 of the chip which form the chip. The resin film 106 is a material originally used as a protective film for the first protective film 105. For the present invention, the presence of a slight protective film on the cutting path is effective, and therefore the design thereof is designed. Is mainly formed to protect the first protective film 105. A polyimide resin was used as the resin film material. It should be noted that the chip fixing tape 107 is used to prevent the chips from being separated after cutting.
Control the dicing saw so that it does not cut all of the tape, as in.
【0008】図1 (a)はチップに切断する前のウエハー
の切断経路領域の断面図で、W1は切断経路領域の幅を
示す。図1 (b)はダイシングした後の状態で、W2はダ
イシングソーの切り幅、W3は基板の欠け幅を示す。比
較として図2に同様のウエハーで保護膜なしの従来の方
法を示す。図2 (a)はダイシング前、図2 (b)はダイシ
ング後であり、W4が切断経路幅、W6は保護膜の無い
場合の欠けの幅でW3よりも大きい。従って、W4はW
1より大きく取る必要があった。発明者らの実測では、
図6に示すように、従来の欠け幅W6は最大20μmであ
り、W3は 5μm以下でほとんど観測不能であった。ま
た従来、W4は欠け幅を考慮して図3の場合には第一の
保護膜と第二の保護膜との重なりを5μmとるとすれば
約90μmにもなり、ダイシングソーの倍以上の切断経路
幅が必要だったが、本実施例の場合のW1は50μmで済
んでおり、40%以上の節約となった。切断後のW2は
ダイシングソーの切り幅であるが、従来の場合のW5よ
りわずかながら狭い。発明者らの実測ではダイシングソ
ーの幅37.5μmに対し、切り幅W5は42μmであったの
が、切り幅W2は40μmとなっており、この点でも改善
の効果が得られていた。このように、本発明は切断経路
を狭く設定することが可能で、1枚のウェハー上のチッ
プ集積率を向上させることができる。FIG. 1A is a cross-sectional view of the cutting path region of the wafer before being cut into chips, and W1 indicates the width of the cutting path region. FIG. 1 (b) shows a state after dicing, where W2 is a cutting width of the dicing saw and W3 is a chipping width of the substrate. As a comparison, FIG. 2 shows a conventional method without a protective film on a similar wafer. 2 (a) is before dicing and FIG. 2 (b) is after dicing. W4 is a cutting path width, W6 is a width of a chip without a protective film, and is larger than W3. Therefore, W4 is W
It was necessary to take more than 1. According to the inventors' actual measurement,
As shown in FIG. 6, the conventional chip width W6 was 20 μm at maximum and W3 was 5 μm or less, which was almost unobservable. Conventionally, W4 is about 90 μm if the overlap between the first protective film and the second protective film is 5 μm in the case of FIG. Although the width of the path was required, W1 in this example was 50 μm, which was a saving of 40% or more. Although W2 after cutting is the width of the dicing saw, it is slightly narrower than W5 in the conventional case. According to the actual measurement conducted by the inventors, the cutting width W5 was 42 μm with respect to the dicing saw width of 37.5 μm, but the cutting width W2 was 40 μm, and the improvement effect was obtained also in this respect. As described above, according to the present invention, the cutting path can be set narrow, and the chip integration rate on one wafer can be improved.
【0009】さらに、本実施例によれば、ダイシングソ
ーの寿命を延長させることができた。図5に示すよう
に、平均して2割以上寿命が延びた結果が得られてい
る。これは、樹脂がダイシングソーに掛かることによ
り、樹脂が基板に対して潤滑の役割を果たしているため
とみられ、そのために欠けも発生しにくいとみられる。Further, according to this embodiment, the life of the dicing saw can be extended. As shown in FIG. 5, the result that the life is extended by 20% or more on average is obtained. This is considered to be because the resin plays a role of lubricating the substrate when the resin is hung on the dicing saw, and it is considered that chipping is unlikely to occur because of this.
【0010】本発明の他の実施例として、図4に示すよ
うに、必ずしも切断経路上すべてに樹脂膜が形成されて
いなくても、図4のW8で示す幅がダイシングソーの切
り幅(図1のW2)より狭く、ダイシングソーに当たる
領域まで樹脂で覆われたサンドイッチ構造であれば、上
記の理由から同様の効果を発揮する。また、樹脂膜はポ
リイミド系樹脂だけではなく、耐熱性、密着性、電気的
絶縁性、弾性、清浄性がある樹脂であればよい。As another embodiment of the present invention, as shown in FIG. 4, even if the resin film is not necessarily formed on the entire cutting path, the width indicated by W8 in FIG. If the sandwich structure is narrower than W2) of No. 1 and the region corresponding to the dicing saw is covered with the resin, the same effect is exhibited for the above reason. Further, the resin film is not limited to the polyimide resin, and may be a resin having heat resistance, adhesion, electrical insulation, elasticity, and cleanability.
【図1】本発明の一実施例を示す半導体基板の断面図。FIG. 1 is a sectional view of a semiconductor substrate showing an embodiment of the present invention.
【図2】従来例を示す半導体基板の断面図。FIG. 2 is a sectional view of a semiconductor substrate showing a conventional example.
【図3】従来の別の例を示す半導体基板の断面図。FIG. 3 is a sectional view of a semiconductor substrate showing another conventional example.
【図4】本発明の別の実施例を示す半導体基板の断面
図。FIG. 4 is a sectional view of a semiconductor substrate showing another embodiment of the present invention.
【図5】ダイシングソーの使用回数の比較図。FIG. 5 is a comparison diagram of the number of times the dicing saw is used.
【図6】切断後のチップの欠け幅の比較図。FIG. 6 is a comparative diagram of chip chip widths after cutting.
101 半導体基板 102 酸化絶縁膜 103 層間絶縁膜 106 樹脂保護膜 107 チップ固定テープ 101 Semiconductor Substrate 102 Oxide Insulating Film 103 Interlayer Insulating Film 106 Resin Protective Film 107 Chip Fixing Tape
───────────────────────────────────────────────────── フロントページの続き (72)発明者 奥村 寿浩 愛知県刈谷市昭和町1丁目1番地 日本電 装株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Okumura 1-1-1, Showa-cho, Kariya city, Aichi prefecture Nihon Denso Co., Ltd.
Claims (1)
ェハーを各チップごとにダイシングソーで切断するダイ
シング方法において、前記ウェハーの切断経路上におい
て前記ダイシングソーが直接基板に接触しない様に前記
切断経路上を有機保護膜で被覆し、前記ウェハーのパタ
ーンの形成されていない裏面にチップ固定テープを貼付
し、前記切断経路上において、ダイシングソーを移動さ
せてダイシングすることを特徴とする半導体装置のダイ
シング方法。1. A dicing method for cutting a wafer on which a predetermined semiconductor element pattern has been formed into chips by a dicing saw so that the dicing saw does not come into direct contact with the substrate on the wafer cutting path. Dicing of a semiconductor device characterized by covering the top with an organic protective film, attaching a chip fixing tape to the back surface of the wafer on which no pattern is formed, and moving the dicing saw on the cutting path to perform dicing. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32129792A JPH06151584A (en) | 1992-11-04 | 1992-11-04 | Method for dicing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32129792A JPH06151584A (en) | 1992-11-04 | 1992-11-04 | Method for dicing semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06151584A true JPH06151584A (en) | 1994-05-31 |
Family
ID=18131007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32129792A Pending JPH06151584A (en) | 1992-11-04 | 1992-11-04 | Method for dicing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06151584A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521125A (en) * | 1994-10-28 | 1996-05-28 | Xerox Corporation | Precision dicing of silicon chips from a wafer |
DE19713172A1 (en) * | 1997-03-27 | 1998-07-30 | Siemens Ag | Semiconductor component with edges coated for separation from wafer |
JP2006303166A (en) * | 2005-04-20 | 2006-11-02 | Seiko Epson Corp | Thin film element, manufacturing method therefor, and electronic equipment |
US7867825B2 (en) * | 2004-09-30 | 2011-01-11 | Samsung Electronics Co., Ltd. | Semiconductor die with protective layer and related method of processing a semiconductor wafer |
WO2017115435A1 (en) * | 2015-12-28 | 2017-07-06 | オリンパス株式会社 | Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method |
-
1992
- 1992-11-04 JP JP32129792A patent/JPH06151584A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521125A (en) * | 1994-10-28 | 1996-05-28 | Xerox Corporation | Precision dicing of silicon chips from a wafer |
DE19713172A1 (en) * | 1997-03-27 | 1998-07-30 | Siemens Ag | Semiconductor component with edges coated for separation from wafer |
US7867825B2 (en) * | 2004-09-30 | 2011-01-11 | Samsung Electronics Co., Ltd. | Semiconductor die with protective layer and related method of processing a semiconductor wafer |
US8871614B2 (en) | 2004-09-30 | 2014-10-28 | Samsung Electronics Co., Ltd. | Semiconductor die with protective layer and related method of processing a semiconductor wafer |
JP2006303166A (en) * | 2005-04-20 | 2006-11-02 | Seiko Epson Corp | Thin film element, manufacturing method therefor, and electronic equipment |
WO2017115435A1 (en) * | 2015-12-28 | 2017-07-06 | オリンパス株式会社 | Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method |
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