WO2017115435A1 - Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method - Google Patents
Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method Download PDFInfo
- Publication number
- WO2017115435A1 WO2017115435A1 PCT/JP2015/086561 JP2015086561W WO2017115435A1 WO 2017115435 A1 WO2017115435 A1 WO 2017115435A1 JP 2015086561 W JP2015086561 W JP 2015086561W WO 2017115435 A1 WO2017115435 A1 WO 2017115435A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating layer
- scribe line
- semiconductor
- semiconductor chip
- semiconductor wafer
- Prior art date
Links
Images
Definitions
- the present invention relates to a semiconductor wafer, a semiconductor chip, and a method for manufacturing a semiconductor chip.
- a technique for preventing chipping a technique is disclosed in which a concave groove is formed by etching on a scribe line of a semiconductor chip, and then a metal line made of metal alloyed with a semiconductor substrate is formed inside the concave groove (for example, see Patent Document 1).
- Patent Document 2 a semiconductor chip having a convex portion and / or a concave portion on the chip surface between the element portion and the chip end has been proposed (for example, Patent Document 2).
- Patent Documents 1 and 2 can reduce the defect rate due to chipping or cutting chips, respectively, they do not achieve the prevention of chipping and the reduction of the defect rate due to cutting chips at the same time.
- the present invention has been made in view of the above, and even in a miniaturized semiconductor chip, a semiconductor wafer, a semiconductor chip, and a semiconductor chip that can simultaneously achieve the prevention of chipping and the reduction of the defect rate due to cutting scraps, etc. It aims at providing the manufacturing method of.
- a semiconductor wafer according to the present invention is a semiconductor wafer in which a plurality of semiconductor elements are formed in a lattice shape on one surface, and the semiconductor substrate on which the element portions are formed. And an insulating layer laminated on the surface of the semiconductor substrate on which the element portion is formed, a scribe line provided around the element portion, which is a cutting region when the element portion is separated into pieces by dicing, An insulating scattering prevention member provided on the scribe line and on an end portion of the insulating layer and having a concave cross section perpendicular to the scribe line.
- the scattering prevention member is integrally formed with the bottom surface portion directly formed on the scribe line and the bottom surface portion on the end portion of the insulating layer.
- a wall portion, and a side surface of the wall portion on the side of the bottom surface portion is tapered.
- the side surface of the wall portion on the bottom surface portion side is located closer to the element portion than the boundary between the insulating layer and the scribe line. .
- an electrode pad is formed in the vicinity of one side of the element portion of the insulating layer, and a wall portion of the scattering prevention member in the vicinity of the electrode pad is adjacent. It is lower than the wall portion on the element portion side.
- a semiconductor chip provided with a semiconductor substrate on which an element portion is formed, an insulating layer laminated on a formation surface of the element portion of the semiconductor substrate, and around the element portion.
- a scribe line which is a cutting area when the element part is singulated, on the remaining part of the scribe line, and on the end of the insulating layer, and the cross section perpendicular to the scribe line is L-shaped.
- an insulating scattering prevention member is provided on the remaining part of the scribe line, which is a cutting area when the element part is singulated, on the remaining part of the scribe line, and on the end of the insulating layer, and the cross section perpendicular to the scribe line.
- a method for manufacturing a semiconductor chip according to the present invention is a method for manufacturing a semiconductor chip for dicing a semiconductor wafer in which an insulating layer for protecting the element portion is laminated on a semiconductor substrate having a plurality of element portions.
- a scattering prevention member forming step for forming an insulating scattering prevention member, which is provided on a scribe line around the element portion and on an end portion of the insulating layer and has a concave cross section perpendicular to the scribe line, and dicing A step of dicing the semiconductor substrate from above the anti-scattering member with a blade to divide the semiconductor chip into individual pieces.
- the present invention it is possible to prevent defects due to chipping, cutting waste, and the like adhering to the element portion, and thus it is possible to provide a highly reliable semiconductor chip.
- FIG. 1 is a plan view illustrating a semiconductor wafer according to an embodiment of the present invention.
- FIG. 2 is a partially enlarged plan view of the semiconductor chip before dicing.
- FIG. 3 is a cross-sectional view of a diced semiconductor chip.
- FIG. 4 is a diagram for explaining dicing of a semiconductor wafer.
- FIG. 5 is a diagram for explaining dicing of a semiconductor wafer.
- FIG. 6 is a diagram illustrating the formation of the scattering prevention member.
- FIG. 7 is an enlarged cross-sectional view of an end portion of a semiconductor chip according to Modification 1 of the embodiment of the present invention.
- FIG. 8 is a cross-sectional view illustrating a semiconductor wafer according to Modification 2 of the embodiment of the present invention.
- FIG. 9 is a cross-sectional view illustrating a semiconductor wafer according to Modification 3 of the embodiment of the present invention.
- FIG. 1 is a plan view illustrating a semiconductor wafer according to an embodiment of the present invention.
- FIG. 2 is a partially enlarged plan view of the semiconductor wafer.
- FIG. 3 is a cross-sectional view of a diced semiconductor chip.
- semiconductor chips 1 having a plurality of element portions 11 are formed in a lattice shape, and scribe lines S are formed around each semiconductor chip 1.
- the scribe line S is a cutting area when the semiconductor chip 1 is separated into pieces. By dicing the semiconductor wafer 100 along the scribe line S, the semiconductor chip 1 having the element portion 11 is separated into pieces.
- the semiconductor chip 1 includes a semiconductor substrate 10, an element portion 11, an electrode pad 12 formed near one side of the element portion 11, and an insulating layer formed so as to cover the element portion 11. 13 and a scattering prevention member 14 formed on the outer periphery of the semiconductor chip 1.
- a plurality of electrode pads 12 are formed in the vicinity of one side of the element part 11, but the present invention is not limited to this, and the electrode pad 12 is provided in the vicinity of two opposite sides of the element part 11.
- the electrode pad 12 may be formed in the vicinity of one side of the element portion 11, and the peripheral circuit may be formed on the opposite side of the side on which the electrode pad 12 is formed.
- the scattering prevention member 14 is made of an insulating material, and is provided on the scribe line S and on the end of the insulating layer 13.
- the scattering prevention member 14 includes a bottom surface portion 14 a formed directly on the scribe line S on the surface of the semiconductor substrate 10, and a wall portion 14 b formed integrally with the bottom surface portion 14 a on the end portion of the insulating layer 13.
- the anti-scattering member 14 has a cross section perpendicular to the scribe line S in a concave shape in the state of the semiconductor wafer 100 and an L shape in the state of the separated semiconductor chip 1.
- the scattering prevention member 14 it is preferable to select a material having a material constant similar to that of the semiconductor substrate 10 from the viewpoint of easy dicing at the time of dicing, prevention of chipping of the semiconductor substrate 10, and reduction of cutting waste.
- a material for the scattering prevention member 14 a photosensitive resin material such as a polyimide resin can be used.
- FIG. 4 and 5 are diagrams for explaining dicing of the semiconductor wafer 100.
- FIG. 4 and 5 are cross-sectional views taken along line AA in FIG.
- the semiconductor wafer 100 is diced by the dicing blade 20 along the dicing line S from above the scattering prevention member 14.
- the dicing blade 20 dices the anti-scattering member 14
- cracks may occur in the anti-scattering member 14.
- the influence of the cracks on the element unit 11 is suppressed. Can do.
- the scattering prevention member 14 of this Embodiment since the scattering prevention member 14 of this Embodiment has the wall part 14b, it supplies on the scribe line S for the prevention of scattering of the cutting waste generated at the time of dicing and cutting waste, and cooling of the semiconductor substrate 10. Scattering of the cutting water to the element portion 11 can be effectively prevented.
- the width r1 of the bottom surface portion 14a of the scattering preventing member 14 is larger than the kerf width r2 of the dicing blade 20 and preferably 5 ⁇ m or more in order to prevent interference between the dicing blade 20 and the wall portion 14b during dicing. Is preferred.
- the thickness h1 of the bottom surface portion 14a is preferably 2 ⁇ m or more and 5 ⁇ m or less. By setting the thickness h1 of the bottom surface portion 14a to 2 ⁇ m or more, chipping of the semiconductor substrate 10 can be prevented. Further, by setting the thickness h1 of the bottom surface portion 14a to 5 ⁇ m or less, the height of the wall portion 14b from the insulating layer 13 is suppressed, and dicing becomes easy.
- the height h2 of the wall portion 14b from the bottom surface portion 14a is preferably 5 ⁇ m or more and 30 ⁇ m or less. By making the height h2 from the bottom surface part 14a of the wall part 14b to be 5 ⁇ m or more, it is possible to effectively prevent the scattering of cutting waste and cutting water. By setting the height h2 from the bottom surface portion 14a of the wall portion 14b to 30 ⁇ m or less, the lead can be easily connected to the electrode pad 12.
- a photosensitive resin material 141 that is a material of the scattering prevention member 14 is applied by spin coating or the like (FIG. 6). (See (b)).
- the photosensitive resin material 141 is exposed and developed through the mask 30 (see FIG. 6C), and the shape of the anti-scattering member 14 that does not have the bottom surface portion 14a is patterned on the photosensitive resin material 141 (see FIG. 6). 6 (d)).
- the photosensitive resin material 141 is exposed and developed again with the mask 31 that patterns the shape of the bottom surface portion 14a (see FIG. 6E), and the photosensitive resin material 141 is heated to form the scattering prevention member 14. .
- the semiconductor wafer 100 according to the present embodiment includes the insulating scattering prevention member 14 having a concave cross section on the scribe line S, it is possible to prevent scattering of cutting waste and cutting water generated during dicing. Defects of the semiconductor chip 1 due to adhesion of debris or the like to the element unit 11 can be reduced.
- the scattering prevention member 14 since the semiconductor wafer 100 is diced through the scattering prevention member 14, the occurrence of cracks in the semiconductor substrate 10 can be prevented. Furthermore, since the scattering preventing member 14 is provided on the scribe line S and on the end portion of the insulating layer 13, the area required for the scribe line S can be reduced and the yield of the semiconductor chip 1 can be improved.
- a semiconductor chip including an image sensor as an element portion has been described.
- the present invention is not limited to this, and the semiconductor chip 1 that does not form a protective film on the insulating layer 13, for example, MEMS ( It can also be applied to Micro Electro Mechanical Systems).
- FIG. 7 is an enlarged cross-sectional view of an end portion of a semiconductor chip according to Modification 1 of the embodiment of the present invention.
- the side surface f1 on the bottom surface portion 14a side of the wall portion 14b of the scattering prevention member 14A is located closer to the element portion 11 than the boundary f2 between the insulating layer 13 and the scribe line S.
- the width of the scribe line S can be further shortened, and the yield of the semiconductor chip can be improved.
- FIG. 8 is a cross-sectional view illustrating a semiconductor wafer according to Modification 2 of the embodiment of the present invention.
- the side surface f1 on the bottom surface portion 14a side of the wall portion 14b of the scattering prevention member 14B is tapered, and the inside of the scattering prevention member 14B has an inverted trapezoidal shape.
- FIG. 9 is a cross-sectional view illustrating a semiconductor wafer according to Modification 3 of the embodiment of the present invention. Note that FIG. 9 is a cross-sectional view taken along the line BB in FIG.
- the height h2 from the bottom surface portion 14a of the wall portion 14b-2 of the scattering prevention member 14C in the vicinity of the electrode pad 12 is equal to the bottom surface portion 14a of the wall portion 14b-1 on the adjacent element portion 11-1 side. Is lower than the height h3.
- the height of the wall portion 14b-2 in the vicinity of the electrode pad 12 is also preferably high from the viewpoint of preventing scattering of cutting waste and the like.
- the electrode pad 12 is interposed between the wall portion 14b-2 and the element portion 11-2.
Landscapes
- Dicing (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Endoscopes (AREA)
Abstract
To provide: a semiconductor wafer whereby the rate of defectives due to chipping and cut chips can be reduced; a semiconductor chip; and a semiconductor chip manufacturing method. A semiconductor wafer of the present invention has a plurality of element sections that are formed in a lattice shape in one surface. The semiconductor wafer is characterized by being provided with: a semiconductor substrate in which the element sections are formed; an insulating layer laminated on the element section forming surfasce of the semiconductor substrate; scribe lines, which are provided around the element sections, and which are to be used at the time of dividing the element sections into individual element sections by means of dicing; and an insulating scattering prevention member, which is provided on the scribe lines and end portion of the insulating layer, and in which a cross-section perpendicular to the scribe lines has a recessed shape.
Description
本発明は、半導体ウエハ、半導体チップ、および半導体チップの製造方法に関する。
The present invention relates to a semiconductor wafer, a semiconductor chip, and a method for manufacturing a semiconductor chip.
従来、半導体ウエハ上に複数の素子部を形成し、これらの素子部をダイシングにより切り離して半導体チップを製造することが広く行われている。近年、素子部および半導体チップの小型化に伴い、ダイシング時に発生する半導体チップのチッピング、およびダイシング時に発生するウエハの切削屑やチッピング片の素子部への付着による欠陥が問題となっている。
Conventionally, it has been widely practiced to manufacture a semiconductor chip by forming a plurality of element portions on a semiconductor wafer and separating these element portions by dicing. In recent years, with the miniaturization of the element portion and the semiconductor chip, chipping of the semiconductor chip that occurs during dicing, and defects due to adhesion of wafer chips and chipping pieces that occur during dicing to the element portion have become problems.
チッピングを防止する技術として、半導体チップのスクライブライン上にエッチングにより凹状溝を形成した後、該凹状溝の内部に半導体基板と合金化する金属からなる金属ラインを形成する技術が開示されている（例えば、特許文献１参照）。
As a technique for preventing chipping, a technique is disclosed in which a concave groove is formed by etching on a scribe line of a semiconductor chip, and then a metal line made of metal alloyed with a semiconductor substrate is formed inside the concave groove ( For example, see Patent Document 1).
一方、ウエハの切削屑による素子部の特性劣化を防止する技術として、素子部とチップ端との間のチップ表面に、凸部および/または凹部を備えた半導体チップが提案されている（例えば、特許文献２参照）。
On the other hand, as a technique for preventing deterioration of the characteristics of the element portion due to wafer cutting waste, a semiconductor chip having a convex portion and / or a concave portion on the chip surface between the element portion and the chip end has been proposed (for example, Patent Document 2).
特許文献１および２に開示の技術は、それぞれチッピングまたは切削屑による不良率を低減できるものの、チッピングの防止と切削屑による不良率の低減とを同時に達成するものではない。
Although the techniques disclosed in Patent Documents 1 and 2 can reduce the defect rate due to chipping or cutting chips, respectively, they do not achieve the prevention of chipping and the reduction of the defect rate due to cutting chips at the same time.
本発明は、上記に鑑みてなされたものであって、小型化された半導体チップにおいても、チッピングの防止と切削屑等による不良率の低減を同時に達成しうる半導体ウエハ、半導体チップ、および半導体チップの製造方法を提供することを目的とする。
The present invention has been made in view of the above, and even in a miniaturized semiconductor chip, a semiconductor wafer, a semiconductor chip, and a semiconductor chip that can simultaneously achieve the prevention of chipping and the reduction of the defect rate due to cutting scraps, etc. It aims at providing the manufacturing method of.
上述した課題を解決し、目的を達成するために、本発明にかかる半導体ウエハは、片面に複数の半導体素子が格子状に形成された半導体ウエハであって、前記素子部が形成された半導体基板と、前記半導体基板の前記素子部の形成面に積層されてなる絶縁層と、前記素子部の周囲に設けられ、ダイシングにより前記素子部を個片化する際の切削領域であるスクライブラインと、前記スクライブライン上、および前記絶縁層の端部上に設けられ、前記スクライブラインと垂直な断面が凹状をなす、絶縁性の飛散防止部材と、を備えることを特徴とする。
In order to solve the above-described problems and achieve the object, a semiconductor wafer according to the present invention is a semiconductor wafer in which a plurality of semiconductor elements are formed in a lattice shape on one surface, and the semiconductor substrate on which the element portions are formed. And an insulating layer laminated on the surface of the semiconductor substrate on which the element portion is formed, a scribe line provided around the element portion, which is a cutting region when the element portion is separated into pieces by dicing, An insulating scattering prevention member provided on the scribe line and on an end portion of the insulating layer and having a concave cross section perpendicular to the scribe line.
また、本発明にかかる半導体ウエハは、上記発明において、前記飛散防止部材は、前記スクライブライン上に直接形成される底面部と、前記絶縁層の端部上に前記底面部と一体に形成される壁部とを有し、前記壁部の前記底面部側の側面がテーパ状をなすことを特徴とする。
In the semiconductor wafer according to the present invention, the scattering prevention member is integrally formed with the bottom surface portion directly formed on the scribe line and the bottom surface portion on the end portion of the insulating layer. A wall portion, and a side surface of the wall portion on the side of the bottom surface portion is tapered.
また、本発明にかかる半導体ウエハは、上記発明において、前記壁部の前記底面部側の側面は、前記絶縁層と前記スクライブラインとの境界よりも前記素子部側に位置することを特徴とする。
In the semiconductor wafer according to the present invention as set forth in the invention described above, the side surface of the wall portion on the bottom surface portion side is located closer to the element portion than the boundary between the insulating layer and the scribe line. .
また、本発明にかかる半導体ウエハは、上記発明において、前記絶縁層の前記素子部の一辺の近傍には電極パッドが形成され、前記電極パッドの近傍の前記飛散防止部材の壁部は、隣接する前記素子部側の壁部より低いことを特徴とする。
In the semiconductor wafer according to the present invention, in the above invention, an electrode pad is formed in the vicinity of one side of the element portion of the insulating layer, and a wall portion of the scattering prevention member in the vicinity of the electrode pad is adjacent. It is lower than the wall portion on the element portion side.
また、本発明にかかる半導体チップは、素子部が形成された半導体基板と、前記半導体基板の前記素子部の形成面に積層されてなる絶縁層と、前記素子部の周囲に設けられ、ダイシングにより前記素子部を個片化する際の切削領域であるスクライブラインの残部と、前記スクライブラインの残部上、および前記絶縁層の端部上に設けられ、前記スクライブラインと垂直な断面がＬ字状をなす、絶縁性の飛散防止部材と、を備えることを特徴とする。
According to another aspect of the present invention, there is provided a semiconductor chip provided with a semiconductor substrate on which an element portion is formed, an insulating layer laminated on a formation surface of the element portion of the semiconductor substrate, and around the element portion. Provided on the remaining part of the scribe line, which is a cutting area when the element part is singulated, on the remaining part of the scribe line, and on the end of the insulating layer, and the cross section perpendicular to the scribe line is L-shaped. And an insulating scattering prevention member.
また、本発明にかかる半導体チップの製造方法は、複数の素子部を有する半導体基板上に前記素子部を保護する絶縁層が積層された半導体ウエハをダイシングする半導体チップの製造方法であって、前記素子部の周囲のスクライブライン上、および前記絶縁層の端部上に設けられ、前記スクライブラインと垂直な断面が凹状をなす、絶縁性の飛散防止部材を形成する飛散防止部材形成工程と、ダイシングブレードにより、前記飛散防止部材上から前記半導体基板をダイシングして、前記半導体チップを個片化する個片化工程と、を含むことを特徴とする。
A method for manufacturing a semiconductor chip according to the present invention is a method for manufacturing a semiconductor chip for dicing a semiconductor wafer in which an insulating layer for protecting the element portion is laminated on a semiconductor substrate having a plurality of element portions. A scattering prevention member forming step for forming an insulating scattering prevention member, which is provided on a scribe line around the element portion and on an end portion of the insulating layer and has a concave cross section perpendicular to the scribe line, and dicing A step of dicing the semiconductor substrate from above the anti-scattering member with a blade to divide the semiconductor chip into individual pieces.
本発明によれば、チッピングや切削屑等が素子部に付着することによる欠陥を防止できるため、信頼性の高い半導体チップを提供することができる。
According to the present invention, it is possible to prevent defects due to chipping, cutting waste, and the like adhering to the element portion, and thus it is possible to provide a highly reliable semiconductor chip.
以下の説明では、本発明を実施するための形態（以下、「実施の形態」という）として、素子部としてイメージセンサが形成された半導体ウエハについて説明する。また、この実施の形態により、この発明が限定されるものではない。さらに、図面の記載において、同一部分には同一の符号を付している。さらにまた、図面は、模式的なものであり、各部材の厚みと幅との関係、各部材の比率等は、現実と異なることに留意する必要がある。また、図面の相互間においても、互いの寸法や比率が異なる部分が含まれている。
In the following description, a semiconductor wafer on which an image sensor is formed as an element portion will be described as a mode for carrying out the present invention (hereinafter referred to as “embodiment”). Moreover, this invention is not limited by this embodiment. Furthermore, the same code | symbol is attached | subjected to the same part in description of drawing. Furthermore, the drawings are schematic, and it should be noted that the relationship between the thickness and width of each member, the ratio of each member, and the like are different from the actual ones. Moreover, the part from which a mutual dimension and ratio differ also in between drawings.
（実施の形態）
図１は、本発明の実施の形態にかかる半導体ウエハを説明する平面図である。図２は、半導体ウエハの一部拡大平面図である。図３は、ダイシングされた半導体チップの断面図である。 (Embodiment)
FIG. 1 is a plan view illustrating a semiconductor wafer according to an embodiment of the present invention. FIG. 2 is a partially enlarged plan view of the semiconductor wafer. FIG. 3 is a cross-sectional view of a diced semiconductor chip.
図１は、本発明の実施の形態にかかる半導体ウエハを説明する平面図である。図２は、半導体ウエハの一部拡大平面図である。図３は、ダイシングされた半導体チップの断面図である。 (Embodiment)
FIG. 1 is a plan view illustrating a semiconductor wafer according to an embodiment of the present invention. FIG. 2 is a partially enlarged plan view of the semiconductor wafer. FIG. 3 is a cross-sectional view of a diced semiconductor chip.
半導体ウエハ１００は、複数の素子部１１を有する半導体チップ１が格子状に形成されており、各半導体チップ１の周囲にはスクライブラインＳが形成されている。スクライブラインＳは、半導体チップ１を個片化する際の切削領域である。半導体ウエハ１００をスクライブラインＳでダイシングすることにより、素子部１１を有する半導体チップ１が個片化される。
In the semiconductor wafer 100, semiconductor chips 1 having a plurality of element portions 11 are formed in a lattice shape, and scribe lines S are formed around each semiconductor chip 1. The scribe line S is a cutting area when the semiconductor chip 1 is separated into pieces. By dicing the semiconductor wafer 100 along the scribe line S, the semiconductor chip 1 having the element portion 11 is separated into pieces.
半導体チップ１は、図３に示すように、半導体基板１０と、素子部１１と、素子部１１の一辺の近傍に形成された電極パッド１２と、素子部１１を覆うように形成される絶縁層１３と、半導体チップ１の外周上に形成される飛散防止部材１４と、を備える。
As shown in FIG. 3, the semiconductor chip 1 includes a semiconductor substrate 10, an element portion 11, an electrode pad 12 formed near one side of the element portion 11, and an insulating layer formed so as to cover the element portion 11. 13 and a scattering prevention member 14 formed on the outer periphery of the semiconductor chip 1.
本実施の形態では、電極パッド１２は、素子部１１の一辺の近傍に複数形成されているが、これに限定されるものではなく、素子部１１の対向する二辺の近傍に電極パッド１２が形成されていてもよく、あるいは、素子部１１の一辺の近傍に電極パッド１２が形成され、電極パッド１２が形成される側の対向する側に周辺回路が形成されていてもよい。
In the present embodiment, a plurality of electrode pads 12 are formed in the vicinity of one side of the element part 11, but the present invention is not limited to this, and the electrode pad 12 is provided in the vicinity of two opposite sides of the element part 11. Alternatively, the electrode pad 12 may be formed in the vicinity of one side of the element portion 11, and the peripheral circuit may be formed on the opposite side of the side on which the electrode pad 12 is formed.
飛散防止部材１４は、絶縁性の材料からなり、スクライブラインＳ上および絶縁層１３の端部上に設けられている。飛散防止部材１４は、半導体基板１０面のスクライブラインＳ上に直接形成される底面部１４ａと、絶縁層１３の端部上に底面部１４ａと一体に形成される壁部１４ｂと、を有する。飛散防止部材１４は、スクライブラインＳと垂直な断面が、半導体ウエハ１００の状態では凹状、個片化された半導体チップ１の状態ではＬ字状をなしている。
The scattering prevention member 14 is made of an insulating material, and is provided on the scribe line S and on the end of the insulating layer 13. The scattering prevention member 14 includes a bottom surface portion 14 a formed directly on the scribe line S on the surface of the semiconductor substrate 10, and a wall portion 14 b formed integrally with the bottom surface portion 14 a on the end portion of the insulating layer 13. The anti-scattering member 14 has a cross section perpendicular to the scribe line S in a concave shape in the state of the semiconductor wafer 100 and an L shape in the state of the separated semiconductor chip 1.
飛散防止部材１４は、ダイシングの際のダイシングの容易性、半導体基板１０のチッピング防止、および切削屑を低減する観点から、半導体基板１０の材料と材料定数が類似するものを選択することが好ましい。飛散防止部材１４の材料としては、感光性樹脂材料、例えば、ポリイミド樹脂等を使用することができる。
As the scattering prevention member 14, it is preferable to select a material having a material constant similar to that of the semiconductor substrate 10 from the viewpoint of easy dicing at the time of dicing, prevention of chipping of the semiconductor substrate 10, and reduction of cutting waste. As a material for the scattering prevention member 14, a photosensitive resin material such as a polyimide resin can be used.
図４および図５は、半導体ウエハ１００のダイシングを説明する図である。図４および図５は、図２のＡ－Ａ線で示す断面図である。図４および図５に示すように、半導体ウエハ１００は、飛散防止部材１４上からダイシングラインＳに沿ってダイシングブレード２０によりダイシングされる。スクライブラインＳとして設定された領域内の半導体基板１０を、飛散防止部材１４を介してダイシングすることにより、半導体基板１０のチッピングを防止し、切削屑の発生を低減することができる。ダイシングブレード２０が飛散防止部材１４をダイシングする際、飛散防止部材１４にクラックが発生する場合があるが、クラックは飛散防止部材１４内に留まるため、クラックによる素子部１１への影響を抑制することができる。
4 and 5 are diagrams for explaining dicing of the semiconductor wafer 100. FIG. 4 and 5 are cross-sectional views taken along line AA in FIG. As shown in FIGS. 4 and 5, the semiconductor wafer 100 is diced by the dicing blade 20 along the dicing line S from above the scattering prevention member 14. By dicing the semiconductor substrate 10 in the region set as the scribe line S via the scattering prevention member 14, chipping of the semiconductor substrate 10 can be prevented, and generation of cutting waste can be reduced. When the dicing blade 20 dices the anti-scattering member 14, cracks may occur in the anti-scattering member 14. However, since the cracks remain in the anti-scattering member 14, the influence of the cracks on the element unit 11 is suppressed. Can do.
また、本実施の形態の飛散防止部材１４は壁部１４ｂを有するので、ダイシングの際発生する切削屑や、切削屑の飛散防止および半導体基板１０の冷却のためにスクライブラインＳ上に供給される切削水の素子部１１への飛散を効果的に防止することができる。
Moreover, since the scattering prevention member 14 of this Embodiment has the wall part 14b, it supplies on the scribe line S for the prevention of scattering of the cutting waste generated at the time of dicing and cutting waste, and cooling of the semiconductor substrate 10. Scattering of the cutting water to the element portion 11 can be effectively prevented.
飛散防止部材１４の底面部１４ａの幅ｒ１は、ダイシングの際にダイシングブレード２０と壁部１４ｂとの干渉を防止するために、ダイシングブレード２０のカーフ幅ｒ２より大きく、好ましくは５μｍ以上大きくすることが好ましい。
The width r1 of the bottom surface portion 14a of the scattering preventing member 14 is larger than the kerf width r2 of the dicing blade 20 and preferably 5 μm or more in order to prevent interference between the dicing blade 20 and the wall portion 14b during dicing. Is preferred.
底面部１４ａの厚さｈ１は、２μｍ以上５μｍ以下とすることが好ましい。底面部１４ａの厚さｈ１を２μｍ以上とすることで、半導体基板１０のチッピングを防止することができる。また、底面部１４ａの厚さｈ１を５μｍ以下とすることで、壁部１４ｂの絶縁層１３からの高さを抑制し、ダイシングも容易となる。
The thickness h1 of the bottom surface portion 14a is preferably 2 μm or more and 5 μm or less. By setting the thickness h1 of the bottom surface portion 14a to 2 μm or more, chipping of the semiconductor substrate 10 can be prevented. Further, by setting the thickness h1 of the bottom surface portion 14a to 5 μm or less, the height of the wall portion 14b from the insulating layer 13 is suppressed, and dicing becomes easy.
壁部１４ｂの底面部１４ａからの高さｈ２は、５μｍ以上３０μｍ以下とすることが好ましい。壁部１４ｂの底面部１４ａからの高さｈ２を５μｍ以上とすることで、切削屑や切削水の飛散を効果的に防止することができる。壁部１４ｂの底面部１４ａからの高さｈ２を３０μｍ以下とすることで、電極パッド１２へのリードの接続が容易となる。
The height h2 of the wall portion 14b from the bottom surface portion 14a is preferably 5 μm or more and 30 μm or less. By making the height h2 from the bottom surface part 14a of the wall part 14b to be 5 μm or more, it is possible to effectively prevent the scattering of cutting waste and cutting water. By setting the height h2 from the bottom surface portion 14a of the wall portion 14b to 30 μm or less, the lead can be easily connected to the electrode pad 12.
次に、図６を参照して、飛散防止部材１４の形成について説明する。
Next, the formation of the anti-scattering member 14 will be described with reference to FIG.
素子部１１を覆うように絶縁層１３を形成した半導体ウエハ１００上に（図６（ａ）参照）、飛散防止部材１４の材料である感光性樹脂材料１４１をスピンコート等で塗布する（図６（ｂ）参照）。
On the semiconductor wafer 100 on which the insulating layer 13 is formed so as to cover the element portion 11 (see FIG. 6A), a photosensitive resin material 141 that is a material of the scattering prevention member 14 is applied by spin coating or the like (FIG. 6). (See (b)).
マスク３０を介して感光性樹脂材料１４１を露光、現像して（図６（ｃ）参照）、感光性樹脂材料１４１を、底面部１４ａを有しない飛散防止部材１４の形状をパターンニングする（図６（ｄ）参照）。
The photosensitive resin material 141 is exposed and developed through the mask 30 (see FIG. 6C), and the shape of the anti-scattering member 14 that does not have the bottom surface portion 14a is patterned on the photosensitive resin material 141 (see FIG. 6). 6 (d)).
その後、底面部１４ａの形状をパターニングするマスク３１により、再度感光性樹脂材料１４１を露光、現像し（図６（ｅ）参照）、感光性樹脂材料１４１を加熱して、飛散防止部材１４とする。
Thereafter, the photosensitive resin material 141 is exposed and developed again with the mask 31 that patterns the shape of the bottom surface portion 14a (see FIG. 6E), and the photosensitive resin material 141 is heated to form the scattering prevention member 14. .
本実施の形態にかかる半導体ウエハ１００は、スクライブラインＳ上に、断面凹状の絶縁性の飛散防止部材１４を備えることにより、ダイシング時に発生する切削屑や、切削水の飛散を防止できるため、切削屑等の素子部１１への付着による半導体チップ１の欠陥を低減できる。
Since the semiconductor wafer 100 according to the present embodiment includes the insulating scattering prevention member 14 having a concave cross section on the scribe line S, it is possible to prevent scattering of cutting waste and cutting water generated during dicing. Defects of the semiconductor chip 1 due to adhesion of debris or the like to the element unit 11 can be reduced.
また、飛散防止部材１４を介して半導体ウエハ１００をダイシングするため、半導体基板１０へのクラックの発生を防止できる。さらに、飛散防止部材１４を、スクライブラインＳ上、および絶縁層１３の端部上に設けているため、スクライブラインＳに要する面積を低減でき、半導体チップ１の収率を向上することができる。
In addition, since the semiconductor wafer 100 is diced through the scattering prevention member 14, the occurrence of cracks in the semiconductor substrate 10 can be prevented. Furthermore, since the scattering preventing member 14 is provided on the scribe line S and on the end portion of the insulating layer 13, the area required for the scribe line S can be reduced and the yield of the semiconductor chip 1 can be improved.
なお、上記の実施の形態は、素子部としてイメージセンサを備える半導体チップについて説明したが、これに限定されるものではなく、絶縁層１３上に保護膜を形成しない半導体チップ１、例えば、ＭＥＭＳ（Ｍｉｃｒｏ Ｅｌｅｃｔｒｏ Ｍｅｃｈａｎｉｃａｌ Ｓｙｓｔｅｍｓ）等にも適用可能である。
In the above embodiment, a semiconductor chip including an image sensor as an element portion has been described. However, the present invention is not limited to this, and the semiconductor chip 1 that does not form a protective film on the insulating layer 13, for example, MEMS ( It can also be applied to Micro Electro Mechanical Systems).
また、飛散防止部材の壁部の底面部側の側面は、絶縁層とスクライブラインとの境界よりも素子部側に位置させることが好ましい。図７は、本発明の実施の形態の変形例１にかかる半導体チップの端部の拡大断面図である。
Further, it is preferable that the side surface on the bottom surface side of the wall portion of the scattering prevention member is positioned closer to the element portion than the boundary between the insulating layer and the scribe line. FIG. 7 is an enlarged cross-sectional view of an end portion of a semiconductor chip according to Modification 1 of the embodiment of the present invention.
変形例１において、飛散防止部材１４Ａの壁部１４ｂの底面部１４ａ側の側面ｆ１は、絶縁層１３とスクライブラインＳとの境界ｆ２よりも素子部１１側に位置する。これにより、スクライブラインＳの幅をさらに短くでき、半導体チップの収率を向上することができる。
In the first modification, the side surface f1 on the bottom surface portion 14a side of the wall portion 14b of the scattering prevention member 14A is located closer to the element portion 11 than the boundary f2 between the insulating layer 13 and the scribe line S. Thereby, the width of the scribe line S can be further shortened, and the yield of the semiconductor chip can be improved.
さらに、飛散防止部材の壁部の底面部側の側面は、テーパ状をなすものであってもよい。図８は、本発明の実施の形態の変形例２にかかる半導体ウエハを説明する断面図である。
Furthermore, the side surface on the bottom surface side of the wall portion of the anti-scattering member may be tapered. FIG. 8 is a cross-sectional view illustrating a semiconductor wafer according to Modification 2 of the embodiment of the present invention.
変形例２において、飛散防止部材１４Ｂの壁部１４ｂの底面部１４ａ側の側面ｆ１は、テーパ状をなし、飛散防止部材１４Ｂの内部は逆台形形状となっている。側面ｆ１をテーパ状とすることにより、飛散防止部材１４Ｂの外部から内部への切削水の供給が容易となり、また、ダイシングブレードとの干渉も低減することができる。
In Modification 2, the side surface f1 on the bottom surface portion 14a side of the wall portion 14b of the scattering prevention member 14B is tapered, and the inside of the scattering prevention member 14B has an inverted trapezoidal shape. By making the side surface f1 into a tapered shape, the cutting water can be easily supplied from the outside to the inside of the anti-scattering member 14B, and interference with the dicing blade can be reduced.
さらにまた、電極パッドの近傍の飛散防止部材の壁部は、隣接する素子部側の壁部より低く形成してもよい。図９は、本発明の実施の形態の変形例３にかかる半導体ウエハを説明する断面図である。なお、図９は、図２でＢ－Ｂ線で示す位置における断面図である。
Furthermore, the wall portion of the scattering prevention member in the vicinity of the electrode pad may be formed lower than the wall portion on the adjacent element portion side. FIG. 9 is a cross-sectional view illustrating a semiconductor wafer according to Modification 3 of the embodiment of the present invention. Note that FIG. 9 is a cross-sectional view taken along the line BB in FIG.
変形例３において、電極パッド１２の近傍の飛散防止部材１４Ｃの壁部１４ｂ－２の底面部１４ａからの高さｈ２は、隣接する素子部１１－１側の壁部１４ｂ－１の底面部１４ａからの高さｈ３より低い。素子部１１－１および１１－２への切削屑等の飛散を防止するためには、壁部１４ｂの高さをある程度高くすることが必要であるが、高すぎると、電極パッド１２へのリードの接続が困難となる。電極パッド１２の近傍の壁部１４ｂ－２の高さも、切削屑等の飛散防止の観点では高い方が好ましいが、壁部１４ｂ－２と素子部１１－２との間には電極パッド１２が存在し、隣接する素子部１１－１と壁部１４ｂ－１との間の距離より長いため、壁部１４ｂ－２の高さｈ２を壁部１４ｂ－１の高さｈ３より低くしても、切削屑等の飛散による影響を小さくできる。
In Modification 3, the height h2 from the bottom surface portion 14a of the wall portion 14b-2 of the scattering prevention member 14C in the vicinity of the electrode pad 12 is equal to the bottom surface portion 14a of the wall portion 14b-1 on the adjacent element portion 11-1 side. Is lower than the height h3. In order to prevent scattering of cutting waste and the like to the element portions 11-1 and 11-2, it is necessary to increase the height of the wall portion 14b to some extent. Connection becomes difficult. The height of the wall portion 14b-2 in the vicinity of the electrode pad 12 is also preferably high from the viewpoint of preventing scattering of cutting waste and the like. However, the electrode pad 12 is interposed between the wall portion 14b-2 and the element portion 11-2. Existing and longer than the distance between the adjacent element portion 11-1 and the wall portion 14b-1, even if the height h2 of the wall portion 14b-2 is lower than the height h3 of the wall portion 14b-1, It is possible to reduce the influence of scattering of cutting wastes.
１ 半導体チップ
１０ 半導体基板
１１ 素子部
１２ 電極パッド
１３ 絶縁層
１４、１４Ａ、１４Ｂ、１４Ｃ 飛散防止部材
１４ａ 底面部
１４ｂ、１４ｂ－１、１４ｂ－２ 壁部 DESCRIPTION OFSYMBOLS 1 Semiconductor chip 10 Semiconductor substrate 11 Element part 12 Electrode pad 13 Insulating layer 14, 14A, 14B, 14C Anti-scattering member 14a Bottom part 14b, 14b-1, 14b-2 Wall part
１０ 半導体基板
１１ 素子部
１２ 電極パッド
１３ 絶縁層
１４、１４Ａ、１４Ｂ、１４Ｃ 飛散防止部材
１４ａ 底面部
１４ｂ、１４ｂ－１、１４ｂ－２ 壁部 DESCRIPTION OF
Claims (6)
- 片面に複数の素子部が格子状に形成された半導体ウエハであって、
前記素子部が形成された半導体基板と、
前記半導体基板の前記素子部の形成面に積層されてなる絶縁層と、
前記素子部の周囲に設けられ、ダイシングにより前記素子部を個片化する際の切削領域であるスクライブラインと、
前記スクライブライン上、および前記絶縁層の端部上に設けられ、前記スクライブラインと垂直な断面が凹状をなす、絶縁性の飛散防止部材と、
を備えることを特徴とする半導体ウエハ。 A semiconductor wafer in which a plurality of element portions are formed in a lattice shape on one side,
A semiconductor substrate on which the element portion is formed;
An insulating layer laminated on the formation surface of the element portion of the semiconductor substrate;
A scribe line that is provided around the element part and is a cutting region when the element part is separated into pieces by dicing,
An insulating scattering prevention member provided on the scribe line and on an end of the insulating layer, and having a concave cross section perpendicular to the scribe line;
A semiconductor wafer comprising: - 前記飛散防止部材は、前記スクライブライン上に直接形成される底面部と、前記絶縁層の端部上に前記底面部と一体に形成される壁部とを有し、
前記壁部の前記底面部側の側面がテーパ状をなすことを特徴とする請求項１に記載の半導体ウエハ。 The scattering prevention member has a bottom surface portion directly formed on the scribe line, and a wall portion formed integrally with the bottom surface portion on an end portion of the insulating layer,
The semiconductor wafer according to claim 1, wherein a side surface of the wall portion on the bottom surface portion side is tapered. - 前記壁部の前記底面部側の側面は、前記絶縁層と前記スクライブラインとの境界よりも前記素子部側に位置することを特徴とする請求項２に記載の半導体ウエハ。 3. The semiconductor wafer according to claim 2, wherein a side surface of the wall portion on the bottom surface portion side is located closer to the element portion than a boundary between the insulating layer and the scribe line.
- 前記絶縁層の前記素子部の一辺の近傍には電極パッドが形成され、
前記電極パッドの近傍の前記飛散防止部材の壁部は、隣接する前記素子部側の壁部より低いことを特徴とする請求項２または３に記載の半導体ウエハ。 An electrode pad is formed in the vicinity of one side of the element portion of the insulating layer,
4. The semiconductor wafer according to claim 2, wherein a wall portion of the scattering prevention member in the vicinity of the electrode pad is lower than a wall portion on the adjacent element portion side. - 素子部が形成された半導体基板と、
前記半導体基板の前記素子部の形成面に積層されてなる絶縁層と、
前記素子部の周囲に設けられ、ダイシングにより前記素子部を個片化する際の切削領域であるスクライブラインの残部と、
前記スクライブラインの残部上、および前記絶縁層の端部上に設けられ、前記スクライブラインと垂直な断面がＬ字状をなす、絶縁性の飛散防止部材と、
を備えることを特徴とする半導体チップ。 A semiconductor substrate having an element portion formed thereon;
An insulating layer laminated on the formation surface of the element portion of the semiconductor substrate;
The remainder of the scribe line which is provided around the element part and is a cutting area when the element part is separated into pieces by dicing,
An insulating scattering prevention member provided on the remaining part of the scribe line and on an end of the insulating layer, and having a cross-section perpendicular to the scribe line in an L shape;
A semiconductor chip comprising: - 複数の素子部を有する半導体基板上に前記素子部を保護する絶縁層が積層された半導体ウエハをダイシングする半導体チップの製造方法であって、
前記素子部の周囲のスクライブライン上、および前記絶縁層の端部上に設けられ、前記スクライブラインと垂直な断面が凹状をなす、絶縁性の飛散防止部材を形成する飛散防止部材形成工程と、
ダイシングブレードにより、前記飛散防止部材上から前記半導体基板をダイシングして、前記半導体チップを個片化する個片化工程と、
を含むことを特徴とする半導体チップの製造方法。 A method of manufacturing a semiconductor chip for dicing a semiconductor wafer in which an insulating layer for protecting the element portion is laminated on a semiconductor substrate having a plurality of element portions,
A scattering prevention member forming step for forming an insulating scattering prevention member, which is provided on the scribe line around the element portion and on the end portion of the insulating layer and has a concave cross section perpendicular to the scribe line,
By the dicing blade, the semiconductor substrate is diced from above the scattering prevention member, and the semiconductor chip is singulated,
A method for manufacturing a semiconductor chip, comprising:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2015/086561 WO2017115435A1 (en) | 2015-12-28 | 2015-12-28 | Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method |
| JP2016248828A JP2017120900A (en) | 2015-12-28 | 2016-12-22 | Semiconductor chip, imaging device, and endoscope |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2015/086561 WO2017115435A1 (en) | 2015-12-28 | 2015-12-28 | Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2017115435A1 true WO2017115435A1 (en) | 2017-07-06 |
Family
ID=59224842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2015/086561 WO2017115435A1 (en) | 2015-12-28 | 2015-12-28 | Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2017120900A (en) |
| WO (1) | WO2017115435A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03204953A (en) * | 1989-12-29 | 1991-09-06 | Fujitsu Ltd | Semiconductor device |
| JPH06151584A (en) * | 1992-11-04 | 1994-05-31 | Nippondenso Co Ltd | Method for dicing semiconductor device |
| JPH1116860A (en) * | 1997-05-27 | 1999-01-22 | Lg Semicon Co Ltd | Method of sawing semiconductor device |
| JP2003203882A (en) * | 2002-01-07 | 2003-07-18 | Murata Mfg Co Ltd | Semiconductor device and its manufacturing method |
| WO2014009997A1 (en) * | 2012-07-11 | 2014-01-16 | 三菱電機株式会社 | Semiconductor device and method for producing same |
-
2015
- 2015-12-28 WO PCT/JP2015/086561 patent/WO2017115435A1/en active Application Filing
-
2016
- 2016-12-22 JP JP2016248828A patent/JP2017120900A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03204953A (en) * | 1989-12-29 | 1991-09-06 | Fujitsu Ltd | Semiconductor device |
| JPH06151584A (en) * | 1992-11-04 | 1994-05-31 | Nippondenso Co Ltd | Method for dicing semiconductor device |
| JPH1116860A (en) * | 1997-05-27 | 1999-01-22 | Lg Semicon Co Ltd | Method of sawing semiconductor device |
| JP2003203882A (en) * | 2002-01-07 | 2003-07-18 | Murata Mfg Co Ltd | Semiconductor device and its manufacturing method |
| WO2014009997A1 (en) * | 2012-07-11 | 2014-01-16 | 三菱電機株式会社 | Semiconductor device and method for producing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017120900A (en) | 2017-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4751634B2 (en) | Manufacturing method of semiconductor device | |
| US8053337B2 (en) | Method of manufacturing semiconductor device | |
| JP5401301B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| JP2007194469A (en) | Method for manufacturing semiconductor device | |
| US20120286397A1 (en) | Die Seal for Integrated Circuit Device | |
| JP2006282480A (en) | Thin film-fitted glass substrate, method for producing the same, and semiconductor device using the same | |
| US20030162369A1 (en) | Semiconductor device and method for fabricating the same | |
| JP2008270232A (en) | Semiconductor device | |
| JP2007165789A (en) | Method for manufacturing semiconductor device | |
| US7211500B2 (en) | Pre-process before cutting a wafer and method of cutting a wafer | |
| JP5271610B2 (en) | Manufacturing method of semiconductor device | |
| US11145515B2 (en) | Manufacturing method of semiconductor device with attached film | |
| JP2006339189A (en) | Semiconductor wafer and semiconductor device using the same | |
| JP4491036B2 (en) | Manufacturing method of semiconductor device | |
| WO2017115435A1 (en) | Semiconductor wafer, semiconductor chip, and semiconductor chip manufacturing method | |
| JP2006108489A (en) | Manufacturing method of semiconductor device | |
| JP2006049419A (en) | Dicing method | |
| JP6591240B2 (en) | Device manufacturing method | |
| TWI549243B (en) | Semiconductor structure and manufacturing method thereof | |
| JP2011129612A (en) | Method for manufacturing semiconductor device and semiconductor device | |
| US8310032B2 (en) | Wafer and method of manufacturing semiconductor device | |
| JP2009076782A (en) | Semiconductor substrate and manufacturing method thereof, and semiconductor chip | |
| JP2011040611A (en) | Semiconductor device and method of manufacturing the same | |
| JP2016072413A (en) | Semiconductor device and manufacturing method of the same | |
| JP2008085043A (en) | Semiconductor wafer, semiconductor chip, and method of manufacturing semiconductor chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15912101 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 15912101 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: JP |