JPH06149864A - Vector processor - Google Patents

Abstract

PURPOSE:To obtain a vector processor capable of processing a macro operation code efficiently and at high speed with a small amount of materials. CONSTITUTION:This processor is equipped with arithmetic resources 6, 7 comprised of plural arithmetic parts consisting of a vector computing element which processes vector data held with vector registers VRO-VR31 and a scalar data buffer 5, and a second scalar data buffer 11 which fetches the data from the buffer on one side of two pairs of arithmetic resources 6, 7 and stores data to be inputted to a post-processing computing element 13. The resources 6, 7 after delivering a computed result to the second buffer 11 can start arithmetic processing by the next macro operation code without awaiting the completion of the processing of the post-processing computing element, which enables the processing of the macro operation code to be executed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device for executing an operation instruction (macro operation instruction) between all vector elements, and more particularly to a vector processing device provided with operation resources composed of a plurality of operation units. .

[0002]

2. Description of the Related Art In general, a vector processing device is provided with a plurality of vector arithmetic units for processing a plurality of vector elements of vector data in parallel in order to increase the processing speed of vector instructions. The processing speed of instructions is improved. The vector processing device having such a configuration is capable of performing arithmetic processing such as sum and product of vector data at a higher speed by simultaneously processing one instruction by a plurality of vector arithmetic units.

In this type of vector processing device, the intermediate result obtained by each vector operation unit is finally given for the operation instruction between all vector elements (macro operation instruction) such as inner product, summation, comparison and the like. Arithmetic processing is required.

As a conventional technique relating to a vector processing apparatus capable of processing such an operation instruction between all vector elements, for example, a technique described in Japanese Patent Laid-Open No. 63-10263 is known.

This prior art is a scalar data buffer that holds an intermediate result obtained by a vector operation unit,
A post-processing arithmetic unit for taking out data from the buffer and finally performing a post-processing operation is provided, whereby processing of operation instructions between all vector elements such as inner product, summation, and comparison is performed.

A conventional technique of this type will be described below with reference to the drawings.

FIG. 4 is a block diagram showing a configuration of a conventional technique having a computing resource and a post-processing computing unit, FIG. 5 is a block diagram showing a configuration of a conventional technique having a plurality of sets of computing resources and a post-processing computing unit, FIG. FIG. 6 is a diagram for explaining processing resources and a processing pitch of a post-processing operation unit when processing a macro operation instruction in FIG. 5. 4 and 5, 3, 12, 1
7 is a selector, 4 is a vector calculator, 5 is a scalar data buffer, 6 is a calculation resource, 6a to 6b are calculation units, 1
3 is a post-processing arithmetic unit, VR0 to VR31 are vector registers, and SR0 to SR31 are scalar registers.

In the prior art shown in FIG. 4, four vector calculators for processing 256 vector elements of vector data held in a vector register in parallel, and four vector calculators are provided.
And a post-processing arithmetic unit that takes out data from the scalar data buffer and finally performs post-processing, with arithmetic resources composed of four scalar data buffers that hold the intermediate results obtained by the vector arithmetic units 4. 2 is an example of a vector processing device configured as follows.

That is, the vector processing device shown in FIG. 4 is composed of a high speed random access memory (RAM), and can read and write independently of each other.
32 vector registers VR0 to VR31 capable of holding vector data of 6 elements, and 32 scalar registers SR0 to SR31 storing scalar data.
And a selector 3 of a switch matrix logic for selectively outputting the output data of the vector registers VR0 to VR31 and the scalar registers SR0 to SR31 to an arithmetic unit by an instruction.
And a plurality of arithmetic units 6a composed of the vector arithmetic unit 4 and the scalar data buffer 5 storing the arithmetic result thereof.
To 6d, the calculation resource 6 and the selector 3
Operand data supplied through
Operand paths 8a to 8h to be input to the following, an operand path 10 for inputting data of a scalar register designated by an operand to a post-processing arithmetic unit, a feedback path 20 of a post-processing arithmetic result, and each of the arithmetic resources 6 A selector 12 composed of a switch matrix logic for selecting and outputting input data of a post-processing arithmetic unit from data of the scalar data buffer 5 in the arithmetic unit, data of the scalar registers SR0 to SR31 and feedback data of the post-processing arithmetic result; A post-processing arithmetic unit 13 that calculates data in the scalar data buffer 5, data in the scalar registers SR0 to SR31, and feedback data of the post-processing arithmetic result, a result path 14 that outputs the arithmetic result of the vector arithmetic unit 4, and a post-processing arithmetic. Result path 1 which outputs the calculation result of the device 13 When the selector 17 composed of a switch matrix logic for selecting to write the operation result from the result path vector registers VR0~VR31 or scalar register SR0~SR31
And is configured.

The vector calculator 4 is an adder, a multiplier or a multiplier / adder, and in the case of an adder, a function of adding all input data {Σ [A (i) + B (i)]}.
And the function of comparing {MaxA (i), MinA (i)}
In the case of a multiplier, it has a function of multiplying input data and adding all the results {ΣA (i) × B (i)},
Further, in the case of the multiplier / adder, it has a function that the result of one arithmetic unit becomes the input data of the other arithmetic unit.

Although not shown, the illustrated vector processing device is provided with a load pipeline for supplying operand data from the main memory to the vector register and a store pipeline for storing data from the vector register in the main memory.

Next, in the vector processing device constructed as shown in FIG. 4, an inner product operation S = S + Σ {A (i) × B (i)} (i = 0 to 25) effective for solving simultaneous linear equations.
The operation when 5) is processed by one instruction as a macro operation instruction will be described.

Each of the arithmetic units 6a to 6d including the vector arithmetic unit (multiplier) 4 for performing an arithmetic operation on each element, the arithmetic unit 6a calculates Σ {A (4j) × B (4j)},
The calculation unit 6b calculates Σ {A (4j + 1) × B (4j + 1)}.
And the calculation unit 6c calculates Σ {A (4j + 2) × B (4
j + 2)}, and the calculation unit 6d calculates Σ {A (4j +
3) × B (4j + 3)} is calculated. However, j = 0 to 6
It is 3.

The intermediate result obtained by the vector calculator 4 is stored in the scalar data buffer 5. The selector 12 selects and outputs the input data to the post-processing arithmetic unit 13 from the paths 10, 47a to 47d, 20. The post-processing arithmetic unit 13 outputs the intermediate result of each vector arithmetic unit and the data of the scalar register designated by the operand. And all the sums of and are calculated, and the final result is output to the result path 16. The selector 17 selects one of the scalar registers SR0 to SR31 designated by the operand, writes this output, and ends the instruction.

In the above-mentioned prior art, since one post-processing arithmetic unit corresponds to the arithmetic resource composed of a plurality of vector arithmetic units corresponding to one vector data, the macro instruction, the continuous The vector instructions to be processed can be processed at high speed.

Next, another conventional technique capable of performing vector processing at a higher speed will be described with reference to FIGS.

The prior art shown in FIG. 5 is constructed by equipping a plurality of sets of arithmetic resources. In the prior art shown in FIG. 4, an arithmetic unit 7a constituted by a vector arithmetic unit 4 and a scalar data buffer 5 is provided. .About.7d, a set of calculation resources 7 is added.

That is, the vector processing device shown in FIG. 5 is composed of a high-speed RAM and can read and write independently, and 32 vector registers VR0 to VR0 capable of holding vector data of 256 elements.
VR31, 32 scalar registers SR0 to SR31 for storing scalar data, and vector registers VR0 to
A plurality of operations composed of a switch matrix logic selector 3 for selectively outputting the output data of the VR 31 and the scalar registers SR0 to SR31 to an operation unit by an instruction, a vector operation unit 4 and a scalar data buffer 5 for storing the operation result. Two sets of operation resources 6 and 7 configured by the units 6a to 6b and 7a to 7b, and operand paths 8a to 8h and 9a to 9h for inputting operand data supplied through the selector 3 to the operation resources 6 and 7, Operand path 10 for inputting the data of the scalar register specified by the operand to the post-processing operation unit, feedback path 20 for the post-processing operation result, and scalar data buffer 5 in each operation unit of operation resources 6 and 7 The data, the data in the scalar registers SR0 to SR31, and the post-processing operation result Selector 12 configured by switch matrix logic for selecting and outputting input data of the post-processing arithmetic unit from the feedback data, data of the scalar data buffer 5, data of the scalar registers SR0 to SR31, and feedback data of the post-processing arithmetic result are calculated. The post-processing arithmetic unit 13, the result paths 14 and 15 for outputting the calculation result of the vector arithmetic unit 4, and the post-processing arithmetic unit 1
The result path 16 that outputs the operation result of No. 3 and the operation results from each result path are vector registers VR0 to VR.
31 or a selector 17 configured by a switch matrix logic for selecting to write to the scalar registers SR0 to SR31.

The vector calculator 4 is an adder, a multiplier, or a multiplier / adder. In the case of an adder, a function of adding all input data {Σ [A (i) + B (i)]}
And the function of comparing {MaxA (i), MinA (i)}
In the case of a multiplier, it has a function of multiplying input data and adding all the results {ΣA (i) × B (i)},
Further, in the case of the multiplier / adder, it has a function that the result of one arithmetic unit becomes the input data of the other arithmetic unit.

Although not shown, the illustrated vector processing device is provided with a load pipeline for supplying operand data from the main memory to the vector register and a store pipeline for storing data from the vector register to the main memory.

In the vector processing device configured as described above, for example, when three or more macro operation instructions are consecutively given, the first two macro operation instructions are each given two.
Although it is issued to one computing resource 6 or 7, the remaining macro computing instructions operate so as to wait until the final result of one of the first two macro computing instructions is obtained.

That is, the data in the scalar data buffer 5 needs to be stored in the buffer 5 until the post-processing operation unit 13 operates and the processing is completed. , During this time, the operation by the next macro operation instruction cannot be performed,
The next macro operation instruction cannot be issued to this resource.

The processing pitch when the above-described vector processing device processes macro operation instructions successively will be described with reference to FIG.

Now, it is assumed that macro operation instructions are continuously issued to the vector processing device shown in FIG. In the example shown in FIG. 6, in this case, first, the arithmetic resource 6 executes the macro arithmetic instruction process 72, and the arithmetic resource 7 executes the macro arithmetic instruction process 73. The post-processing arithmetic unit 13 processes the macro operation instruction 72 at the time when the macro operation instruction processing 72 in the operation resource 6 is completed.
Start post-processing operation 69 for
Therefore, the next macro operation instruction cannot be issued until the post-processing operation 69 for the macro operation instruction processing 72 is completed.

Then, this macro operation instruction is issued to the operation resource 6 after the post-processing operation 69 is completed,
The processing 67 of the macro operation instruction is executed. For this reason,
A wasteful time 68 occurs in the computing resource 6.
The same applies to the calculation resource 7, and the macro calculation instruction cannot be issued to the calculation resource 7 until the post-processing calculation 70 for the processing 73 of the macro calculation instruction is completed, and the processing 71 is delayed, resulting in a dead time 74. Will occur.

Note that, in FIG. 6, the calculation time of the post-processing arithmetic unit is shown as about 1/2 of the calculation time of the vector arithmetic unit of the calculation resource, but generally, the calculation time of the post-processing arithmetic unit is The dead time is shorter than the calculation time of the vector calculators, and the dead time described above differs from the illustrated example depending on the calculation time of these calculators.

As described above, the vector processing device shown in FIG. 5 cannot increase the processing pitch when macro operation instructions are continuous, although the operation resources are increased to two. .

The fact that the processing pitch cannot be improved when the macro operation instructions are continuous is the same in the case of the prior art shown in FIG.

[0029]

As described above, in the prior art shown in FIGS. 4 and 5, the calculation resource that gives the result of the vector calculation to the post-processing arithmetic unit until the processing by the post-processing arithmetic unit is completed. In addition, there is a problem in that the next macro operation instruction cannot be issued, and in particular, when the macro operation instructions are continuous, the processing pitch is reduced.

The object of the present invention is to solve the above-mentioned problems of the prior art, and to configure with a small amount of hardware,
An object of the present invention is to provide a vector processing device capable of efficiently and continuously processing macro operation instructions.

[0031]

According to the present invention, the object is to provide a post-processing arithmetic unit between a calculation resource and a post-processing arithmetic unit in a vector processing device having a calculation resource and a post-processing arithmetic unit. This is achieved by providing a second scalar data buffer that holds the same number of data as the input data of the post-processing arithmetic unit in the scalar data buffer of the arithmetic resource.

[0032]

After the operation is completed, the operation resource immediately transfers the data in the scalar data buffer of the operation resource to the second buffer. The operation resource that transferred the data in the scalar data buffer of its own resource to the second buffer is
It becomes possible to execute the next macro operation instruction.

The post-processing operation unit processes the data transferred to the second buffer, and after the processing is completed, the data in the scalar data buffer of the next operation resource requiring the post-processing operation is transferred to the second buffer. Capture and repeat the arithmetic processing.

As described above, according to the present invention, it is possible to issue a vector instruction including a macro operation instruction at an early stage to an operation resource in which data is fetched in the second buffer.
As a result, continuous macro operation instructions can be processed at high speed.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a vector processing device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a schematic configuration of a control system,
FIG. 3 is a diagram for explaining the processing resources and the processing pitch of the post-processing operation unit when processing the macro operation instruction in FIG.
In FIGS. 1 and 2, 11 is a second scalar data buffer, 18 is a scalar data buffer, 19 and 29 are selectors, 21 is an instruction buffer, 23, 25, 27 and 28 are operation instruction buffers, and 30 is vector control. The other reference numerals are the same as those in FIGS. 4 and 5.

The embodiment of the present invention shown in FIG. 1 is constructed by providing a selector 19 and a second scalar data buffer 11 between the operation resource and the post-processing operation unit in the prior art described with reference to FIG. ing.

That is, the vector processing apparatus according to the embodiment of the present invention shown in FIG. 1 is composed of a high-speed RAM, can read and write independently, and can store vector data of 256 elements. Vector registers VR0 to VR31, 32 scalar registers SR0 to SR31 for storing scalar data, vector registers VR0 to VR31 and scalar register SR0
To a plurality of arithmetic units 6a to 6b each composed of a switch matrix logic selector 3 for selectively outputting the output data of SR31 to an arithmetic unit according to an instruction, a vector arithmetic unit 4 and a scalar data buffer 5 storing the arithmetic result thereof.
Two sets of computing resources 6, 7 composed of 7a-7b
And operand paths 8a to 8 for inputting the operand data supplied through the selector 3 to the operation resources 6 and 7.
h, 9a to 9h, the operand path 10 for inputting the data of the scalar register designated by the operand to the post-processing arithmetic unit, and the post-processing of the data of the scalar data buffers 5 and 18 in the arithmetic resources 6 and 7. The second scalar data buffer 11 by the buffers 11a to 11d for storing the input data of the arithmetic unit, the selector 19 for selecting one of the data from the arithmetic resources 6 and 7 and giving it to the second scalar data buffer 11, and A switch for selecting and outputting input data of the post-processing arithmetic unit from the feedback path 20 of the processing arithmetic result, the data in the second scalar data buffer 11, the data of the scalar registers SR0 to SR31, and the feedback data of the post-processing arithmetic result. The selector 12 composed of matrix logic and the second scalar data buffer 11 Over data, scalar register SR0~SR
31. The post-processing arithmetic unit 13 for calculating the data of 31 and the feedback data of the post-processing arithmetic result, the result paths 14 and 15 for outputting the arithmetic result of the vector arithmetic unit 4, and the result for outputting the arithmetic result of the post-processing arithmetic unit 13. Pass 16,
The calculation result from each result path is a vector register VR
0-VR31 or a scalar register SR0-SR31 and a selector 17 constituted by a switch matrix logic for selecting to write.

The above-mentioned vector calculator 4 is an adder,
It is a multiplier or a multiplier / adder, and in the case of an adder, a function of adding all input data {Σ [A (i) + B
(I)]} and the function to compare {MaxA (i), Min
A (i)} and, in the case of a multiplier, a function of multiplying input data and adding all the results {ΣA (i) × B
(I)}, and in the case of the multiplier / adder, it has a function that the result of one arithmetic unit becomes the input data of the other arithmetic unit.

Although not shown in the drawings, the vector processing apparatus according to the embodiment of the present invention includes a load pipeline for supplying operand data from the main memory to the vector register and a store pipeline for storing data from the vector register to the main memory. And are provided.

In the vector processing apparatus according to the embodiment of the present invention configured as described above, for example, when three or more macro operation instructions are continuously given, the first two macro operation instructions are respectively 2 Two computing resources 6, 7
Published in. Then, the intermediate result of the operation by the operation resources 6 and 7 is stored in the scalar data buffers 4 and 18.

The selector 19 has two calculation resources 6,
7 is selected, one of the scalar data buffers 5 and 18 is selected as input data to the post-processing calculator 13, and the selected data is stored in the second scalar data buffer 11.

The post-processing arithmetic unit 13 outputs the data in the second scalar data buffer 11 and the scalar registers SR0 to SR0.
The SR31 data is used as input data for the calculation, and the final result is written to the register designated by the operand via the result path 16 and the selector 17.

In the above operation, the scalar data buffer 5,
The following macro operation instruction is issued to the operation resource in which the data of 18 is stored in the second scalar data buffer 11. As a result, the calculation resource with which the internal scalar data buffer becomes empty can immediately start executing the next macro calculation instruction without waiting for the end of the post-processing calculation, thus improving the processing efficiency of the entire processing device. It is possible to improve.

FIG. 2 shows a circuit configuration of an example of the control logic for controlling the arithmetic operation described above.

As shown in FIG. 2, the vector controller 30
Is a vector instruction buffer 21 and calculation resources 6 and 7
Instruction buffers 23 and 25 for
Instruction buffers 27 and 28 for the post-processing calculator 13 that calculates the intermediate result of 7 and these instruction buffers 27 and 2
The switch matrix logic selector 29 for selectively outputting the command from 8 to the post-processing arithmetic unit 13 is configured.

That is, according to one embodiment of the present invention, the number of instruction buffers for each operation resource and the number of instruction buffers for the post-processing operation unit are the same as the number of operation resources processed by the post-processing operation unit, so that each operation resource is Also, it is possible to enable the parallel operation of the post-processing arithmetic unit.

The processing pitch when the above-described vector processing device processes macro operation instructions successively will be described with reference to FIG.

Now, it is assumed that macro operation instructions are continuously issued to the vector processing device shown in FIG. In the example shown in FIG. 3, in this case, first, the arithmetic resource 6 executes the macro arithmetic instruction process 34, and the arithmetic resource 7 executes the macro arithmetic instruction process 31. When the processing 34 of the macro operation instruction is completed in the operation resource 6, the post-processing operation unit 13 determines that the processing 34 of the macro operation instruction is completed.
The post-processing operation 32 for is started.

At this time, since the intermediate result by the processing 34 of the macro operation instruction obtained by the operation resource 6 is stored in the second scalar data buffer 11 shown in FIG.
The computing resource 6 can immediately execute the next macro computing instruction processing 33 after the macro computing instruction processing 34 is completed.

As described above, according to the embodiment of the present invention, it is possible to prevent wasteful time and prevent the processing pitch from decreasing.

Note that, in FIG. 3, the calculation time of the post-processing arithmetic unit is shown as about 1/2 of the calculation time of the vector arithmetic unit of the calculation resource, but in general, the calculation time of the post-processing arithmetic unit is shown. Is shorter than the operation time of the vector operation unit, and depending on these operation times, a small dead time may occur in the processing of either the operation resource or the post-processing operation unit.

Although the above-described embodiment of the present invention has been described assuming that two sets of calculation resources and one set of post-processing calculators are provided, the present invention includes more sets of calculation resources and It can also be applied to a vector processing device having a smaller number of post-processing arithmetic units. In this case, the number and the second scalar data buffer may be provided corresponding to the post-processing arithmetic unit.

Furthermore, the present invention can be applied to the prior art described with reference to FIG. 4, that is, to the vector processing device in which the calculation resource and the post-processing calculator are each provided in one set or in the same number. Also in this case, the calculation resource can start the processing of the next macro calculation instruction without waiting for the end of the post-processing calculation.

According to the above-described embodiment of the present invention, the process of obtaining the intermediate result of the macro operation instruction by the vector operation unit corresponding to each element and the final result by the post-processing operation unit using the intermediate result as input data. Since it is separated from the processing, even when the number of computing resources is increased, the physical quantity of the post-processing computing unit is minimized, and the computing resources are effective even when macro computing instructions are issued consecutively. Can be used
Thereby, the processing speed can be increased.

[0056]

As described above, according to the present invention, in the vector processing device having the arithmetic resource and the post-processing arithmetic unit, the second scalar data buffer is provided between the arithmetic resource and the post-processing arithmetic unit. , When the intermediate result of the arithmetic resource is processed by the post-processing arithmetic unit like the macro arithmetic instruction, the data from the arithmetic resource is fetched into the second scalar data buffer, and the data is stored in the second scalar data buffer. The processing resource that has been taken in can start the processing of the vector instruction including the next macro processing instruction at an early stage, speeding up one macro processing instruction with a small amount of material, and an instruction when the macro processing instructions are continuous. The processing pitch can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a control system.

FIG. 3 is a diagram for explaining processing resources and a processing pitch of a post-processing operation unit when processing a macro operation instruction in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional technique including a computing resource and a post-processing computing unit.

FIG. 5 is a block diagram showing a configuration of a conventional technique including a plurality of sets of calculation resources and a post-processing calculator.

6 is a diagram for explaining processing resources and a processing pitch of a post-processing operation unit when processing a macro operation instruction in FIG.

[Explanation of symbols]

 3, 12, 17, 19, 19, 29 selector 4 vector calculator 5, 18 scalar data buffer 6, 7 calculation resource 13 post-processing calculator VR0-VR31 vector register SR0-SR31 scalar register 11 second scalar data buffer 19, 29 Selector 21 instruction buffer 23, 25, 27, 28 operation instruction buffer 30 vector control unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masamori Kashiwayama, No. 1 Horiyamashita, Horiyamashita, Hadano-city, Kanagawa Prefecture, General Computer Division, Hitachi, Ltd. (72) Yasuhiro Maeda, No. 1 Horiyamashita, Hadano, Kanagawa Prefecture Hitachi Computer Data Engineering Co., Ltd.

Claims (3)

[Claims] 1. A plurality of vector registers for holding vector data composed of a plurality of vector elements, a vector calculator for processing a plurality of vector elements of the vector data held in the vector register in parallel, and a scalar data buffer. In a vector processing device having an arithmetic resource and a post-processing arithmetic unit that uses the data of the scalar data buffer as input data, a second scalar data buffer that holds the data of the scalar data buffer as input data of the post-processing arithmetic unit A vector processing device comprising: 2. A plurality of vector registers for holding vector data consisting of a plurality of vector elements, a vector calculator for processing a plurality of vector elements of the vector data held in the vector register in parallel, and a scalar data buffer. In a vector processing device having a plurality of arithmetic resources and a post-processing arithmetic unit that receives the data of the scalar data buffer as input data and has a number smaller than the number of the arithmetic resources, the data of the scalar data buffer is post-processing arithmetic unit. Second to hold as input data of
Vector processing device, characterized in that the same number of scalar data buffers are provided as in the post-processing arithmetic unit. 3. The vector processing device according to claim 1, wherein the arithmetic resource can start arithmetic processing for the next vector element after passing data to the second scalar data buffer. .