JPH06149719A - Interface device - Google Patents

Abstract

PURPOSE:To perform plural processes in parallel by lightening the process load on a central control part. CONSTITUTION:A switching device 800 in a computer interface part 7 operates with the instruction a CPU 1003 arranged in a core part 10 and switches an output destination to a side OUT1 when a signal line 801 has logic high or to a side 0UT2 when the line has logic low. When the switching device 800 is set on the side 0UT2, an input signal from a terminal is inputted to a formatter part 8 directly not through a CPU bus 1054. Consequently, the CPU bus 1054 is not used for the input from the terminal device, so it is usable to transfer data with other option boards.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device comprising a main board and a plurality of option boards, to which an external device for inputting commands and the like is connected.

[0002]

2. Description of the Related Art Conventionally, in an external control device for a digital copying machine, which comprises a main board and a plurality of option boards, an interface device that controls the interface with a terminal device receives a command or data input from the terminal device. It transmits to the above CPU, and the CPU analyzes these commands and the like. Then, the CPU determines the board to receive the command or data, and further communicates with the target option board by the CPU, so that the data between the terminal device such as a computer and the plurality of option boards is transferred. We are communicating.

[0003]

However, in the above-mentioned conventional digital copying machine, when the terminal device exchanges data with the interface device and an option board other than the main board, the CPU on the main board once receives a command or a command. Since it is necessary to send data and it is necessary to communicate with the target option board after command analysis, a large processing load is applied to the CPU on the main board. Therefore, there is a problem in that a processing delay occurs in the processing system on the main board, and this processing delay must be avoided by using a faster CPU.

Further, in the conventional digital copying machine, the CPU bus on the main board is occupied for the communication processing between the interface device and each option board. Therefore, as the number of types of option boards increases, the CPU bus waits empty. It takes a long time, which is a big obstacle when performing multiple processes at the same time. An object of the present invention is to provide an interface device that switches the output destination of a command or data according to an input command and reduces the processing load of the control unit on the main board.

[0005]

In order to achieve the above object, the present invention provides an external control section comprising a main board for controlling the main control of the apparatus and a plurality of option boards, and an external control section connected to the external control section. In an interface device including a device, a unit for analyzing a command or data input from the external device, and outputs the command or data by switching to the main board or the plurality of option boards according to the result of the analysis. Switching means, and the switching means is included in the plurality of option boards.

[0006]

With the above structure, the processing load of the central control unit on the main board is reduced, and the plurality of processes can be performed in parallel.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing the configuration of an image forming system according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a reader unit that functions as an image input device that converts a document into image data, and 2 has a plurality of types of recording paper cassettes. The printer 3, which is an image output device for outputting, is an external device electrically connected to the reader unit 1 and has various functions.

The external device 3 includes a fax unit 4, a file unit 5, an external storage device 6 connected to the file unit 5, a computer interface unit 7 for connecting to the computer 15, and a visible image of information from the computer 15. A formatter unit 8 for storing the information, an image memory unit 9 for temporarily storing the information sent from the reader unit 1 and the information sent from the computer 15, and
A core unit 10 that controls each of the above functions is provided.

The functions of the above-mentioned parts will be described in detail below. <Description of Reader Unit 1> FIG. 2 is a cross-sectional configuration diagram of the reader unit 1 and the printer unit 2. In the figure, the originals (not shown) stacked on the original feeding device 101 are sequentially conveyed one by one onto the original table glass surface 102. When the original is conveyed, the lamp 103 of the scanner unit is turned on and the scanner unit 104 moves to illuminate the original. Then, the reflected light from the document is reflected by the mirrors 105, 106, 10
The light passes through the lens 108 via 7 and then enters the CCD image sensor unit 109 (hereinafter referred to as CCD).

FIG. 3 is a circuit block diagram showing a signal processing configuration of the reader unit 1. In the figure, the image information input to the CCD 109 is converted into an electric signal by photoelectric conversion there. The color information from this CCD 109 is
A / D by the amplifier 110R, 110G, 110B of the next stage
It is amplified according to the input signal level of the converter 111.
The output signal from the A / D converter 111 is input to the shading circuit 112, where the lamp 103
The uneven light distribution and the uneven sensitivity of the CCD 109 are corrected. Then, the signal from the shading circuit 112 is input to the Y signal generation / color detection circuit 113 and the external I / F switching circuit 119.

The Y signal generation / color detection circuit 113 performs a calculation on the signal from the shading circuit 112 according to the following equation (1) to obtain a Y signal. Y = 0.3R + 0.6G + 0.1B (1) The color detection circuit of the Y signal generation / color detection circuit 113 further separates the R, G, and B signals into seven colors and outputs signals for each color. . The output signal from the Y signal generation / color detection circuit 113 is input to the scaling / repeat circuit 114 to scale in the sub-scanning direction according to the scanning speed of the scanner unit 104, and the scaling circuit / repeat circuit. 1
Magnification change in the main scanning direction is performed by 14. Note that it is possible to output a plurality of identical images by the scaling / repeat circuit 114.

The contour / edge emphasis circuit 115 emphasizes high frequency components of the signal from the scaling / repeat circuit 114 to obtain edge emphasis and contour information. This contour
The signal from the edge enhancement circuit 115 is input to the marker area determination / contour generation circuit 116 and the patterning / thickening / masking / trimming circuit 117. A marker area determination / contour generation circuit 116 reads a portion of a document written with a marker pen of a designated color to generate contour information of the marker, and also performs patterning / thickening / masking / marking.
The trimming circuit 117 performs thickening, masking, and trimming based on this contour information, and performs patterning by the color detection signal from the Y signal generation / color detection circuit 113.

An output signal from the patterning / thickening / masking / trimming circuit 117 is input to a laser driver circuit 118, and various processed signals are converted into signals for driving a laser. Laser driver circuit 118
Output signal is input to the printer unit 2, where an image is formed as a visible image. Next, the external I / F switching circuit 119 that controls the interface with the external device 3 will be described.

When outputting image information from the reader unit 1 to the external device 3, the external I / F switching circuit 119 outputs the image information from the patterning / thickening / masking / trimming circuit 117 to the connector 120. When the image information from the external device 3 is input to the reader unit 1, the external I / F switching circuit 119 inputs the image information from the connector 120 to the Y signal generation / color detection circuit 113.

The above image processing is carried out in accordance with an instruction from the CPU 122, and the area generation circuit 121 causes the CPU 12 to operate.
Various timing signals necessary for the above image processing are generated according to the value set by 2. Furthermore, the CPU 12
2 communicates with the external device 3 by using the communication function built in the SUB / CPU 123. The SUB / CPU 123 controls the operation unit 124, and at the same time, the SUB / CPU 123
Communication with the external device 3 is performed using the communication function built in the. <Description of Printer Unit 2> Next, the configuration and operation of the printer unit 2 will be described with reference to FIG.

The signal input to the printer unit 2 is converted into an optical signal by the exposure control unit 201, and the photoconductor 202 is illuminated according to the image signal. This irradiation light causes the photoconductor 202
The latent image formed above is developed by the developing device 203. The transfer sheet is conveyed from the transfer sheet stacking section 204 (or 205) at the same timing as the above-mentioned development, and the developed image is transferred onto the transfer sheet at the transfer section 206. The transferred image is fixed on the transfer paper by the fixing unit 207, and then discharged from the paper output unit 208 to the outside of the apparatus. The transfer paper output from the paper output unit 208 is discharged to each bin when the sort function of the sorter 220 is working, or to the highest bin of the sorter when the sort function is not working. To be done.

Here, a method of outputting sequentially read images on both sides of a single output sheet will be described. The output paper sheet fixed by the fixing unit 207 is once conveyed to the paper discharge unit 208, and then the conveyance direction of the paper sheet is reversed, and the re-transferred transfer paper sheet stacking unit 2 is conveyed via the conveyance direction switching member 209.
It is transported to 10. And when the next manuscript is prepared,
The original image is read in the same manner as in the above process, but since the transfer paper is fed from the re-transferred transfer paper stacking section 210, two original images are eventually printed on the front and back sides of the same output paper. Can be output. <Description of External Device 3> The external device 3 is connected to the reader unit 1 by a cable, and the core unit 10 in the external device 3 controls signals and functions. As described above, the external device 3 includes the fax unit 4 that performs fax transmission / reception, the file unit 5 that converts various document information into electric signals and stores the signals, and the formatter unit 8 that expands the code information from the computer 15 into image information. A computer interface section 7 for interfacing with the computer 15, an image memory section 9 for accumulating information from the reader section 1 or temporarily accumulating information sent from the computer 15, and each of the above. It is composed of a core unit 10 that controls functions.

Therefore, the configuration and operation of the core portion 10 in the external device 3 will be described with reference to the block diagram shown in FIG. In the following description, signal names and data names are bracketed to distinguish them from signal lines or data lines. <Description of Core Unit 10> FIG. 4 is a block diagram showing a detailed configuration of the core unit 10. In the figure, the connector 1001 of the core unit 10 is connected to the connector 120 of the reader unit 1 by a cable. Four types of signals appear on the connector 1001, and among them, the signal (1057) is 8 bits.
It is a multi-valued video signal. Also, the signal (1055) is
It is a control signal for controlling the video signal, and is a signal (105
1) is a signal for communicating with the CPU 122 in the reader unit 1.

The signal (1052) is the SU in the reader unit 1.
B · Communicates with the CPU 123, the signal (1051) and the signal (1052) are subjected to communication protocol processing by the communication IC 1002, and the CPU 10 is transmitted via the CPU bus 1053.
The communication information is transmitted to 03. Also, the signal (1057)
Is a bidirectional video signal line, and the core unit 10 receives information from the reader unit 1 and outputs information from the core unit 10 to the reader unit 1.

The above signal (1057) is sent to the buffer 101.
0, where it is separated into bidirectional signals and unidirectional signals (signals (1058), (1070)). Of these signals, the signal (1058) is an 8-bit multivalued video signal from the reader unit 1 and is input to the LUT 1011 in the next stage. The LUT 1011 converts the image information from the reader unit 1 into a desired value by referring to the look-up table. Then, the output signal (1059) from the LUT 1011 is input to the binarization circuit 1012 or the selector 1013.

The binarization circuit 1012 has a multilevel signal (10
59) simple binarization function for binarizing 59) with a fixed slice level, a binarization function with a variable slice level in which the slice level fluctuates from the values of pixels around the pixel of interest, and a binary value with an error diffusion method. It has a conversion function. Binarized information is 00H (H is 16 when its value is logical “0”).
(Indicated by a decimal number) and is converted into a multivalued signal of FFH when it is a logic "1", and the converted signal is input to the selector 1013 at the next stage.

The selector 1013 selects the signal from the LUT 1011 or the output signal of the binarization circuit 1012, and the output signal (1060) from this selector 1013.
Is input to the selector 1014. Selector 1014
Are output video signals from the fax unit 4, the file unit 5, the computer interface unit 7, the formatter unit 8, and the image memory unit 9, respectively.
A signal (1064) which is a signal input to the core unit 10 via 5, 1006, 1007, 1008, 1009;
The output signal (1060) from the selector 1013 is set to C
It is selected by the instruction of the PU 1003.

Output signal of selector 1014 (1061)
Is input to the rotation circuit 1015 or the selector 1016. The rotation circuit 1015 adds +9 to the input image signal.
It has the function of rotating 0 degrees, -90 degrees, and +180 degrees.
Further, in the rotating circuit 1015, the information output from the reader unit 1 is converted into a binary signal by the binarizing circuit 1012, and then stored as information from the reader unit 1, and the CPU 10
In response to an instruction from 03, the rotation circuit 1015 rotates and reads this stored information.

Further, the selector 1016 is the rotation circuit 10
15 output signal (1062) and the rotation circuit 1015.
Select any of the input signals (1061) to the fax unit 4 as a signal (1063) and connect it to the fax unit 4 connector 1
005, a connector 1006 with the file unit 5, a connector 1007 with the computer interface unit 7, a connector 1008 with the formatter unit 8, a connector 1009 with the image memory unit 9, and a selector 1017.

The signal line 1063 transfers image information from the core unit 10 to the fax unit 4, the file unit 5, the computer interface unit 7, the formatter unit 8 and the image memory unit 9, and is therefore a synchronous 8-bit unidirectional video. It's a bus. The signal line 1064 is a synchronous 8-bit unidirectional video bus for transferring image information from the fax unit 4, file unit 5, computer interface unit 7, formatter unit 8 and image memory unit 9. The video control circuit 1004 controls the signal line 1063 and the synchronous bus of the signal line 1064, and specifically, this control is performed by the output signal (1056) from the video control circuit 1004.

In addition, a signal line 1054 is connected to each of the connectors 1005 to 1009. This signal line 1054 is a bidirectional 16-bit C
It is a PU bus and exchanges data commands asynchronously. Also, the fax section 4, the file section 5,
For transferring information between the computer interface unit 7, the formatter unit 8, the image memory unit 9 and the core unit 10, the two signal lines 1063, which are video buses, are also used.
It is possible by 1064 and CPU bus 1054.

The signal (1064) from the fax unit 4, file unit 5, computer interface unit 7, formatter unit 8 and image memory unit 9 is sent to the selector 101.
4 and the selector 1017. Also, selector 1
014 is a signal (106
4) is input to the rotation circuit 1015 of the next stage. Selector 1
017 shows the signal (1063) and the signal (1064) as C
The output signal (1065) of the selector 1017 selected by the instruction of the PU 1003 is the pattern matching 1018.
Is input to the selector 1019. The pattern matching 1018 performs pattern matching between the input signal (1065) and a predetermined pattern,
When both patterns match, a predetermined multilevel signal is output to the signal line 1066. On the other hand, if the two patterns do not match in the pattern matching, the input signal (1065) is output as the signal (1066).

The selector 1019 selects the signal (1065) and the signal (1066) according to the instruction of the CPU 1003, and the output signal (1067) from the selector 1019 is
It is input to the LUT 1020 in the next stage. This LUT102
When the image information is output to the printer unit 2, 0 converts the input signal (1067) according to the characteristics of the printer. The selector 1021 outputs the output signal (106
8) and the signal (1065) are selected by the instruction of the CPU 1003. Then, the output signal of the selector 1021 is input to the enlarging circuit 1022 at the next stage. Enlargement circuit 1
In 022, the enlargement magnification can be set independently in the X and Y directions by an instruction from the CPU 1003, and the enlargement method is a linear interpolation method of the first order. The output signal (1070) of the expansion circuit 1022 is
It is input to the buffer 1010.

The signal (10
70) is a bidirectional signal (1
057), and is sent to the printer unit 2 via the connector 1001 and printed out. Next, the core portion 10
And the flow of signals between the respective parts will be described. [Explanation of operation of core unit 10 based on information of fax unit 4]
First, the case of outputting information to the fax unit 4 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 to issue a document scan command. In the reader unit 1, the scanner unit 104 scans the document according to this command, and the image information is output to the connector 120. The reader unit 1 and the external device 3 are connected by a cable, and information from the reader unit 1 is transferred to the connector 1001 of the core unit 10.
Entered in. Further, the image information input to the connector 1001 is input to the buffer 1010 through the multi-level 8-bit signal line 1057. Then, according to an instruction from the CPU 1003, the buffer circuit 1010 inputs the multivalued 8-bit signal (1057) that is a bidirectional signal as a one-way signal to the LUT 1011 via the signal line 1058.

The LUT 1011 converts the image information from the reader unit 1 into a desired value using a look-up table. This conversion can remove the background of the document, for example. Then, the output signal (1059) of the LUT 1011 is input to the binarization circuit 1012 at the next stage. As described above, the binarization circuit 1012 converts the 8-bit multi-valued signal (1059) into a binarized signal, and when the binarized signal is logical 0, it is 00H, and when it is logical 1, it is FF.
It is converted into two multilevel signals of H. The output signal from the binarization circuit 1012 is input to the rotation circuit 1015 or the selector 1016 via the selector 1013 and the selector 1014.

Further, the output signal (10
62) is also input to the selector 1016, and the selector 101
6 selects either the signal (1061) or the signal (1062). This signal is selected by the CPU 1003 by the C
It is determined by communicating with the fax unit 4 via the PU bus 1054. Then, the output signal (1063) from the selector 1016 is sent to the fax unit 4 via the connector 1005.

Next, the case of receiving information from the fax unit 4 will be described. The image information from the fax unit 4 is transmitted to the signal line 1064 via the connector 1005. Signal on signal line 1064 (1064)
Is input to the selectors 1014 and 1017. Then, when the image at the time of fax reception is rotated and output to the printer unit 2 according to the instruction of the CPU 1003, the rotation circuit 1015 rotates the signal (1064) input to the selector 1014. This rotating circuit 101
The output signal (1062) from the selector 5 is the selector 1016,
Pattern matching 1018 via the selector 1017
Entered in.

On the other hand, when the image at the time of fax reception is output to the printer 2 as it is according to the instruction of the CPU 1003, the signal (1064) input to the selector 1017 is input to the pattern matching 1018. The pattern matching 1018 has a function of smoothing rattling of an image when received by fax. The pattern-matched signal is sent to the LUT 102 via the selector 1019.
Input to 0. The LUT 1020 outputs the fax-received image to the printer unit 2 at a desired density.
The table can be changed by the CPU 1003. The output signal (1068) of the LUT 1020 is input to the expansion circuit 1022 via the selector 1021.

The expansion circuit 1022 has two values (00H,
FFH) 8-bit multivalues are enlarged by a linear interpolation method of the first order. An 8-bit multi-valued signal having many values from the expansion circuit 1022 is sent to the reader unit 1 via the buffer 1010 and the connector 1001. Then, the reader unit 1 inputs this signal to the external I / F switching circuit 119 via the connector 120.

The external I / F switching circuit 119 outputs the signal from the fax unit 4 to the Y signal generation / color detection circuit 113, and the output signal from the Y signal generation / color detection circuit 113 is processed as described above. After that, the image is output to the printer unit 2 and an image is formed on the output paper. [Description of Operation of Core Unit 10 Based on Information of File Unit 5] Next, a case of outputting information of the file unit 5 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 to issue a document scan command. In the reader unit 1, the scanner unit 104 scans the document according to this command, and outputs the obtained image information to the connector 120. Reader unit 1
The external device 3 and the external device 3 are connected by a cable, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. Then, the image information input to the connector 1001 is unidirectional signal (10
58). A signal that is a multilevel 8-bit signal (105
8) is converted into a desired signal by the LUT 1011 and the output signal (1059) from the LUT 1011 is the selector 1013, the selector 1014, and the selector 101.
6, and the connector 1006 via the signal line 1063.
Entered in. That is, without using the functions of the binarization circuit 1012 and the rotation circuit 1015, the 8-bit multivalued signal is transferred to the file unit 5 as it is.

On the other hand, the CPU bus 105 of the CPU 1003
When filing the binarized signal by communicating with the file unit 5 via the binarizing unit 4, the binarizing circuit 1012
The function of the rotating circuit 1015 is used. In addition, these 2
Since the binarization process and the rotation process are the same as those in the case of the above-described fax, the description thereof will be omitted here. Next, a case of receiving information from the file unit 5 will be described.

The image information from the file section 5 is sent as a signal (1064) to the selector 1 via the connector 1006.
014 or the selector 1017. 8 bi
In the case of multi-valued filing, the image signal is selected by the selector 1
017, or in the case of binary filing, can be input to the selector 1014 (or 1017). The processing for binary filing is as follows.
Since the processing is similar to that of the above fax, the description thereof is omitted.

In the case of multi-value filing, the selector 10
The output signal (1065) from the selector 17 is supplied to the selector 1019.
To the LUT 1020 via. This LUT102
At 0, the CPU 100 is adjusted according to the desired print density.
A lookup table is created according to the instruction of 3. Then, the output signal (1068) from the LUT 1020 is input to the expansion circuit 1022 via the selector 1021.

The 8-bit multilevel signal (1070) expanded by the expansion circuit 1022 at a desired expansion ratio is sent to the reader unit 1 via the buffer 1010 and the connector 1001. The information of the file section sent to the reader section 1 is
Similar to the above-mentioned fax, it is output to the printer unit 2 and an image is formed on the output paper. [Description of Operation of Core Unit 10 Based on Information of Computer Interface Unit 7] The computer interface unit 7 interfaces with the computer 15 connected to the external device 3. This computer interface unit 7 is, for example, SCSI, RS-232.
It is equipped with a plurality of interfaces for communicating with devices having a C or Centronics system. And
Information from each of the above three types of interfaces is sent to the CPU 100 via the connector 1007 and the data bus 1054.
Sent to 3. The CPU 1003 performs various controls based on the content of the sent information. [Description of Operation of Core Unit 10 Based on Information from Formatter Unit 8] The formatter unit 8 has a function of expanding command data such as a document file sent from the computer interface unit 7 into image data. When the CPU 1003 determines that the data sent from the computer interface unit 7 via the data bus 1054 is the data related to the formatter unit 8, the CPU 1003 transfers the data to the formatter unit 8 via the connector 1008. Then, the formatter unit 8
Develops in the memory from the transferred data as a meaningful image such as characters and figures.

Next, a procedure for receiving information from the formatter unit 8 and forming an image on an output sheet will be described. The image information from the formatter unit 8 is output to the connector 10
08 through signal line 1064 to two values (00
H, FFH) and is transmitted as a multilevel signal. The signal (1064) on the signal line 1064 is sent to the selector 10
14, input to the selector 1017, and according to an instruction from the CPU 1003, the selector 1014 and the selector 1017.
To control. Since the subsequent operation is the same as that of the above-mentioned fax, the description thereof is omitted. [Description of Operation of Core Unit 10 Based on Information in Image Memory Unit 9] Next, a case where information is output to the image memory unit 9 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and issues a document scan command. In the reader unit 1, the scanner unit 104 scans the document according to this command and outputs the obtained image information to the connector 120. The reader unit 1 and the external device 3 are connected by a cable, and information from the reader unit 1 is input to the connector 1001 of the core unit 10.

The image information input to the connector 1001 is the multilevel 8-bit signal line 1057 and the buffer 10.
Sent to LUT 1011 via 10. And LU
The output signal (1059) from T1011 is the selector 1
Multivalued image information is transferred to the image memory unit 9 via 013, 1014, 1016, the signal line 1063, and the connector 1009. The image information stored in the image memory unit 9 is sent to the CPU 1003 via the CPU bus 1054 connected to the connector 1009.

The CPU 1003 is the computer described above.
The data sent from the image memory unit 9 is transferred to the interface unit 7. The computer interface section 7 includes three types of interfaces (SC
Data is transferred to the computer 15 through a desired interface among SI, RS-232C, and Centronics).

Next, a case where information is received from the image memory unit 9 will be described. First, an image signal is sent from the computer 15 to the core unit 10 via the computer interface unit 7. CPU 1 of core unit 10
003 is the computer interface unit 7 to C
When it is determined that the data sent via the PU bus 1054 is data relating to the image memory unit 9, the data is transferred to the image memory unit 9 via the connector 1009.

The image memory unit 9 has a connector 1009.
8 bit multi-level signal (1064) via selector 1
014, and transmits to the selector 1017. Then, the output signal from the selector 1014 or the selector 1017 is output to the printer unit 2 in accordance with an instruction from the CPU 1003, similarly to the above-mentioned fax, and an image is formed on an output sheet. <Description of Fax Unit 4> FIG. 5 is a block diagram showing a detailed configuration of the fax unit 4.

The fax unit 4 is connected to the core unit 10 by the connector 400 and exchanges various signals. When the binary information from the core unit 10 is stored in any of the memories A405 to D408, the connector 4
The signal (453) from 00 is the memory controller 404.
Under the control of this memory controller, it is stored in any one of the memory A 405, the memory B 406, the memory C 407, and the memory D 408, or those in which two sets of these memories are cascade-connected.

The memory controller 404 has the following five functions. That is, (1) CPU
In accordance with the instruction of 412, the memory A405, the memory B40
6, memory C407, memory D408 and CPU bus 46
Mode for exchanging data via 2; (2) CODEC 411 and CODE having encoding / decoding function
A mode for exchanging data via the C bus 463, (3) memory A405, memory B406, memory C
407 and the contents of the memory D 408 are transferred from the scaling circuit 403 to the bus 454 under the control of the DMA controller 402.
Mode in which data is exchanged via the memory, (4) a mode in which binary video input data (454) is stored in any of the memories A405 to D408 under the control of the timing generation circuit 409, and (5) Memory A40
In this mode, the memory content is read from any one of the memory 5 to the memory D 408 and is output to the signal line 452.

The memory A405, the memory B406, the memory C407, and the memory D408 are 2 Mbytes each.
And has a capacity of 400 dpi and stores an image corresponding to A4 size at a resolution of 400 dpi. Also, the timing generation circuit 409
Are connected to the connector 400 via a signal line 459, and control signals (HSYNC, H
EN, VSYNC, VEN)
Generate signals to accomplish one function.

That is, the first function is to store the image signal from the core unit 10 in any one of the memories A405 to D408, or two of them, and the other is the memory A405. ~ Memory D408
It is a function of reading an image signal from any one of them and transmitting it to the signal line 452. The dual port memory 410 is connected to the C of the core unit 10 via the signal line 461.
It is connected to the PU 1003 and also to the CPU 412 of the fax unit 4 via a signal line 462. These CP
Each of the U's exchanges commands via the dual port memory 410.

The SCSI controller 413 interfaces with the hard disk 11 connected to the fax section 4 shown in FIG. 1, and stores data at the time of fax transmission and fax reception in the hard disk 11. The CODEC 411 reads the image information stored in any of the memories A405 to D408, encodes the image information by a desired method of the MH, MR, and MMR systems, and then encodes it into one of the memories A405 to D408. Store as information. Also, memory A
405 to memory D 408, the encoded information stored in the memory A 405 to the memory D 408 is read, and the decoded information is stored in one of the memories A 405 to D 408. Memorize as.

The MODEM 414 is a CODEC 411,
Alternatively, a function of modulating the coded information from the hard disk connected to the SCSI controller 413 for transmission on the telephone line, and demodulation of the information sent from the NCU 415 to convert the coded information into CODEC41
1, or the encoded information is transferred to the hard disk 11 connected to the SCSI controller 413. The NCU 415 exchanges information with an exchange installed in a telephone station or the like connected to a telephone line by a predetermined procedure.

Here, a transmission example of fax transmission will be described. The binarized image signal from the reader unit 1 is the connector 400.
More input, and reaches the memory controller 404 through the signal line 453. The signal on the signal line 453 (4
53) is the memory A by the memory controller 404.
405 is stored. The timing signal for this storage is generated by the timing generation circuit 409 by the timing signal (459) from the reader unit 1.

The CPU 412 is the memory controller 40.
4 memory A 405 and memory B 406
Connect to the bus line 463 of C411. CODEC4
11 reads the image information from the memory A405,
The coded information coded by the MR method is stored in the memory B4.
Write to 06. Then, when the CODEC 411 encodes the A4 size image information, the CPU 412 connects the memory B 406 of the memory controller 404 to the CPU bus 462.

The CPU 412 sequentially reads the coded information from the memory B 406 and outputs it to the MODEM 414.
Transfer to. The MODEM 414 modulates the encoded information and transmits it as fax information on the telephone line via the NCU. Next, a reception example in fax reception will be described. The information sent from the telephone line is input to the NCU 415, and the fax unit 4 and the telephone line are connected by a predetermined procedure in the NCU 415. And NCU41
The information from 5 enters MODEM 414 where it is demodulated. Further, the CPU 412 stores the information from the MODEM 414 in the memory C407 via the CPU bus 462.

When the information of one screen is stored in the memory C407, the CPU 412 controls the memory controller 404 to cause the data line 45 of the memory C407.
7 to line 463 of CODEC 411. CO
The DEC 411 sequentially reads the encoded information of the memory C407 and decodes it, that is, stores it in the memory D408 as image information.

The CPU 412 is a dual port memory 4
The CPU 1003 communicates with the CPU 1003 of the core unit 10 via the CPU 10, and makes settings for printing out an image from the memory D 408 through the core unit 10 to the printer unit 2. When this setting is completed, the CPU 412 activates the timing generation circuit 409 and outputs a predetermined timing signal from the signal line 460 to the memory controller 404.

The memory controller 404 reads the image information from the memory D408 in synchronization with the signal from the timing generation circuit 409, transmits it to the signal line 452, and outputs it to the connector 400. The operation up to the output from the connector 400 to the printer unit 2 has been described with respect to the operation of the core unit, so the description thereof is omitted here. <Description of File Unit 5> FIG. 6 is a block diagram showing a detailed configuration of the file unit 5. Therefore, the configuration and operation will be described with reference to FIG.

The file unit 5 is connected to the core unit 10 via the connector 500 and exchanges various signals. The multi-valued input signal (551) is input to the compression circuit 503, where it is converted from multi-valued image information into compressed information and then output to the memory controller 510. The output signal (552) of the compression circuit 503 is under the control of the memory controller 510, the memory A 506, the memory B 507, and the memory C 50.
8 or the memory D509, or those in which two sets of these memories are cascade-connected.

The memory controller 510 sets the memory A50 as a function mode according to the instruction of (1) CPU 516.
6, memory B507, memory C508, memory D509
And a mode for exchanging data via the CPU bus 560, (2) CODEC 51 for encoding / decoding
Mode for exchanging data via the CODEC bus 570 of (7) memory A506, memory B50
7, the contents of memory C508 and memory D509 are DMA
A mode in which data is exchanged from the scaling circuit 511 via the bus 562 under the control of the controller 518, and (4) a signal (553) is stored in any one of the memory A506 to the memory D509 under the control of the timing generation circuit 514. Mode, and (5) Memory A506 ~
Read the memory contents from any of the memories D509,
The five functions of the mode of outputting it to the signal line 559 are realized.

The memory A 506, the memory B 507, the memory C 508, and the memory D 509 each have 2 Mbytes.
And has a capacity of 400 dpi and stores an image corresponding to A4 size at a resolution of 400 dpi. In addition, the timing generation circuit 514
Are connected to the connector 500 by a signal line 553, and control signals (HSYNC, HEN,
VSYNC, VEN) to generate signals to accomplish the following two functions:

That is, one of them is a function of storing the information from the core unit 10 in any one of the memories A506 to D509, or those two memories, and the other functions are memory A506 to memory A506. This is a function of reading image information from any one of D509 and transmitting it to the signal line 556. Dual port memory 5
15 is the CPU of the core unit 10 via the signal line 554.
1003, and also connected to the CPU 516 of the file unit 5 via a signal line 560. Each of these CPUs exchanges commands via the dual port memory 515.

The SCSI controller 519 interfaces with the external storage device 6 connected to the file unit 5 in FIG. The external storage device 6 is, specifically,
It is composed of a magneto-optical disk and stores data such as image information. In addition, the CODEC 517 is a memory A50.
6 to memory D509, the image information stored in any one of them is read and encoded by a desired method of MH, MR, and MMR, and then, memory A506 to memory D5.
The data is stored in any of 09 as encoded information.

The coded information read out by the CODEC 517 and stored in the memories A506 to D509 is decoded by a desired one of the MH, MR and MMR systems, and then the memories A506 to D509. In any of the above, the decryption information, that is, the image information is stored. Next, an example of accumulating file information in the external storage device 6 will be described.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 500 and output to the compression circuit 503 through the signal line 551. Signal line 551
When the above signal (551) is input to the compression circuit 503, it is converted into compression information 552, and then input to the memory controller 510. Further, the memory controller 510 causes the timing generation circuit 514 to receive the timing signal (5
59) and stores the compressed signal (552) in the memory A 506 according to this timing signal.

The CPU 516 is the memory controller 51.
0 memory A 506 and memory B 507
Connect to the bus line 570 of C517. CODEC 5
The memory 17 reads the compressed information from the memory A506, encodes it by the MR method, and writes the encoded information in the memory B507. When the CODEC 517 finishes the encoding, the CPU 516 causes the memory controller 5
10 memory B 507 is connected to the CPU bus 560.
Then, the CPU 516 stores the encoded information in the memory B.
The data is sequentially read from 507 and transferred to the SCSI controller 519. The SCSI controller 519 stores the encoded information (572) in the external storage device 6.

Next, an example of extracting information from the external storage device 6 and outputting it to the printer unit 2 will be described. CPU51
6 receives the information retrieval / print command,
Via the SCSI controller 519, the external storage device 6
And receives the encoded information from and transfers the encoded information to the memory C508. At this time, the memory controller 510 is instructed by the CPU 516 to send the CPU bus 5
60 is connected to the bus 566 of the memory C508.

When the transfer of the encoded information to the memory C 508 is completed, the CPU 516 causes the memory controller 510 to
By controlling the memory C508 and the memory D50.
9 to bus 570 of CODEC 517. COD
The EC 517 reads the encoded information from the memory C 508, sequentially decodes it, and then transfers it to the memory D 509.

If scaling such as enlarging / reducing is required when outputting the decoded information to the printer unit 2, the memory D509 is connected to the bus 562 of the scaling circuit 511, and DM
Under the control of the A controller 518, the contents of the memory D509 are scaled. The CPU 516 communicates with the CPU 1003 of the core unit 10 via the dual port memory 515, and sets an image to be printed out from the memory D509 to the printer unit 2 via the core unit 10. Upon completion of this setting, the CPU 516 activates the timing generation circuit 514 and outputs a predetermined timing signal to the memory controller 510 through the signal line 559.
Output to.

The memory controller 510 reads the decoded information from the memory D509 in synchronization with the signal from the timing generation circuit 514 and transmits it to the signal line 556. The signal (556) on this signal line 556 is input to the decompression circuit 504, where the information is decompressed. The output signal (555) from the expansion circuit 504 is output by the connector 50.
It is output to the core unit 10 via 0. The connector 5
The operation from the 00 to the output to the printer unit 2 is performed by the core unit 1
Since the operation has been described as 0, the description thereof will be omitted here. <Explanation of computer interface section 7>
The computer interface section 7 will be described with reference to FIG.

In FIG. 7, a connector A700 and a connector B701 are SCSI interface connectors. The connector C702 is a Centronics interface connector, and is a connector D70.
Reference numeral 3 is an RS-232C interface connector. The connector E707 is a connector for connecting the computer interface unit 7 to the core unit 10.

The SCSI interface has two connectors (connector A700 and connector B70) as described above.
When connecting a device having the above 1) and a plurality of SCSI interfaces to the computer interface section 7, the connectors A700 and B701 are connected in cascade. When the external device 3 and the computer are connected one-to-one, the connector A700 and the computer are connected by a cable, and the terminator is connected to the connector B701 or the connector B7.
01 and the computer with a cable, connector A7
Connect a terminator to 00.

Connector A700 or connector B70
The information input from 1 is transmitted via the signal line 751.
SCSI I / F-A704 or SCSI I / A
It is input to F-B708. And SCSI I / F
-A704 or SCSI I / F-B708
After performing the procedure according to the SCSI protocol, the data is output to the connector E707 via the signal line 754.

The connector E707 is the CPU of the core unit 10.
The CPU 1 of the core unit 10 connected to the bus 1054
003 is a SCSI I from this CPU bus 1054.
/ F connector (connector A700, connector B70
Receive the information entered in 1). When outputting the data from the CPU 1003 of the core unit 10 to the SCSI connector (connector A700, connector B701), the procedure is reversed.

A connector C702 is used as the Centronics interface, and a signal from the connector C702 is input to the Centronics I / F 705 via a signal line 752. Centronics I / F70
5 receives data according to the procedure of the determined protocol, and the connector E707 is connected via the signal line 754.
Output a signal to. The connector E707 is connected to the CPU bus 1054 of the core unit 10 as described above, and the CPU 1003 of the core unit 10 is connected to the CPU bus 105.
4 to Centronics I / F connector (connector C
The information input in 702) is received.

A connector D703 is used as the RS-232C interface, and a signal is input to the RS-232C I / F 706 via the signal line 753. The RS-232C I / F 706 receives data according to the procedure of the determined protocol, and outputs the data to the connector E707 via the signal line 754. As already mentioned, the connector E707
Are connected to the CPU bus 1054 of the core unit 10, and the CPU 1003 of the core unit 10 is connected to the CPU bus 1054.
The information input to the RS-232C I / F connector (connector D703) is received through The data from the CPU 1003 of the core unit 10 is RS-232
When outputting to the C / I / F connector (connector D703), the procedure is reversed. <Description of Formatter Unit 8> FIG.
9 is a block diagram showing the configuration of FIG.
The configuration and operation of the formatter unit 8 will be described.

The data from the computer interface unit 7 is discriminated by the core unit 10. If the data is data relating to the formatter unit 8, the core unit 1
The CPU 1003 of 0 is the connector 100 of the core unit 10.
8 and the connector 800 of the formatter unit 9,
Data from computer is dual port memory 80
Transfer to 3.

The CPU 809 of the formatter unit 8 receives the code data sent from the computer via the dual port memory 803. And CPU8
09 sequentially develops the code data into image data, and through the memory controller 808, the memory A8
06 or the image data is transferred to the memory B807. These memories A806 and B807 each have a capacity of 1 Mbytes, and one memory (memory A806 or memory B807) can handle up to A4 paper size at a resolution of 300 dpi. Also,
When a resolution of 300 dpi and up to A3 size paper are supported, the memory A806 and the memory B807 are connected in cascade to develop image data. The above memory control is performed by the memory controller 808 according to an instruction from the CPU 809.

When it is necessary to rotate a character or a graphic when developing the image data, the character is rotated in the rotating circuit 804 and then transferred to the memory A 806 or the memory B 807. When the expansion of the image data in the memory A 806 or the memory B is completed, the CPU 809 controls the memory controller 808 to connect the data bus line 858 of the memory A 806 or the data bus line 859 of the memory B 807 to the output line 85 of the memory controller 808.
Connect to 1.

Next, the CPU 809 communicates with the CPU 1003 of the core unit 10 via the dual port memory 803, and sets the mode in which the image information is output from the memory A 806 or the memory B 807. In addition, the CPU 1003 of the core unit 10 uses the communication IC 1 in the core unit 10.
Via 002, the print output mode is set in the CPU 122 using the communication function built in the CPU 122 of the reader unit 1.

When the print output mode is set, the CPU 1003 of the core unit 10 activates the timing generation circuit 802 via the connector 1008 and the connector 800 of the formatter unit 8. Timing generation circuit 8
02 indicates the memory A 806 or the memory B 80 to the memory controller 808 according to the signal from the core unit 10.
7 generates a timing signal for reading image information.

The image information from the memory A 806 or the memory B 807 is input to the memory controller 808 via the signal line 858 or the signal line 859. Then, the output image information from the memory controller 808 is transferred to the core unit 10 via the signal line 851 and the connector 800. The output from the core unit 10 to the printer unit has been described in the core unit 10, and thus the description thereof is omitted here. <Description of Image Memory Unit 9> The configuration and operation of the image memory unit 9 will be described below with reference to the block diagram shown in FIG.

The image memory unit 9 is connected to the core unit 10 via the connector 900 and exchanges various signals. The multi-valued input signal (954) is stored in the memory 904 under the control of the memory controller 905. The memory controller 905 is (1) a mode for exchanging data with the memory 904 via the CPU bus 957 according to an instruction from the CPU 906, and (2) a timing generation circuit 9
Under the control of 02, it has three functions: a mode for storing the signal (954) in the memory 904, and (3) a mode for reading the memory content from the memory 904 and outputting it to the signal line 955.

The memory 904 has a capacity of 32 Mbytes, has a resolution of 400 dpi, 256 gradations, and
An image corresponding to three sizes is stored. Further, the timing generation circuit 902 is connected to the connector 900 by a signal line 952, and the control signal (HSYN
C, HEN, VSYNC, VEN) to generate signals to achieve the following two functions.

That is, one of the functions is the core unit 10.
The second is the function of reading the image information from the memory 904 and transmitting it to the signal line 955. Further, the dual port memory 903 is connected to the CPU 1003 of the core unit 10 via the signal line 953 and the connector 900,
CPU of the image memory unit 9 via the signal line 957
It is connected to 906. Each of these CPUs exchanges commands via the dual port memory 903.

Here, an example in which image information is stored in the image memory unit 9 and this information is transferred to a computer will be described. The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 900 and input to the memory controller 905 via the signal line 954. The timing generation circuit 902 generates a timing signal (956) according to the signal (952) from the core unit 10, and the memory controller 905 stores the signal (954) in the memory 904 according to this signal. Then, the CPU 906 replaces the memory 904 of the memory controller 905 with the CPU bus 95.
Connect to 7.

The CPU 906 sequentially starts from the memory 904.
The image information is read and transferred to the dual port memory 903. In addition, the CPU 1003 of the core unit 10
Is a dual port memory 903 of the image memory unit 9.
The image information inside is read through the signal line 953 and the connector 900, and this information is transferred to the computer interface section 7. The operation of transferring information from the computer interface unit 7 to the computer has already been described, and will be omitted here.

Next, an example of outputting the image information sent from the computer to the printer unit 2 will be described. The image information sent from the computer is sent to the core unit 10 via the computer interface unit 7. The CPU 1003 of the core unit 10 is the CPU bus 105.
4 and the image memory unit 9 via the connector 1009.
The image information is transferred to the dual port memory 903. At this time, the CPU 906 determines that the memory controller 9
05 to connect the CPU bus 957 to the bus of the memory 904.

The CPU 906 is a dual port memory 9
Image information from the memory controller 905.
To the memory 904 via. And the memory 90
Upon completion of transferring the image information to 4, the CPU 906
The memory controller 905 is controlled to connect the data line of the memory 904 to the signal line 955. CPU90
6 is the core unit 1 via the dual port memory 903.
No. 0 CPU 1003 is communicated with, and settings for printing out an image from the memory 904 through the core unit 10 to the printer unit 2 are performed.

Upon completion of this setting, the CPU 906
The timing generation circuit 902 is activated and the signal line 9
A predetermined timing signal is output to the memory controller 905 via 56. The memory controller 905 is
Image information is read from the memory 904 in synchronization with the signal from the timing generation circuit 902, transmitted to the signal line 955, and output to the connector 900. In addition,
The operation up to outputting from the connector 900 to the printer unit 2 has already been described, and will be omitted.

FIG. 10 is a schematic view of a computer interface unit having a switching device built therein. As shown in the figure, the switching device 800 operates according to an instruction from the CPU 1003 arranged in the core unit 10.
For example, a terminal device such as a computer is a connector C70.
Centronics I / F 705 when connected to 2
Is output when the signal line 801 is logic high
The output destination to the OUT2 side when the signal line is logic low.

The initial setting of the switching device 800 is set to O.
When set to UT2 side, the input signal from the terminal is C
The formatter unit 8 directly without passing through the PU bus 1054.
Is input to and the processing in the formatter unit 8 is executed. At this time, since the CPU bus 1054 is not used by the input from the terminal device, it can be used for exchanging data with other option boards.
Further, the formatter unit 8 performs processing in response to a processing request from the terminal device, but the formatter unit 8 cannot process, for example, when a processing request for the reader unit 1 is received, the CPU 809 of the formatter unit 8 , C
CPU 1003 of the core unit 10 via the PU bus 1054
Send a processing request to.

When the CPU 1003 of the core section receives the above processing request, it switches the signal line 801 to the logical high state and sets the output destination of the switching device 800 of the computer interface section 7 to the OUT1 side. By this operation, the processing request from the terminal device is sent to the CPU bus 1
It is transmitted to the CPU 1003 via 054. CPU100
3 is a signal line 801 after the processing request from the terminal device is completed.
Is set to the logic low output, the output destination of the switching device 800 is set to the OUT2 side, the transmission destination of the data from the terminal device is reset to the formatter unit 8, and the processing is continued.

As described above, according to this embodiment,
In an image forming device consisting of a main board and multiple option boards, command processing and data input from a terminal device connected to the outside of the main board or multiple option boards are switched to the main board or multiple option boards and output. By doing so, the processing load on the main control unit on the main board is reduced, and it is not necessary to have a processor that operates faster than necessary as the main control unit.
Further, since the occupation time of the main control bus required for the communication processing between the terminal device and the board is reduced, a plurality of processings can be performed in parallel. <Modification> A modification of the above embodiment will be described below.

FIG. 11 is a schematic block diagram of a computer interface unit incorporating a switching device according to this modification. In the figure, the same components as those of the apparatus according to the above embodiment are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 11, switching devices 840, 8
Reference numeral 50 denotes an output signal OUT1 and an output signal O from the CPU 220 incorporated in the computer interface unit 7.
Switching control is performed by the UT2. This CPU2
The reference numeral 20 constantly analyzes the signal contents of the signal IN1 and the signal IN2 input to the computer interface unit 7, and based on the analyzed contents, the switching device 84
Switching control of 0,850 is performed.

For example, the signal of IN1 input from the connector C702 is switched to the core unit 10 or the formatter unit 8 as a result of command and data analysis, and the signal of IN2 input from the connector A700 is
The core unit 10 or the fax unit 4, or the file unit 5 can be switched. CPU 220
Analyzes the command or data received from IN1 and sets the output destination of the switching device 840 to OUT2 when the formatter unit 8 can process the data. And
An input signal from the terminal device is directly input to the formatter unit 8 without passing through the CPU bus 1054, and the processing there is executed. At this time, since the CPU bus 1054 is not used by the input from the terminal device, it can be used for exchanging data with other option boards.

The formatter section 8 performs processing in response to a processing request from the terminal device. When the CPU 220 receives a processing request that the formatter unit 8 cannot process, for example, the processing of the reader unit 1 or the like, the switching device 840.
Of the core unit 10 to a processing request from the terminal device via the CPU bus 1054.
Send to U1003. The CPU 1003 performs processing according to this processing request.

Further, the CPU 220 analyzes the command or data received from IN2, and when the result is that the fax unit 4 or file unit 5 can process the data, the output destination of the switching device 850 is OUT4 or OUT5.
Set to. Then, the input signal from the terminal device is
The data is directly input to the fax unit 4 or the file unit 5 without passing through the U bus 1054, and the processing is executed in each option board. At this time, since the CPU bus 1054 is not used by the input from the terminal device, it can be used for exchanging data with other option boards.

In the example shown in FIG. 11, the fax unit 5 performs processing in response to a processing request from the terminal device. CPU2
When the processing unit 20 receives a processing request such as the processing of the reader unit 1 that cannot be processed by the fax unit 5 or the file unit 4, the output destination of the switching device 850 is OUT1.
Switch to 2. Then, the processing request from the terminal device
CPU 10 of the core unit 10 via the CPU bus 1054
Send to 03. The CPU 1003 performs processing according to this processing request.

[0101]

As described above, according to the present invention,
By switching the output destination of the command and data to the main board or multiple option boards according to the analysis result of the input commands and data, the processing load on the control unit on the main board is reduced, and the main board is unnecessary. You don't have to have a fast processor.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an image forming system according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional configuration of a reader unit and a printer unit.

FIG. 3 is a circuit block diagram showing a signal processing configuration of a reader unit 1.

FIG. 4 is a block diagram showing a configuration of a core unit 10.

5 is a block diagram showing a detailed configuration of a fax unit 4. FIG.

FIG. 6 is a block diagram showing a detailed configuration of a file section 5.

FIG. 7 is a block diagram showing a configuration of a computer interface unit 7.

FIG. 8 is a block diagram showing a configuration of a formatter unit 8.

9 is a block diagram showing a configuration of an image memory unit 9. FIG.

FIG. 10 is a schematic diagram of a computer interface unit including a switching device.

FIG. 11 is a schematic block diagram of a computer interface unit including a switching device according to a modified example of the embodiment.

[Explanation of symbols]

1 reader unit 2 printer unit 3 external device 4 fax unit 5 file unit 6 external storage device 7 computer interface unit 8 formatter unit 9 image memory unit 10 core unit 15 computer 101 document feeder 102 document platen glass surface 103 lamp 104 scanner Units 105, 106, 107 Mirror 108 Lens 109 CCD image sensor section 110R, 110G, 110B Amplifier 111 A / D converter 112 Shading circuit 113 Y signal generation / color detection circuit 114 Magnification / repeat circuit 119 External I / F switching Circuit 115 Contour / edge enhancement circuit 116 Marker area determination / contour generation circuit 117 Patterning / thickening / masking / trimming circuit 117 118 Laser driver circuit 119 External I / F switching Circuit 120 connector 121 area generation circuit 122 CPU 123 SUB / CPU 201 exposure control unit 202 photoconductor 203 developing device 204, 205 transfer paper stacking unit 206 transfer unit 207 fixing unit 208 paper discharge unit 209 conveyance direction switching member 210 re-feeding Transferred paper stacking unit for paper 1001, 1005 to 1009 Connector 1002 Communication IC 1011 LUT 1022 Enlarged circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideki Ozaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (4)

[Claims] 1. An interface device comprising an external control unit comprising a main board for controlling the main control of the device and a plurality of option boards, and an external device connected to the external control unit, wherein a command input from the external device is provided. Alternatively, it comprises means for analyzing data, and switching means for outputting the command or data by switching to the main board or the plurality of option boards according to the result of the analysis and outputting the command board or the plurality of option boards. An interface device characterized by being included in. 2. The interface device according to claim 1, wherein the switching means is set to switch to a specific board of the plurality of option boards or the main board as an initial setting. 3. The interface device according to claim 1, wherein the switching instruction to the switching unit is issued by the main board or the plurality of option boards. 4. The main board has a main bus for the main control on the board, and the plurality of option boards have a local bus for connecting the boards to each other. The interface device according to claim 1, wherein the command or the data is output using the local bus without using the main bus.