JPH06149627A - Monitoring device for computer system - Google Patents

Abstract

PURPOSE:To monitor plural software processes and to specify a software process generating abnormality by making it possible to monitor plural software processes in executing as abnormality monitoring objects. CONSTITUTION:In a software process group 7 to be driven by a computer device 1, a counter reset signal D8 generated at the time of normal operation is specified in each overflow of a counter device 5 and stored in a counter latch circuit 6 and a software process continuously sending the counter reset signal D8 over the prescribed number of overflows in the device 5 is processed by the device 1 and stored in a reset expected value register 10. The contents of the circuit 6 is compared with that of the register 10 by a compare logic 11, and at the time of detecting abnormality, an alarm signal D2 is outputted from an alarm signal generating circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system monitoring apparatus, and more particularly to a computer system monitoring apparatus suitable for performing abnormality monitoring in an industrial computer system.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional computer system monitoring apparatus. In the figure, 1 is a computer device that is an object of abnormality monitoring, 5 is a counter device that counts down at preset time intervals and operates as a timer, 3 is a counter control device that controls the operation of the counter device 4, and 4 is a counter device. The overflow value of 5, that is, a count value register for storing the set time, 14 is a data bus to which the computer device 1 and the count value register 4 are connected, and 15 is a software process which is a target of abnormality monitoring in the computer device 1. Note that the software process 15 of the computer device 1 sends a reset signal D17 at regular time intervals as proof that it is operating normally, and this reset signal D17 is given to the counter control device 3. On the other hand, the counter control device 3 to the computer device 1
An interrupt signal D16 is sent to Further, the counter control device 3 sends a warning signal D2 for notifying the outside that the software process 15 of the computer device 1 is in an abnormal state. The operation of the configuration described above will be described below.

First, when the computer device 1 releases the warning signal D2 to the outside, the count value stored in the count value register 4 is loaded into the counter device 5 under the control of the counter control device 3. The count value of the count value register 4 is set to a value larger than the time interval at which the software process 15 sends the reset signal D17 during normal operation. And
The setting is set in the counter device 5 from the computer device 1 via the data bus 14.

The counter device 5 loaded with the count value as described above immediately starts counting down.
However, when the counter control device 3 receives the reset signal D17 generated by a specific software process 15 provided to the computer device 1, the counter device 5 is reset and the count value from the count value register 4 is set again. Performs countdown operation. As long as the reset signal D17 is continuously received from the software process 15 of the computer device 1 during this countdown operation, the counter device 5 similarly repeats resetting and countdown. That is, as long as the software process 15 is operating normally, the reset signal D17 is output during the countdown of the counter device 5, so the counter device 5 does not overflow and repeats the countdown operation.

Now, the counter control device 3 is the computer device 1
If the counter device 5 overflows before receiving the reset signal from, that is, before the countdown of the counter device 5 is completed, the software process 15
When the counter control device 3 cannot output the reset signal D17, the counter control device 3 sends the interrupt signal D to the computer device 1.
16 is transmitted. As a result, the counter control device 3 resets the counter device 5, and the count value register 4
Then, the count value is set in the counter device 5 again, and the counter device 5 is caused to count down again.

During the second countdown operation, the counter control device 3 resets the reset signal D1 from the computer device 1.
When 7 is not received, that is, when the software process 15 cannot output the reset signal D17, the counter device 5 causes overflow again, but in this case, the counter control device 3 issues an external warning. The signal D2 is transmitted to notify the outside that the software process 15 of the computer system 1 is abnormal.

[0007]

Since the conventional computer system monitoring device is constructed as described above, the counter device 5 can be reset only by the specific software process 15 incorporated in the computer device 1. If there are multiple software processes, it is not possible to know in which software process the error occurred, and if there is a software process with a lower priority than the monitored software process, the error is detected. There is a problem that it cannot be detected.

The present invention has been made to solve the above problems, and scans a plurality of software processes being executed, and abnormally monitors all the registered software processes based on the scan results. It is an object of the present invention to provide a computer system monitoring device capable of monitoring a plurality of software processes and identifying a software process in which an abnormality has occurred.

[0009]

In order to achieve the above object, the computer system monitoring apparatus according to claim 1 executes a plurality of software processes for generating reset signals at predetermined time intervals during normal operation. A computer system, a timer means for timing out at a predetermined time interval, a latch means for specifying a software process that has sent a reset signal in the software process for each time-out of the timer means, and the timer means. The reset expected value storage means for storing the software process which has continuously sent the reset signal for a predetermined number of times as the reset expected value, and the contents of the latch means and the contents of the reset expected value are compared to find a difference. A computer system including: a comparing unit that determines an abnormality when it occurs. There is provided a viewing device.

In order to achieve the above object, a computer system monitoring apparatus according to a second aspect of the present invention is a computer system that executes a plurality of software processes that generate reset signals at predetermined time intervals during normal operation. , Timer means for timing out at a predetermined time interval,
Latch means for specifying a software process that has sent a reset signal in the software process each time the timer means times out, and a software process that has continuously sent a reset signal for a predetermined number of times of the timer means Is stored as a reset expectation value, and the contents of the latch means and the contents of the reset expectation value are compared with each other to judge an abnormality when there is a difference, and the software process causing the abnormality And a computer system monitoring apparatus including an abnormality determining unit for identifying the above.

Further, in order to achieve the above object, a computer system monitoring apparatus according to a third aspect of the present invention is a computer system that executes a plurality of software processes that generate reset signals at predetermined time intervals during normal operation. A registration means for registering a specific software process, a timer means for timing out at a predetermined time interval,
Latch means for specifying a software process that has sent a reset signal in the software process each time the timer means times out, and a software process that has continuously sent a reset signal for a predetermined number of times of the timer means Is stored as a reset expectation value, and the contents of the latch means and the contents of the reset expectation value are compared with each other to judge an abnormality when there is a difference, and the software process causing the abnormality A computer system monitoring device comprising: an abnormality determining means for identifying the above, and a warning means for notifying an abnormality when the software process identified by the abnormality determining means matches the software process registered in the registration means. It is provided.

[0012]

According to the computer system monitoring apparatus of the present invention, a reset signal generated during normal operation in a plurality of software processes operating in the computer system is specified for each time-out of the timer means and stored in the latch means. The software process that has continuously sent the reset signal for a predetermined number of times of the timer means is stored in the reset expectation value storage means as the reset expectation value, and the contents of the latch means and the contents of the reset expectation value are compared. If there is a difference, the comparing means determines that there is an abnormality.

According to another aspect of the computer system monitoring apparatus of the present invention, a reset signal generated during normal operation in a plurality of software processes operating in the computer system is specified for each timeout of the timer means and stored in the latch means. A software process that has continuously sent a reset signal for a predetermined number of times of the timer means is stored in the reset expectation value storage means as a reset expectation value, and the abnormality determination means resets the contents of the latch means and the resetting. If the contents of the expected values are compared and a difference occurs, the abnormality is judged and the software process that caused the abnormality is specified.

A computer system monitor according to claim 3
The device is a set of software that operates in a computer system.
Reset generated during normal operation in the wear process
Latches the specified signal every time the timer means times out.
Stored in the means, and the predetermined time-out of the timer means
Software that continuously sends the reset signal over the number of times
Wear process as reset expected value Reset expected value
It is stored in the storage means, and the abnormality determination means stores the latch.
Compare the contents of the reset means and the contents of the reset expected value
If there is a difference, the abnormality is judged and the software that caused the abnormality is detected.
Software process, and the warning means
Register the software process that has always been the cause as a registration method.
If the recorded software process matches and matches
If it does, an error will be reported.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a computer system monitoring apparatus according to an embodiment of the present invention. In the figure, 7 is a software process group including a plurality of software processes incorporated in the computer apparatus 1 to be monitored for an abnormality, and 6 is a latch group assigned to each software process of the software process group 7. The counter reset signal D which has and is sent from the software process group 7
8 is a counter latch circuit that latches 8; 10 is a reset expected value register that stores a reset expected value based on the scanning result of the software process group 7 in the computer apparatus 1 based on the signal from the counter latch circuit 6;
Reference numeral 1 is a compare logic for logically comparing the output of the counter latch circuit 6 and the output of the reset expected value register 10 and sending the comparison result to the counter control device 3. Reference numeral 13 is connected to the computer device 1 via a data bus 14. The warning signal generation circuit determines whether or not to output the warning signal D2 based on the output result of the reset expected value register 10 and the output of the counter control device 3. The counter control device 3 sends an interrupt signal D9 to the computer device 1 in order to scan the software process currently in progress in the software process group 7 of the computer device 1. Also,
The counter control device 3 sends an interrupt signal D12 to the computer device 1 when an abnormality is found in any of the software processes in the software process group 7 from the output result of the compare logic 11.

The operation of the above-described structure will be described below with reference to the flow chart of FIG.

First, when the computer device 1 releases the warning signal D2 to the outside, the count value stored in the count value register 4 is loaded into the counter device 5 under the control of the counter control device 3. The count value of the count value register 4 is the data bus 1
The count value of the counter reset signal D8 output when the arbitrary software process of the software process group 7 operating in the computer device 1 is normally operated. The value is set to cover the output time interval. At the same time, the counter latch circuit 6 arranged corresponding to each software process of the software process group 7 is enabled.

The counter device 5 loaded with the count value as described above immediately starts the countdown, that is, the timer operation. During this period, the counter reset signal D8 generated by a certain software process in the software process group 7 provided in the computer device 1 is held in the counter latch circuit 6 for each output.

Now, the counter device 5 during the countdown
When the counter overflows due to a timeout, the counter control device 3 generates an expected value generating interrupt signal D9 to the computer device 1. As a result, the computer system 1 starts an interrupt process for generating an expected value.

In this process, first, as shown in step S1, the data held in the counter latch circuit 6 is read. Next, as shown in step S2, an AND condition is obtained with the data read in the previous similar interrupt processing. Then, as shown in step S3, for example, only the data bit of the software process that has transmitted the counter reset signal D8 twice consecutively is held as the reset signal expected value.

The above-described processing is performed every time the counter device 5 overflows. This is determined in step S4 while restarting the countdown of the counter device 5 in step S5 and returning in step S6.
It is executed by repeating the same operation.

When the number of repetitions reaches a predetermined number N, this is judged in step S4, and at this stage, the software in the software process group 7 which can send the reset signal before the counter device 5 overflows. Determine the process. The expected reset value is step S7.
At, the data is stored in the reset expected value register 10 via the data bus 14.

When the above processing is completed, the processing proceeds to step S8, the countdown of the counter device 5 is restarted, the operation returns at step S9, and the same operation is repeated.

After the reset expected value is stored in the reset expected value register 10, the counter control device 3 outputs the reset expected value of the counter latch circuit 6 and the reset expected value register 10 every time the counter device 5 overflows. The comparison is made via the compare logic 11. If there is a difference between the two, an interrupt signal D12 is sent to the computer apparatus 1 as a software process error.
To occur. That is, the software process in which the error occurred is the reset expected value register 1 as the reset expected value.
Although registered as 0, the counter reset signal D8 could not be output before the counter device 5 overflowed, so that it is determined to be abnormal.

The computer system 1 uses the interrupt signal D12.
Upon receipt, the software process that caused the abnormality is identified and sent to the warning signal generation circuit 13. The warning signal generation circuit 13 determines whether a specific software process in the software process group 7 set in advance in the warning signal generation circuit 13 and a software process that causes a difference in the compare logic 11 match. , A warning signal D2 is sent to the outside to notify the occurrence of an abnormality. Incidentally, any software process in the software process group 7 preset in the warning signal generation circuit 13 can be freely set and changed from the computer device 1 through the data bus 14.

The expected value generation interrupt process is performed each time the counter device 5 overflows, and the reset signal expected value is updated each time the counter device 5 overflows. As a result, it is possible to monitor a plurality of software processes that can be processed within the overflow time of the counter device 5.

In the above embodiment, only one type of count value is set in the counter device 5 from the count value register 4. However, this count value is set at regular intervals or in the software process group 7. The switching may be performed in a timely manner according to the frequently used software process, and more accurate abnormality monitoring can be performed.

Further, in the above embodiment, the counter device 5 is used as a timer which can be reset and times out at regular intervals, but a timer circuit such as a crystal oscillator can achieve the same object. It goes without saying that you can do it.

Further, in the above-described embodiment, the configuration in which an interrupt is generated in the computer device 1 when an abnormality is detected has been exemplified.
Depending on the abnormal status, the system may run out of control, and in such a case, it will not be possible to accept interrupts.Therefore, the system should be reset immediately or it is judged that no interrupts have been accepted. The system may be reset by resetting.

In the above embodiment, the warning signal generation circuit 13 outputs the warning signal D2 only when an abnormality occurs in a specific software process in the software process group 7.
Although the configuration for outputting the above is illustrated, the configuration may be such that when any one of the software process groups 7 is found to be abnormal, the warning signal D2 is transmitted.

[0032]

As described above, according to the present invention, the computer system monitoring device can perform abnormality monitoring of any software process currently being executed by scanning a plurality of software processes, and a plurality of software processes can be monitored. It can be applied to process abnormality monitoring and can identify abnormally operating software processes, which makes debugging work and process recovery efficient, and has a significant impact on abnormal software processes. Since only the items can be selected and an alarm can be issued, it is possible to flexibly respond to the system.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system monitoring apparatus according to an embodiment of the present invention.

FIG. 2 is a flow chart for explaining the operation of the configuration of FIG.

FIG. 3 is a block diagram of a conventional computer system monitoring device.

[Explanation of symbols]

 1 Computer Device 3 Counter Control Device 4 Count Value Register 5 Counter Device 6 Counter Latch Circuit 7 Software Process Group 10 Reset Expected Value Register 11 Compare Logic 13 Warning Signal Generation Circuit 14 Data Bus 15 Software Process

Claims (3)

[Claims] 1. A computer system that executes a plurality of software processes that generate reset signals at predetermined time intervals during normal operation, timer means that times out at predetermined time intervals, and timeout of the timer means. Latch means for specifying the software process that has sent the reset signal in each of the software processes, and the software process that has continuously sent the reset signal for a predetermined number of times out of the timer means as the reset expected value. A computer system monitoring apparatus comprising: a reset expectation value storage means for storing the contents; and a comparison means for comparing the contents of the latch means with the contents of the reset expectation value to determine an abnormality when a difference occurs. . 2. A computer system that executes a plurality of software processes that generate reset signals at predetermined time intervals during normal operation, timer means that times out at predetermined time intervals, and time-out of the timer means. Latch means for specifying the software process that has sent the reset signal in each of the software processes, and the software process that has continuously sent the reset signal for a predetermined number of times out of the timer means as the reset expected value. The reset expected value storing means for storing and the contents of the latch means and the contents of the reset expected value are compared to determine an abnormality when a difference occurs,
A computer system monitoring device, comprising: an abnormality determining unit that identifies a software process that has caused an abnormality. 3. A computer system that executes a plurality of software processes that generate a reset signal at predetermined time intervals during normal operation, a registration means that registers a specific software process, and a predetermined time interval. Timer means for time-out, a latch means for specifying a software process that has sent a reset signal in the software process for each time-out of the timer means, and a timer means for continuously resetting for a predetermined number of time-outs The contents of the latch means and the contents of the reset expectation value are compared with the reset expectation value storage means for storing the software process that has sent the signal as the reset expectation value, and if there is a difference, an abnormality is judged and Abnormality determination means that identifies the software process that caused the And warning means for abnormality notification if they match butted with software process that is registered in the registration means software process which is identified by atmospheric determining means, computer system monitoring device, characterized in that it comprises a.