JP2610670B2 - Testing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a test apparatus suitable for monitoring the presence or absence of an abnormality in an output signal generated from a power panel, etc., and automatically monitors the presence or absence of an abnormality in an output signal generated from a power panel, etc. When testing a device under test, a test condition specified by the condition specifying unit is set in the condition output unit at the start of a test for a period for the test condition specified by the specification via the condition setting means. And
When the test data corresponding to the set test condition is supplied from the test data output unit to the device under test, or the output of the state output unit occurs within a period for the test condition according to the designation. Each time, at the start of the test, the same test conditions as those set in the condition output unit are reset in the condition output unit, and test data corresponding to the reset test conditions is sent from the test data output unit to the test data output unit. When supplied to the test apparatus, information indicating an abnormal state of the device under test generated for any of the settings is output to the state output unit, and the test condition set in the condition specification unit The update by the update means is generated immediately after the elapse of the period.

[Industrial applications]

The present invention relates to a test apparatus such as a power panel, and more particularly, to a test apparatus suitable for monitoring whether an output signal generated from the power panel or the like is abnormal.

[Conventional technology]

A power supply panel used for an information processing apparatus or the like is configured to generate various output signals in response to a signal from a main unit. When generating various output signals from the power panel,
When an instantaneous abnormal signal is generated, the output signal has an extremely large effect on the entire main unit. Therefore, it is necessary to monitor the presence or absence of various output signals generated from the power supply panel.

Therefore, in a conventional monitoring device that performs a test on a power panel, a test condition for the power panel is set, an output signal from the power panel in response to the test condition is taken, and whether the output signal matches the set value. That is, it is configured to make a determination as to whether or not it is not. That is, a method is used in which an output signal from the power supply panel is compared with a preset signal according to an empirical allowable number of times, and an error display is performed if the signals do not match within the allowable number of times.

[Problems to be solved by the invention]

However, the conventional monitoring system monitors only the output signal from the power panel in response to a command from the main unit. Could not be automatically monitored for abnormalities. The only way to do that was to do it artificially.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a test apparatus capable of automatically monitoring whether an output signal generated from a power panel or the like is abnormal.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, the invention according to claim 1 includes a condition output unit 2 for sending test conditions, and a test for sending test data to the device under test 1 together with sending of test conditions from the condition output unit 2. A data output unit 3, a state output unit 4 for outputting information indicating the state of the device under test 1 with respect to the test conditions sent from the condition output unit 2, a condition specifying unit 6 for specifying test conditions, Update means 8 for updating the specification of conditions
A condition setting unit 10 for setting test conditions in the condition output unit 2; and a test control unit 12.
Sets a test condition specified by the condition specifying unit 6 to the condition output unit 2 via the condition setting means 10 at the start of a test for a period for the test condition specified by the condition setting unit 10; When test data corresponding to the set test conditions is supplied from the test data output unit 3 to the device under test 1,
Alternatively, each time the output of the state output unit 4 occurs within the period for the test condition according to the designation, the same test condition as the test condition set in the condition output unit 2 at the start of the test is used. When the test data corresponding to the reset test conditions is supplied from the test data output unit 3 to the device under test 1. 1 is output to the status output unit 4 so that the update by the updating unit 8 is performed immediately after the period for the test condition set in the condition specifying unit 6 elapses. It was done.

A test condition is set in the condition output unit 2, test data corresponding to the test condition is supplied from the test data output unit 3 to the device under test (power supply panel, etc.) 1, and a signal representing a state corresponding to the test condition is received. Whether or not a response is returned from the test apparatus 1 is constantly monitored by the state output unit 4, and each time an output of the state output unit 4 occurs, that is, whether the response from the device under test 1 is normal or abnormal. Regardless of this, when a signal (response) is generated and within the test period, the test condition is reset in the condition output unit 2 and test data corresponding to the reset test condition is set. Test data output unit 3
To the device under test 1 and constantly monitored by the status output unit 4, that is, the device under test 1
Is monitored to determine whether an abnormal response is returned, so that when an abnormality occurs in the device under test 1, it is possible to automatically confirm the abnormality.

〔Example〕

In FIG. 2, the control unit 10 constituting the power monitoring device has a CPU 12, a CRT 14, a keyboard 16, a floppy disk 18, an interface (GP-IB) 20, and a digital input / output interface (DIO) 22. The floppy disk 18 stores a program for executing the processing shown in FIG. 4 and executing steps 110 to 124 (this corresponds to the test control means 12 in FIG. 1). The flag (FLG) (first
A program for updating the condition is also stored in the floppy disk 18 (which corresponds to the updating means 8 in FIG. 1). An interface 20 is connected to a digital multimeter (DMM) 24, and a digital input / output interface 22 is connected to an alarm I / O.
It is connected to a power panel 28 via an O circuit (ALMI / O) 26. The CPU 12, the floppy disk 18, and the digital input / output interface 22 correspond to the condition setting means 10 in FIG.
Further, the digital input / output interface 22 is connected to a power supply panel 28 via a control latch (CONT latch) 30, a scan circuit (SCAN) 32, a slidac (AC) 34, and a load (LOAD) 36. The scan circuit 32 is connected to a digital multimeter 38. The control latch 30 is connected to a panel 42 via a manual controller (MANUAL CONT) 40.

As shown in FIG. 3, the alarm I / O circuit 26 includes a control unit 44, a gate circuit 46, a data latch 48, a comparator 50, and an input latch 52.
28, the output of gate circuit 46 and data latch 48
Is connected to the bus line and the data latch 48
And the input of the control unit 44 are connected to the address line. The control unit 44 performs the processing of 100 to 108 in FIG. 4 and the processing of 200 to 220 in FIG. Input latch 52, comparator
50, the processing of 200 to 220 in the processing flow of FIG. 5 in the control unit 44, and the digital input / output interface 22 corresponds to the state output unit 4 of FIG.

This embodiment has the above configuration, and its operation
A description will be given based on the processing flow of FIG. 5 and FIG.

First, when various test conditions are input from the keyboard 16, each test condition is stored in the floppy disk 18.
Then, a command for executing a test on one ALM signal condition is output to the power supply panel 28, and when a flag (FLG) corresponding to the ALM signal condition is set on the floppy disk 18 of the control unit 10, the control unit 44 On the other hand, the process of disabling the hard interrupt is performed (100 in FIG. 4), and the setting process of the alarm signal condition is performed based on the test condition stored in the floppy disk 18 (102 in FIG. 4).
The setting of the alarm signal condition in step 102 in the processing starting from “start” in the processing flow of FIG. 4 represents the setting of “at the start of test” described in claim 1 of the claims. The set flag (FLG) is set until the flag corresponding to the next ALM signal condition is set. Thereafter, monitoring for monitoring the output signal from the power supply panel 28 is started (104 in FIG. 4). Subsequently, the prohibition of the hardware interrupt is released to enable the hardware interrupt (106 in FIG. 4), and alarm data is input to the power supply panel 28 (108 in FIG. 4).

After the alarm data has been sent to the power board (device under test), the control unit 44 enters the processing shown in FIG.

The presence or absence of interruption from the power panel is determined (see Fig. 5).
200), if there is no interruption, the process proceeds to 220 in FIG.
If there is an interrupt, itrt (interrupt control flag) is set to 0 (202 in FIG. 5), and a hard interrupt prohibition process is executed for comparison (204 in FIG. 5). A process for monitoring a signal is started (206 in FIG. 5), and an alarm signal from the power supply panel 28 is read (208 in FIG. 5). Then, it is determined whether or not the count value for the monitoring count is, for example, 1000 (see FIG. 5).
210), it is determined whether the signal condition matches the read signal until the count value reaches 1000 (see FIG. 5).
212). Then, when the determination conditions do not match, the process returns to the process at 206 in FIG. 5 again. At this time, the number of monitoring is incremented by one. On the other hand, when they match, a process is performed in which the signal condition matches the read signal (see FIG. 5).
214). Thereafter, Itrt is set to 1 (216 in FIG. 5), and control is passed to the control unit 10 (220 in FIG. 5).

When the count value reaches 1000, the error flag (ERR) is set to 1 (indicating mismatch) (step 21).
8), transfer control to control unit 10 (2 in FIG. 5)
20).

As described above, even when an alarm condition has not occurred (NO in 200 in FIG. 5), an interruption from the power supply panel may be generated, regardless of whether or not an error condition occurs (see FIG. 4).
214, 218), the control unit 44 notifies the control unit 10 to start the information collection process on the test state of the power board (220 in FIG. 4).

Upon receiving this notification, the control unit 10
The processing after 110 in the figure is started.

It is determined whether Itrt is 1 (11 in FIG. 3).
0). If it is 0 (NO in 110 in FIG. 4), the process of prohibiting the hardware interrupt is performed (112 in FIG. 4). The process for monitoring the signal of the power board 28 is started (114 in FIG. 4), and the power board 2 is started.
The alarm signals from 8 are sequentially taken in (116 in FIG. 4).
Then, a process for setting the error flag (ERR) to 1 is performed (118 in FIG. 4).

On the other hand, when Itrt = 1 is determined at 110 in FIG. 4, it is determined whether the error flag (ERR) is 0 (see FIG. 4).
(Fig. 120). When the error flag is not 0, error processing is performed (122 in FIG. 4). In the error processing, as shown in FIG.
Displayed on the screen of CRT14. Before entering the error processing, a screen as shown in FIG. 6 (A) was displayed on the screen of the CRT 14. When the error processing is started, a screen as shown in FIG. 6 (B) is displayed on the CRT 14. Displayed on the screen. 6B in FIG. 6B indicates normal, and X indicates abnormal. FIG. 6 (B)
Each of the screen areas shown on the lower side of the screen shown in (1), the re-test, the next test, and the end corresponds to the function keys on the keyboard provided on the CRT 14, and when pressed, each operation is generated . When the next screen is designated by the keyboard, for example, data corresponding to the count is displayed each time the key is pressed. Counts on first press 31
The data corresponding to the data items 60 to 60 and the data items corresponding to the data items 61 to 90 are sequentially displayed by the next press. In the retest, the screen is returned to the screen of FIG. 6 (A), and the test is performed from the position where the error occurred. In the next test, a test for the next ALM signal condition is performed ignoring the error part. Termination terminates the current test.

After the processing is completed, the process proceeds to the process of 124 in FIG. 4, and proceeds to the process for setting the next ALM signal condition when the period for the test condition has elapsed. When the setting process is completed, 10 in FIG.
Returning to 0, processing such as setting to the control unit 44 according to the flag (FLG) is continued. Therefore, if the value of the flag (FLG) is the same, the test of the power board 28 under the ALM signal condition corresponding to the flag (FLG) is restarted.

Then, when the above-described series of processing for all the ALM signal conditions is completed (Y of 124 in FIG. 4), the test for the power board is completed.

〔The invention's effect〕

As described above, according to the first aspect of the present invention, it is determined whether a response from the device under test to the test data supplied to the device under test matches a test condition set for the test data. Each time the response occurs, if the test condition is within the period for the test condition, the same test condition is reset and the same test data is resupplied so that the device under test returns an abnormal response. Since the presence or absence of the abnormality is constantly monitored, when an abnormality occurs in the device under test 1, the abnormality can be automatically confirmed.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the invention described in claim 1, FIG. 2 is a configuration diagram of an embodiment of the invention described in claim 1, FIG. FIG. 4 is a view showing a part of the processing flow of the embodiment shown in FIG. 2, FIG. 5 is a view showing the rest of the processing flow of the embodiment shown in FIG. 2, and FIG. 6 is shown in FIG. It is a figure showing the example of a display of an example. 1 to 3, 2 is a condition output section (data latch 48), 4 is a state output section (input latch 52, comparator 50, 200 to 220 of the processing flow in FIG. Input / output interface 22), 6 is a condition specifying unit (flag FLG set in floppy disk 18), 8 is updating means (CPU 12), 10 is condition specifying means (CPU 12, floppy disk 18, digital input / output interface 22) ) And 12 are test control means (110 to 124 in the processing flow of FIG. 4 in the CPU 12 and the floppy disk 18).

Claims (1)

(57) [Claims] A condition output unit for transmitting test conditions; a test data output unit for transmitting test data to the device under test together with the test conditions transmitted from the condition output unit; A state output unit that outputs information indicating a state of the device under test with respect to a test condition; a condition specifying unit that specifies a test condition; an updating unit that updates the specification of the test condition; Condition setting means for setting, and test control means, wherein the test control means converts the test condition specified by the condition specifying unit to the test condition specified by the specification via the condition setting means. When the test is set to the condition output unit at the start of the period, and test data corresponding to the set test condition is supplied from the test data output unit to the device under test, or the test condition according to the designation For Each time an output of the state output unit occurs within the period, the same test condition as the test condition set in the condition output unit at the start of the test is reset in the condition output unit, and the reset test condition When the corresponding test data is supplied from the test data output unit to the device under test, information indicating an abnormal state of the device under test generated for any of the settings is output to the state output unit. A test apparatus for causing an update by the update unit immediately after a period for a test condition set in the condition specifying unit elapses.