JPH06149310A - Digital input device - Google Patents

Abstract

PURPOSE:To improve the over all throughput of a digital input device by setting the detecting functions independently of the bit unit of an input signal for the state changes of the input signal into a low level from a high level and vice versa and for the no change of the input signal. CONSTITUTION:The state changes of the external digital input signals D10-31 are detected to carry out the prescribed logical decision after a signal C7 of a logical cyclic scan counter 1 is set at a high level. Thus the change is decided for the checked external digital input signal. Then the counter 1 produces a write signal through a WE pin and updates the state of the corresponding external digital input signal DIn of a state holding memory 3. In such a way, the signals D10-31 are successively scanned and the old data stored in the memory 3 are compared with the present data. The result of this comparison is sent to a CPU. These operations are repeated so that the state change of the input signal is carried out at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital device for detecting a state change of an input signal in order to perform sequence control by detecting movement and movement of an object in mechatronics, FA or physical distribution, position control, number measurement and the like. Regarding the input device.

[0002]

2. Description of the Related Art The movement or movement of the above-mentioned object is detected by a sensor or the like, and this detection signal is supplied as an on / off signal of a contact or a level signal of an electric signal to an external control computer, a sequence controller or the like. Then, a control computer or a sequence controller senses a change in an external signal to perform sequence control.

Conventionally, signal change detection is performed by software in which an external signal is arbitrarily input as a digital input signal, is input again after a lapse of a certain time, and bit differences are processed by a program for the difference between the states of the previous input signal and the current input signal. Is going.

As a hardware method, FIG.
As shown in (a), the external signals D _n , D _{n + 1} , D _{n + 2.}
.. are delayed by the shift registers 51, 52, 53, ... And then supplied to the exclusive OR circuits 61, 62, 63 .., and the changing edges are detected as shown in FIG. 2B. There is a way.

[0005]

In the conventional method described above, in the soft detection method, in the industrial field of a line in which an object flows at high speed, the soft processing of the control computer or the sequence controller causes the line change. There is a problem that it cannot be used because it cannot follow the speed. This is because a general CPU is not good at bit processing and spends a great deal of time on change detection when the number of external input points is large.

Further, as shown in FIG. 2, the hardware method is to detect the state change point of the external input signal by the exclusive OR circuit and notify the CPU of the change edge by an interrupt or the like. Assuming that a plurality of bits change simultaneously, it is necessary to provide an interrupt priority determination circuit for the CPU.

Further, as the system becomes larger and the number of external input points increases, the desired detection edge becomes different for each bit and it becomes impossible to unify. That is, it is difficult to independently assign the four items of the input signal from off to on, from on to off, both on / off, and without change edge detection, and as a result, this determination is left to the CPU software processing. And the CPU's processing capacity is tightened,
There is a problem that the processing function of the entire device is degraded.

The present invention has been made in view of the above,
It is an object of the present invention to provide a digital input device capable of surely and flexibly detecting a change in an input signal, determining a bit, determining a change edge, and transmitting to a CPU.

[0009]

In order to achieve the above object, a digital input device of the present invention is a digital input device for detecting a change in the state of an input signal, the state of the input signal from a high level to a low level. Change detection function, state change detection function from low level to high level of input signal, state change detection function of input signal to low level or high level, no change detection function of input signal bit unit of input signal It is a gist to have a logical cyclic scan counter, a selector, and a state holding memory configured to be set independently.

[0010]

In the digital input device of the present invention, the function of detecting the change of the input signal from the high level to the low level, the function of detecting the change of the input signal from the low level to the high level, and the function of detecting the low and high levels of the input signal The state change detection function and the input signal non-change detection function can be set independently for each bit of the input signal.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a digital input device according to an embodiment of the present invention. The digital input device shown in FIG. 1 is a 32-bit digital type composed of a logical cyclic scan counter 1, a state holding memory 3, a detection method selection memory 4, an interrupt output section 5, a selector 7, a data buffer 9 and an AND circuit 11. It is an input device. Further, the digital input device is provided with a data signal XD0 to 15 and an address signal XA from a CPU (not shown).
0, 1, reset signal RST, clock signal CLK, interrupt response signal ACK, code read signals CDRD, DI
The read signal DTRD is supplied and the interrupt output signal IRP is supplied to the CPU. The digital input device shown in the figure is supplied with 32-bit external digital input signals DI0-31.

The logic type cyclic scanning counter 1 is a counter composed of 8 bits of counter C output signals C0 to C7 which are all reset to a low level by a reset signal RST supplied from the CPU, and inputs FUL and OD.
I, R0 to R3, D0 to D3, RST, CLK,
It has NDI, WE, and C0 to C7 as outputs and constitutes a state mine composed of the following logical expressions.

[0014]

[Equation 1]

[0015]

[Equation 2]

[0016]

[Equation 3]

The detection method selection memory 4 is shown in Table 1 below.
The truth value tables 1 and 2 shown in Tables 1 and 2 operate, and the selector 7 performs the operation shown in truth table 3 shown in Table 3 below. Further, Table 4 shown below shows the operation of the relevant part executed by the logical cyclic scanning counter 1.

[0018]

[Table 1]

[0019]

[Table 2]

[0020]

[Table 3]

[0021]

[Table 4]

In FIG. 1, a logical cyclic scanning counter 1
Is reset by the reset signal RST, and after the reset signal RST is released, the initial value data is written in the state holding memory 3 as shown in Table 4 while performing the counting operation by the clock signal CLK, initialize.

This data is the external digital input signals DI0 to 31 at that time. Any one of the D0 to 3 signals is selected and output from the NDI pin of the logic type cyclic scanning counter 1 for writing to the state holding memory 3. This is selected by the C2 to 3 signals inside the logic type cyclic scanning counter 1. The D0 to 3 signals are the C4 to 6 signals and the external digital input signal DI0 selected by the selector 7.
4 points out of 31 and the ones selected by the truth table 3 are presented. Further, C2 to 6 are used as address signals of the state holding memory 3 and specify addresses for storing the states of the external digital input signals DI0 to 31. Further, a write signal is output from the WE pin of the logical cyclic scan counter 1 and the write operation to the state holding memory 3 is executed. Although the WE pin is also connected to the interrupt output unit 5, the C7 signal is still at a low level at this point and this is the reset signal for the interrupt output unit 5, so Has no effect.

When the initialization of the state-holding memory 3 is completed in this manner, the state-holding memory 3 is filled with 32-bit data, and the data stored here is treated as the old external digital input signal DI _n .

When the initialization of the state holding memory 3 is completed,
The C7 signal of the logical cyclic scanning counter 1 becomes high level, and thereafter, this signal does not become low level unless it is reset.

Next, after the C7 signal of the logic type cyclic scanning counter 1 becomes high level, the external digital input signal DI
When the state change detection of 0 to 31 is performed and C1, C0 = L, L as shown in Table 4, (NDI _n & / ODI _n & +
E _n ) is logically determined, and C1 and C0 =
At the time of L and H, the determination of (/ NDI _n & DI _n & −E _n ) is performed.

Here, NDI _n is the current new external digital input signal DI _n (new DI _n ) input from the D0 to 3 pins, and ODI _n is the past external digital input signal DI input from the ODI _n pin. _n (old DI
_n ). E _n is the detected edge designated condition input from R0 to 3 pins.

The above-mentioned (NDI _n & / ODI _n & +
E _n ) = 1 or (/ NDI _n & DI _n & -E _n ) = 1
If it is determined that the checked external digital input signal has changed, the logical cyclic scanning counter 1 issues a write signal from the WE pin, and the corresponding external digital input signal DI _{n of the} state holding memory 3 is output. Update the status of. This corresponding address is C2 ...
Specified by C6 signal.

Further, at this time, the write signal writes the state of the C6-2 signal to the interrupt output unit 5. The interrupt output unit 5 is a register composed of 6 + 1 bits, and the written C6 to 2 represent code information of change bits. For example, in the case of C6-2 = L, L, L, L, D
It is determined that I0 has changed. Similarly, C6-2 =
In the case of H, L, H, H, it means that the DI11 signal has changed. Immediately after writing to the interrupt output unit 5, the interrupt output unit 5 issues an interrupt output signal IRP, and this signal is transmitted as an interrupt input of the CPU.

After issuing the interrupt output signal IRP, the logical cyclic scanning counter 1 outputs the interrupt output signal IRP to F
Input to the UL pin to stop the counter operation. When the CPU reads the code information output from the interrupt output unit 5 in response to the interrupt input and then outputs the interrupt response signal ACK, the interrupt output signal IRP is reset,
After that, the counter operation of the logical cyclic scanning counter 1 is restarted.

When the interrupt output unit 5 has a multi-stage register structure such as a FIFO, the counter operation is not stopped until the data writing in the register becomes full. In this case, although not disclosed, the buffer full signal from the interrupt output unit 5 is input to the FUL pin.

Further, the above logical expression is (NDI _n & / O
DI _n & + E _n ) = 0 or (/ NDI _n & DI _n & −
If E _n ) = 0 is not satisfied, the logical cyclic scanning counter 1 does not issue a write signal from the WE pin, and skips (jumps) the write operation of the state holding memory 3 and the interrupt output unit 5.

Next, edge detection data is written in the detection method selection memory 4 by the CPU in the format shown in the truth table 1. Here, + E23- + E0 and -E23--
The number E0 corresponds to the external digital input signals DI31-0. If the data of + E23 to + E0 is "1", "+ edge detection" is permitted, and similarly -E23 to -E.
If E0 is "1", "-edge detection" is permitted, but if it is "0", the changing edge is not detected.
The truth table 2 shows the output order of the edge selection data when the logical cyclic scan counter 1 reads the detection method selection memory 4.

For example, + E0, + E1, + E2, + E3
= 1,0,1,0, -E0, -E1, -E2, -E3
= 0,1,1,0, external digital input signal D
I0 is + edge detection, external digital input signal DI1 is −edge detection, external digital input signal DI2 is ± edge detection, and external digital input signal DI3 is no edge detection. Therefore, the external digital input signals DI0 to 31
The detection method can be specified independently for each bit unit.

The logical type cyclic scan counter 1 is different from a simple counter in that it is a cyclic scan counter having a logical function, and a sequencer having a function of skipping (jumping) depending on the result of the condition judgment and a halt function of looping. There is. The condition judgment is a part of the numbers 1 and 2 in which the external digital input signals DI0 to 31 are respectively executed as shown in Table 4.

The skip destination is number 1 → number 3, number 2 → number 1 (number 1 in the n + 1 portion), and last number 3 (n
= 31) → the first number 1 (n = 0), and the loop is executed with the number 3 respectively. Conditions are satisfied for skip and loop /
These operations and the functions described above are executed by the logical cyclic scan counter 1 according to the result of failure.

As described above, the present digital input device sequentially scans the external digital input signals DI0 to DI31,
The old data and the current data stored in the state-holding memory 3 are compared, the judgment is made and the result is transmitted to the CPU, and this is repeated. The data buffer 9 is free to the external digital input signal DI0 to the CPU regardless of the change detection.
It is a buffer for I / O port that reads ~ 31. If the C6 signal is ignored and the signal is disconnected, the device becomes a 16-bit digital input device. Similarly, if C6 and C5 are disconnected, the device can be used as an 8-bit digital input device.

[0038]

As described above, according to the present invention,
The external input signal is scanned, the change is determined, and it is transmitted to the CPU. The CPU executes the selector 7 in the interrupt processing routine.
It is possible to know the changed bit only by reading the code information of, and it is not necessary to spend a lot of time for software processing, and the throughput of the entire device can be improved.
Further, since the change determination is performed at high speed, it is possible to follow a line in which an object flows at high speed and high-speed sequence control such as mechatronics or FA. In addition, the detection method can be set independently for each bit simply by rewriting the data in the detection method selection memory, which is applicable to large systems.
Can flexibly respond to changes and modifications.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a digital input device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a part of a circuit used in a conventional digital input device and an operation waveform.

[Explanation of symbols]

 1 logic type cyclic scanning counter 3 state holding memory 4 detection method selection memory 5 interrupt output section 7 selector 9 data buffer

Claims (1)

[Claims] 1. A digital input device for detecting a state change of an input signal, the function of detecting a state change of an input signal from a high level to a low level, the function of detecting a state change of an input signal from a low level to a high level, Logic type cyclic scan counter, selector, and state holding function configured to set the state change detection function to the low level and the high level of the input signal and the no-change detection function of the input signal independently for each bit of the input signal A digital input device having a memory.