JPH0276040A - Error deciding system - Google Patents

Abstract

PURPOSE:To decide the presence and absence of an error at a high speed by comparing the contents of a buffer storing part and the contents of a shift register in synchronism with shift operation, storing a compared result to a flip-flop, which can be referred from an arithmetic processing unit, and reading the result after the shift operation is completed. CONSTITUTION:By a comparing circuit 6 to be connected to a data transfer pass 11, which is between a buffer storing part 2 and a shift register 4, through a switch 5, the contents of the buffer storing part 2 and the contents of the shift register 4 are compared in synchronism with the shift operation. The compared result is stored to a flip-flop 7, which can be referred from an arithmetic processing unit 1, and the condition of the flip-flop 7 is read by the arithmetic processing unit 1 after the shift operation is completed. Thus, the presence and absence of error information, which are dispersed in the latch group of an LSI, can be decided at the high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for determining error content in a data processing device.

[Prior Art] FIG. 4 is a block diagram showing hardware for reading and writing from a conventional service processor to a group of latches in an LSI. In the figure, 1 is an arithmetic processing unit that controls a service processor 12 (described later), 2 is a buffer storage unit for holding write data from the arithmetic processing unit 1 in advance, and 3 is an address register that holds the access address of the buffer storage unit 2. , 9 and IO are LSIs (large scale integrated circuits), 4 is a shift register that holds shift data from LSIs 9 and 10 by a fixed bit width, 12 is a service processor, 11 is a data path within the service processor 12, 13 is an LSIQ A latch group 14 within is a shift path for supplying data in the shift register 4 to a latch group 13 in the LSIQ.

FIG. 5 is a diagram showing the timing of each part during operation in the conventional example shown in FIG.

Next, the operation of the above conventional example will be explained. First, from the service processor 12 to the LSI 9 and lO latch group 1
The case where the value is set to 3 will be described. The arithmetic processing unit 1 of the service processor 12 writes all data to be set in the latch group 13 to the buffer storage section 2. The write address is sequentially sent to the arithmetic processing unit 1 by the address register 3.
It is set via the data path 11 from . After completing data accumulation in the buffer storage section 2, the arithmetic processing device 1 starts a shift operation. This shift operation is performed automatically and at high speed while the shift register 4 takes in the write data from the buffer storage section 2.

FIG. 5 shows the timing of each part during the operation of the conventional example as described above. The address register 3 is set by the increment clock prior to the shift clock “1”.
The new write data Do is read out from the buffer storage section 2 and set in the shift register 4 at the same time. The mode of the shift register 4 is switched to parallel set mode during this timing. Next, after setting the mode of the shift register 4 to shift mode, a shift clock corresponding to 8 bits of the bit length of the shift register 4 is generated.

As mentioned above, the contents of shift register 4 are shift path 1
4 to the latch group 13 in the LSIQ. After the 8-bit shift is completed, the mode of the shift register 4 is switched to parallel set mode again and an increment clock is generated, thereby loading new 8-bit data in the buffer storage section 2 into the shift register 4.

Conversely, when reading the data of the latch group 13 in LSre into the buffer storage unit 2, after the shift by the shift clock is completed, the contents of the shift register 4 are read into the buffer storage unit 2 at +1 timing of the address register 3 by the increment clock. write to.

The above hardware allows the service processor 12 to freely read and write the contents of the latch group 13 within the LSIe. Utilizing this function, the conventional service processor 12 reads error information in the LSIs 9 and 10, and the arithmetic processing unit 1 determines the error.

[Problems to be Solved by the Invention] Since the conventional service processor 12 is configured as described above, the large latch group 1 of the LSI 9 and IO is
In order to check the error information scattered in the latch group 13, the arithmetic processing unit 1 has to access the contents of the buffer storage unit 2 many times, and therefore determines the presence or absence of error information in the latch group 13. However, there was a problem in that error determination required a long time.

This invention was made to solve the above-mentioned problems, and aims to provide an error determination method that can quickly determine the presence or absence of error information scattered within a group of LSI latches. purpose.

[Means for Solving the Problems] The error determination method according to the present invention uses a comparison circuit connected to both ends of a switch provided in a data transfer path between the buffer storage unit and the shift register to compare the contents of the buffer storage unit and the shift register. By comparing the contents of the register with the contents of the register in synchronization with the shift operation, storing the comparison result in the flip-flop, and reading the state of the flip-flop with the arithmetic processing unit after the shift operation is completed, the latch group in the LSI is This makes it possible to determine whether a specific error has occurred.

[Operation] The error determination method according to the present invention synchronizes the contents of the buffer storage section and the contents of the shift register with the shift operation using a comparison circuit connected to the data transfer path between the buffer storage section and the shift register via a switch. and compare
The comparison result is stored in a flip-flop that can be referenced by the arithmetic processing unit, and after the shift operation is completed, the arithmetic processing unit reads the state of the flip-flop, thereby providing error information scattered within the latch group of the LSI. It is possible to quickly determine the presence or absence of

[Embodiment] FIG. 1 is a block diagram showing hardware for reading and writing from a service processor to a group of latches in an LSI using an error determination method according to an embodiment of the present invention.
The same reference numerals as in the figures indicate the same or corresponding parts, and detailed explanation thereof will be omitted. In the figure, 5 is a switch provided on the data transfer path between the buffer storage unit 2 and the shift register 4 to separate data transfer between the two, and 6 is a switch that shifts the contents of the buffer storage unit 2 and the shift register 4. A comparison circuit that compares in synchronization with the operation; 7 is a flip-flop that stores the comparison result of the comparison circuit 6; 8 is a flip-flop that sends the contents of the flip-flop 7 to the data path 11, takes in reset data from the data path 11, and stores the comparison result of the comparison circuit 6; This is a buffer 7 register for resetting the buffer 7.

FIG. 2 is a diagram showing the timing of each part during operation in the embodiment of the invention shown in FIG.

Next, the operation of the above embodiment of the present invention will be explained.

Normally, the switch 5 is closed (connected) so that the data in the buffer storage section 2 can be supplied to the shift register 4 and the contents of the shift register 4 can be written into the buffer storage 2 as in the conventional example. do.

Here, if the service processor 12 determines that even one of the several bits of error information scattered within the latch group 13 is "l",
When attempting to determine whether or not a serious error has occurred, the arithmetic processing unit 1 first writes a comparison pattern serving as comparison data into the buffer storage unit 2. Next, the arithmetic processing unit 1 resets the flip-flop 7 using the buffer register 8, and releases the switch 5 rWI to disconnect the data transfer path between the buffer storage section 2 and the shift register 4.

In the above state, the buffer storage unit 2 performs a write operation to the latch group 13, and the shift register 4 performs a read operation from the latch group 13. As a result, the comparison pattern is inputted to the comparison circuit 6 from the buffer storage section 2, the read data of the latch group 13 is inputted from the shift register 4, and the comparison result by the comparison circuit 6 is stored in the flip-flop 7.

FIG. 2 shows the timing of each part during operation of the embodiment of the present invention as described above. After applying the shift clock to the shift register 4 eight times, the mode of the shift register 4 remains in shift and an increment clock is generated. As a result, the contents of address register 3 become +
1 and new comparison data is read from the buffer storage section 2.

By applying a clock to the flip-flop 7 at this timing, the flip-flop 7 can store the comparison result from the comparison circuit 6.

The clock to flip-flop 7 is the shift clock 8.
Since the signal is generated only up to a gap of one clock after the signal is generated, the flip-flop 7 will not accidentally pick up the result of comparison with the data being shifted.

Furthermore, since the shift mode is shifted, the shift register 4 will not accidentally destroy the held data at the timing of the increment clock generation.

FIGS. 3(a) and 3(b) are diagrams showing the configuration of the comparator circuit and data examples of the latch group in the embodiment of the invention shown in FIG. As shown in the figure, the comparator circuit 6 has an AND gate 15
and an OR gate 16. The comparison pattern input from the buffer storage unit 2 to the comparison circuit 6 acts as a mask pattern for the data in the latch group 13 from the shift register 4, and has "1" only in bit positions necessary for error determination. The comparison circuit 6 uses an AND game (AND game) 15 to logically AND the comparison pattern from the buffer storage section 2 and the data of the latch group 13 from the shift register 4, thereby determining the latch group 1 corresponding to "l" of the comparison pattern.
Only the error information in the data in step 3 is extracted. Next, the comparator circuit 6 performs an OR game (OR game)1 on all the extracted error information.
By performing a logical sum using 6, an output signal to the flip-flop 7 is obtained. The flip-flop 7 further performs a logical sum on the output signal with the previous comparison result and stores the result. By repeating the above operations until the latch group 13 is completely shifted, desired error information can be read by the arithmetic processing unit 1 through the buffer register 8.

Although the above embodiment shows a configuration in which the normally used buffer storage section 2 is used as a storage buffer for the comparison pattern manually inputted to the comparison circuit 6, a buffer storage section exclusively for the comparison pattern is separately provided, and the switch 5 may be omitted, and it is also possible to read the contents of the latch group 13 into the buffer storage section 2 at the same time.

Furthermore, in the above embodiment, by providing a plurality of buffer storage unit 2° comparison circuits 6 and flip-flops 7, it goes without saying that a plurality of error determinations can be made simultaneously. [Effects of the Invention] As described above, according to the error determination method of the present invention, the contents of the buffer storage section and the shift The contents of the register are compared in synchronization with the shift operation, the comparison result is stored in a flip-flop that can be referenced by the arithmetic processing unit, and the state of the flip-flop is read by the arithmetic processing unit after the shift operation is completed. Therefore, it is possible to quickly determine the presence or absence of error information scattered within the latch group of an LSI, and furthermore, the device can be realized at a low cost, which is an excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing hardware for reading and writing from a service processor to a group of latches in an LSI using an error determination method according to an embodiment of the present invention, and FIG. 2 is an implementation of the present invention shown in FIG. 3(a) and (b) are diagrams showing the configuration of the comparison circuit and data example of the latch group in the embodiment of the present invention in FIG. 1, and FIG. 4 shows the timing of each part during operation in the example. 5 is a block diagram showing hardware for reading and writing a latch group in an LSI from a conventional service processor, and FIG. 5 is a diagram showing the timing of each part during operation in the conventional example of FIG. In the figure, 1... Arithmetic processing unit, 2... Buffer storage section, 3... Address register, 4... Shift register, 5... Switch, 6... Comparison circuit, 7...
・Flip-flop, 8...Buffer register, 9,
10...LSI, 11...Data path, 12...
Service processor, 13... Latch group, 14...
Shift pass, 15...AND gate, 16...OR
...It's a gate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A shift register for serially reading and writing a group of latches in the LSI, a buffer storage section that sequentially supplies data to this shift register, and an address of this buffer storage section that changes in synchronization with the shifting operation of the latch group. In a service processor equipped with an address register, a switch is provided in the data transfer path between the buffer storage section and the shift register, a comparison circuit connected to both ends of the switch, and a flip-flop that stores the comparison result of the comparison circuit. By providing an arithmetic processing unit that controls the service processor to perform operations such as determining and resetting the contents of this flip-flop, the comparison circuit compares the contents of the buffer storage section with the contents of the shift register. An error determination method characterized in that the presence or absence of error information in the latch group is determined by comparing in synchronization with the shift operation of the latch group.