JPH0614332A - Digital matrix circuit - Google Patents

Abstract

PURPOSE:To simplify a digital matrix circuit(DMC), to provide the DMC with a multifunction and to share the DMC for various synthetic chrominance signals by obtaining plural kinds of synthetic chrominance signals by one DMC. CONSTITUTION:The DMC is provided with plural switch circuits 131 to 133 for switching matrix constants, the operation of the circuits 131 to 133 is controlled by an external control signal and the weighted addition of plural input chrominance signals is executed to selectively output plural kinds of synthetic chrominance signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital matrix circuit for digitally synthesizing a plurality of input color signals to form another color signal, and in particular, outputting a plurality of output color signals by designating them with an external control signal. The present invention relates to an enabled digital matrix circuit.

[0002]

[Prior art]

Generally, in order to form a color television signal of, for example, an NTSC system from an image pickup output obtained by a color television camera, as shown in FIG. 7, for the three primary color signals given as the image pickup output, first to third color signals are provided. Luminance signal E _Y and two color signals E _I and E _Q are created by performing predetermined weighted addition and synthesis by the third matrix circuits 1, 2 and 3, and the above E _Y ,
Encoding according to the NTSC system is performed using three signals of E _I and E _Q.

In the NTSC system, the three primary color signals are a red color signal E _R , a green color signal E _G , and a blue color signal E _B.

E _Y = 0.30E _R + 0.59E _G + 0.11E _B・ ・ ・ First formula

The luminance signal E _Y can be expressed by the following first equation. The color signals E _I and E _Q can be expressed by the following second and third equations.

E _I = 0.74 (E _R −E _Y ) −0.27 (E _B −E _Y ) = 0.60E _R −0.28E _G −0.32E _B

[0008] _{E Q = 0.48 (E R -E} Y) -0.41 (E B -E Y) = 0.21E R -0.52E G + 0.41E B ··· third expression

When the signals E _Y , E _I , and E _Q are combined by digital processing,

[0010]

[Equation 1]

By setting the matrix elements of the determinant shown in the fourth equation as shown in Table 1, for example,

[0012]

[Table 1]

[0013]

[Equation 2]

[0014]

[Equation 3]

[0015]

[Equation 4]

It suffices to perform the digital addition operations of the following equations 5, 6, and 7.

[0017]

By the way, in the conventional digital matrix circuit, the first digital matrix circuit for performing the digital operation of the fifth equation and synthesizing the E _Y signal and the digital operation for the sixth equation are performed. Since the second digital matrix circuit for synthesizing the E _I signal and the third digital matrix circuit for synthesizing the E _Q signal by performing the digital operation of the seventh equation are individually configured, the _EY signal It required three types of integrated circuits: dedicated, dedicated for E _I signals, and dedicated for E _Q signals.

In view of the above-mentioned problems, the present invention intends to simplify the digital matrix circuit and increase the number of functions by making it possible to obtain a plurality of types of composite color signals with a single digital matrix circuit. At the same time, it is intended to standardize the digital matrix circuit for various kinds of composite color signals.

[0019]

In order to solve the above problems, the present invention provides a plurality of matrix constants for switching matrix constants in a digital matrix circuit which performs weighted addition of a plurality of input color signals to form another color signal. A switch circuit is provided, and the operation of the switch circuit is controlled by an external control signal to selectively output a plurality of types of composite color signals.

[0020]

In the digital matrix circuit according to the present invention,
Switch matrix constants with multiple switch circuits,
Weighted addition is performed on a plurality of input color signals, and a plurality of types of composite color signals are selectively output.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 showing a first embodiment of a digital matrix circuit according to the present invention, the first to third signal input terminals 11, 12 and 13 have three primary colors obtained by a color television camera (not shown). Signals E _R , E _G , E
_B is digitized by analog / digital processing, and is supplied as a digital signal indicating each signal level by, for example, an 8-bit BCD code.

The digital matrix circuit 10 of the first embodiment has thirteen multiplication circuits 101, 102, 103,
104, 105, 106, 107, 108, 109, 1
10, 111, 112, 113 and 5 adder circuits 12
1, 122, 123, 124, 125 and three switch circuits 1 that perform switching operation according to the logical value of the external control signal CTL supplied to the external control signal input terminal (not shown).
It is provided with 31, 132, 133 and is configured as follows.

That is, the first signal input terminal 11 includes a first multiplication circuit 101 having a multiplier of "16", a second multiplication circuit 102 having a multiplier of "2", and a third multiplication circuit having a multiplier of "1". 1
It is connected to 03. The first to third multiplication circuits 101, 102, 103 supply each multiplication output to the first addition circuit 121. Here, a first switch circuit 131 is provided between the second multiplication circuit 102 and the first addition circuit 121, and the multiplication output from the second multiplication circuit 102 is the first switch circuit. It is adapted to be supplied to the first adder circuit 121 via 131.

The opening / closing operation of the first switch circuit 131 is controlled by an external control signal CTL, and when the external control signal CTL is logic "1", the first switch circuit 131 is in a closed state and the multiplication output by the second multiplication circuit 102 is output. Is supplied to the first adder circuit 121, and the external control signal CTL is logic "0".
At this time, the open state is established and the supply of the multiplication output from the second multiplication circuit 102 to the first addition circuit 121 is prohibited.

The second signal input terminal 12 is connected to the fourth multiplication circuit 104 having a multiplier of "8" and the fifth multiplication circuit 105 having a multiplier of "2". The fourth and fifth multiplying circuits 104 and 105 supply the respective multiplication outputs to the second adding circuit 122. This second adder circuit 122
Outputs the addition output thereof to the sixth multiplication circuit 10 whose multiplier is "-1".
It is supplied to the third adder circuit 123 via 6. The third addition circuit 123 is supplied with the addition output from the first addition circuit 121, and the addition output is supplied to the seventh multiplication circuit 107 having a multiplier of “1” and the multiplier “−”.
1 ”and the eighth multiplication circuit 108.

Further, the third signal input terminal 13 is
It is connected to the ninth multiplication circuit 109 having a multiplier of “8”, the tenth multiplication circuit 110 having a multiplier of “1”, and the eleventh multiplication circuit 111 having a multiplier of “−1”. Above 9th to 11th
The multiplication circuits 109, 110, and 111 of the above supply the respective multiplication outputs to the fourth addition circuit 124. Here, the first
A second switch circuit 132 is provided between the 0 and 11th multiplication circuits 110 and 111 and the fourth addition circuit 124, and each multiplication output is selected by the second switch circuit 132 to select the first output. 4 to the adder circuit 124.

The second switch circuit 132 is controlled to open / close by an external control signal CTL. When the external control signal CTL is logic "0", the tenth multiplication circuit 1 is operated.
The multiplication output by 10 is supplied to the fourth addition circuit 124,
Further, when the external control signal CTL is logic “1”, the multiplication output from the eleventh multiplication circuit 111 is supplied to the fourth addition circuit 124.

Then, the fourth adder circuit 124 outputs the added output to the twelfth multiplier circuit 112 whose multiplier is "-1".
Is supplied to the fifth adder circuit 125 via. Further, the multiplication outputs of the seventh and eighth multiplication circuits 107 and 108 are selectively supplied to the fifth addition circuit 125 via the third switch circuit 123.

The opening / closing operation of the third switch circuit 123 is controlled by the external control signal CTL, and the seventh multiplication circuit 1 is operated when the external control signal CTL is logic "0".
The multiplication output by 07 is supplied to the fifth addition circuit 125,
Further, when the external control signal CTL is logic “1”, the multiplication output from the eighth multiplication circuit 108 is supplied to the fifth addition circuit 124.

Then, the fifth adder circuit 125 outputs the added output to the thirteenth multiplier circuit 1 whose multiplier is "1/32".
The signal is output from the signal output terminal 15 via 13.

In the first embodiment having the above-mentioned structure, the E _R signal is supplied to the first signal input terminal 11 and the second signal is supplied to the second signal input terminal 11.
The E _B signal is supplied to the signal input terminal 12 of the
The E _G signal is supplied to the signal input terminal 13 of the
By designating the operation of the first to third switch circuits 131, 132, 133 by the external control signal CTL, the E _I signal in the NTSC system is output at the signal output terminal 15
Can be obtained.

That is, when the external control signal CTL is logic "0", the first addition circuit 121 obtains an addition output of (16 + 2 + 1) · E _R , and the fifth addition circuit 125 has the third switch. From the seventh multiplication circuit 107 via the circuit 133 to (16 + 2 + 1) · E _R −
The multiplication output of (8 + 2) .E _B is supplied. Further, the fourth addition circuit 124 obtains an addition output of (8 + 1) · E _G , and the fifth addition circuit 125 is supplied with the multiplication output of − (8 + 1) · E _G from the twelfth multiplication circuit 112. To be done. Therefore, in the fifth adder circuit 125, (1
6 + 2 + 1) · E R - (8 + 1) · E G - (8 + 2) ·
An addition output of E _B is obtained and is output to the signal output terminal 15 via the thirteenth multiplication circuit 113.

[0034]

[Equation 5]

It is possible to obtain the E _I signal represented by the following Eq.

Further, in the above-described first embodiment, the first
Of the logic "1" by supplying the E _G signal to the signal input terminal 11 of the above, supplying the E _B signal to the second signal input terminal 12 and further supplying the E _R signal to the third signal input terminal 13. Switch circuits 131, 132,
Can be obtained E _Q signal in the NTSC system to the signal output terminal 15 by performing the operation specified 133.

That is, the external control signal CTL is logical
When it is “1”, the first adder circuit 121
(16 + 1) ・ E_GAnd the fifth addition is obtained.
The circuit 125 is connected to the eighth switch via the third switch circuit 133.
From the multiplication circuit 108 of − (16-1) · E_G+ (8+
2) ・ E_BIs provided. Also, the fourth addition
(8-2) · E by the arithmetic circuit 124_RThe addition output becomes
The twelfth multiplication circuit 11 is added to the fifth addition circuit 125.
Through 2-(8-1) · E_RIs supplied with the multiplication output
It Therefore, in the fifth addition circuit 125,-(8-1)
E_R-(16-1) ・ E _G+ (8 + 2) ・ E_BBecomes
An output is obtained and a signal is output via the thirteenth multiplication circuit 113.
To the force terminal 15

[0038]

[Equation 6]

[0039] becomes E _Q signal indicated at 9 is obtained.

That is, in the above-mentioned first embodiment,

[0041]

[Equation 7]

Matrix operation represented by the following tenth expression
To perform E in the NTSC system. _ISignal or E
_QSignals are selectively specified by the external control signal CTL and output
can do. Therefore, in the above-mentioned first embodiment
The digital matrix circuit 10 is_ISignal and E_QSignal
Integrated circuit as a common component for forming
You can

Next, in FIG. 2 showing a second embodiment of the digital matrix circuit according to the present invention, 21 is a first signal input terminal to which an E _R signal is supplied, and 22 is an E _G signal. Is a second signal input terminal to which is supplied, and 23 is a third signal input terminal to which an _EB signal is supplied. The E _R signal, the E _G signal, and the E _B signal are digital signals that indicate the signal levels of the three primary color signals by digital codes, respectively, as in the first embodiment, and the sub-carrier frequency f _SC of 4 It is assumed to have a double clock frequency 4f _SC .

The digital matrix circuit 20 of the second embodiment has 16 multiplication circuits 201, 202, 203,
204, 205, 206, 207, 208, 209, 2
10, 211, 212, 213, 214, 215, 21
6 and 7 adder circuits 221, 222, 223, 22
4, 225, 226, 227, and two switch circuits 231 and 2 that perform a switching operation according to the logical value of the external control signal CTL supplied to an external control signal input terminal (not shown).
32, and is configured as follows.

That is, the first signal input terminal 21 has the first
It is connected to the adder circuit 221 is, the first through E _R signal the first signal input terminal 21 of the adder circuit 22
1 is supplied. The second signal input terminal 22 has a multiplier of “−1” for each of the first and second multiplication circuits 20.
1, 202 and the multiplier 32 are connected to the third multiplication circuit 203, and the E _G signal is connected to the second signal input terminal 2
2 through the first to third multiplication circuits 201, 20
2,203. Further, the third signal input terminal 23 is connected to the second adder circuit 222, and E
_{The B} signal is transmitted to the second signal through the third signal input terminal 23.
Is supplied to the adding circuit 222.

The first multiplication circuit 201 supplies the multiplication output to the first addition circuit 221. Then, the first addition circuit 221 obtains an addition output of E _R −E _{G, and} a fourth multiplication circuit 204 having a multiplier of “8”, a fifth multiplication circuit 205 having a multiplier of “2”, and a multiplier. Is the sixth multiplication circuit 206 having a multiplier of “16”, the seventh multiplication circuit 207 having a multiplier of “−1”, the eighth multiplication circuit 208 having a multiplier of “4”, and the ninth multiplication circuit having a multiplier of “−8”. The addition output is supplied to the circuit 209.

Further, the second multiplication circuit 202 supplies the multiplication output to the second addition circuit 222.
Then, the second addition circuit 222 obtains an addition output of E _B −E _G , and the tenth multiplication circuit 21 having a multiplier of “4”.
The addition output is supplied to the eleventh multiplication circuit 211 having a multiplier of “8” and 0 and the twelfth multiplication circuit 212 having a multiplier of “2”.

The third multiplication circuit 203 supplies the multiplication output to the third addition circuit 223. The fourth and fifth multiplying circuits 204 and 205 supply the respective multiplication outputs to the fourth adding circuit 224. The fourth adder circuit 224 obtains an adder output of (8 + 2)  (E _R −E _G ), and outputs this adder output to the third adder circuit 223.
Supply to. Further, the third adder circuit 223 is supplied with the multiplication output from the tenth multiplier circuit 210, and is 32 · E _G + (8 + 2) · (E _R −E _G ) + 4 ·.
An addition output of (E _B −E _G ) is obtained, and the addition output is output from the first signal output terminal 25 via the thirteenth multiplication circuit 213 having a multiplier of “1/32”.

That is, in the second embodiment, the first signal output terminal 25 has

[0050]

[Equation 8]

NTSC represented in the color difference format of the 11th equation
The luminance signal E _Y in the method is obtained.

The sixth to ninth multiplication circuits 20 are also provided.
6, 207, 208, and 209 supply the respective multiplication outputs to the fifth addition circuit 225. Here, the eighth and ninth multiplication circuits 208 and 209 and the fifth addition circuit 225
And a first switch circuit 231 is provided between the first and second switch circuits 231 and 231 and each of the multiplication outputs of the eighth and ninth multiplication circuits 208 and 209 selectively outputs the fifth switch circuit 231 via the first switch circuit 231.
Are supplied to the adder circuit 225.

Further, the eleventh and twelfth multiplication circuits 211 and 212 output the respective multiplication outputs by the sixth addition circuit 226.
Is being supplied to. The sixth adder circuit 226 is (8+
2) · (E _R −E _G ), and the addition output is supplied to the 14th multiplication circuit 214 having a multiplier of “−1” and the 15th multiplication circuit 215 having a multiplier of “1”. ing. Then, the 14th and 15th multiplication circuits 214 and 215
Each multiplication output of the 7th is output via the second switch circuit 232.
Are selectively supplied to the adder circuit 227. The seventh addition circuit 227 is supplied with the addition output from the fifth addition circuit 225, and outputs the addition output via the sixteenth multiplication circuit 216 having a multiplier of "1/32" to the second signal. Output from the output terminal 25.

Here, the first and second switch circuits 231 and 232 are controlled so as to interlock with each other according to the logical value of the external control signal CTL, and the external control signal CTL is logical "1". , The first switch circuit 231 selects the eighth multiplication circuit 208 and the second switch circuit 232 selects the fourteenth multiplication circuit 21.
4 is selected, and when the external control signal CTL is logic "0", the first switch circuit 231 selects the ninth multiplication circuit 209 and the second switch circuit 232 selects the fifteenth multiplication circuit. Select circuit 215. Further, the external control signal CTL controls the switching of the first and second switch circuits 231 and 232 at a clock frequency 2f _{SC that is} twice the sub-carrier frequency f _SC in the NTSC system.

Therefore, in the second embodiment, the fifth adder circuit 225 is (16 + 4-1) .multidot. (E _R -E _G ) when the external control signal CTL is logic "1".
Is supplied to the seventh adder circuit 227, and
When the external control signal CTL is logic "0",
The addition output of (16-8-1) · (E _R −E _G ) is supplied to the seventh addition circuit 227. Therefore, the seventh adder circuit 227, when the external control signal CTL is logic “1”, is (16 + 4-1) · (E _R −E _G ) − (8
+2) · (E _B −E _G ), and the addition signal is obtained from the second signal output terminal 26 via the 16th multiplication circuit 216.

[0056]

[Equation 9]

NTSC represented in the color difference format of Equation 12
The E _I signal in the method can be output. Also,
The seventh adder circuit 227 uses the external control signal CTL.
Is a logical "0", (16-8-1). (E _R
−E _G ) + (8 + 2) · (E _B −E _G ), and the addition output is obtained from the second signal output terminal 26 via the sixteenth multiplication circuit 216.

[0058]

[Equation 10]

NTSC expressed in the color difference format of the thirteenth equation
The _EQ signal in the system can be output.

Therefore, in this second embodiment, as shown in FIG. 3, the NTS has a repetition frequency of 2f _SC.
The E _I signal and the E _Q signal in the C system are output alternately from the second signal output terminal 26.

That is, in the digital matrix circuit 20 of the second embodiment having the above-mentioned configuration, the E _Y signal is obtained at the first signal output terminal 25, and the E _I signal and the E signal are obtained at the second signal output terminal 26. You can get the _Q signal. Therefore, the switch circuits 231 and 232 can be dynamically controlled by the external control signal CTL to obtain the dot-sequential color difference signal shown in FIG. 3 to easily form the carrier color signal in the NTSC system, for example.

Here, the multiplier of each multiplication circuit in the above-mentioned first and second embodiments is 2 ⁿ or 1 /
Since it is set to 2 ⁿ , for example, for an 8-bit digital signal, by giving n additional bits of logic “0” below the least significant bit, when n = 0, the multiplier “1”, n = When 2, the multiplier is “2”, when n = 3, the multiplier is “4”, when n = 4, the multiplier is “8”, when n = 5, the multiplier is “16”, and when n = 6, the multiplier is “32”. ], And the multiplication of the multiplier "1/32" can be performed by removing 6 bits from the least significant bit.

Next, a third embodiment shown in FIG. 4 is obtained by simplifying the digital matrix circuit 20 in the second embodiment and applying it to a popular color video camera for home use. Is.

In the third embodiment, the first to third signal input terminals 31, 32 and 33 are digitized with a clock frequency of 4f _SC , as in the second embodiment. The three primary color signals E _R , E _G , and E _B are supplied. The first to third signal input terminals 31, 32,
33 is a general matrix circuit 300 for forming a luminance signal.
This matrix circuit 300 forms a luminance signal E _Y from the above three primary color signals E _R , E _G , and E _B , supplies the luminance signal E _Y to a subtraction circuit 320, and at the same time, outputs a first signal. Output from the output terminal 35.

The second and third signal input terminals 32.33 are connected to the subtraction circuit 320 via the first switch circuit 331 so that the E _R signal and the E _B signal are the first signals. The signal is selectively supplied to the subtraction circuit 320 via the switch circuit 331. The subtraction circuit 320 alternately obtains a subtraction output of E _R −E _{Y and} a subtraction output of E _B −E _Y to obtain a first multiplication circuit 301 having a multiplier of “0.877” and a multiplier of “0. The subtraction output is supplied to the second multiplication circuit 302 of "455". The first and second multiplication circuits 301 and 302 output the respective multiplication outputs to the second output.
The second signal output terminal 36 via the switch circuit 332.
Selectively output from. Here, the first and second switch circuits 331 and 332 are controlled by the external control signal CTL having a clock frequency of 2f _SC supplied to an external control input terminal (not shown).

In the digital matrix circuit 30 of the third embodiment having the above-mentioned structure, the luminance signal E _Y in the NTSC system is obtained at the first signal output terminal 35, and the color difference signal 0.877. (E _R − E _Y ), 0.455
・ (E _B −E _Y ) is 1 / f _{SC at} the second signal output terminal 26
Obtained alternately in cycles.

Next, a CCD (Charge Coupled Device)
An embodiment of a digital matrix circuit according to the present invention, which is applied to a solid-state color video camera using a solid-state image sensor such as the above, when the imager has a relatively small number of picture elements will be described.

In the fourth embodiment shown in FIG. 5, the first to third signal input terminals 51, 52 and 53 have 3f _SC.
The three primary color signals E _R , E _B , and E _G , which have been digitized with the clock frequency of, are supplied.

E above_RThe signal is the first signal input terminal 51.
The multiplier is "r₁Via the first multiplication circuit 501
It is supplied to the first switch circuit 531 having three inputs. Well
E above_BThe signal is a multiplier from the second signal input terminal 52.
Is "b₁Via the second multiplication circuit 502
Is supplied to the switch circuit 531 of
"B₂Through the third multiplication circuit 503
It is supplied to the second switch circuit 532. Furthermore, the above E
_GThe signal has a multiplier “g from the third signal input terminal 53. ₁"
Via the fourth multiplying circuit 504
It is supplied to the circuit 531 and the multiplier is "g.₂"Become
The second switch circuit via the fifth multiplication circuit 505.
532 is supplied.

The first switch circuit 531 has a multiplication output of r ₁ · E _R supplied from the first signal input terminal 51 via the first multiplication circuit 501 and the second signal input terminal. 52 and a multiplication output of b ₁ · E _B supplied through the second multiplication circuit 502, and g ₁ · E _G supplied from the third signal input terminal 53 through the fourth multiplication circuit 504. And the multiplication output are sequentially selected to add circuit 5
Supply to 20. In addition, the second switch circuit 532
From the second signal input terminal 52 to the third multiplication circuit 5
And a multiplication output of b ₂ · E _B supplied through the third signal input terminal 53 and a multiplication output of g ₂ · E _G supplied through the fifth multiplication circuit 505 from the third signal input terminal 53, for example, ground. The logic "0" data supplied from the line are sequentially selected and supplied to the adder circuit 520.

Here, the first and second switch circuits 531 and 532 are sequentially switched in association with each other at a 1 / f _SC cycle by an external control signal CTL supplied to an external control signal input terminal (not shown). Is designed to do.

Then, the adder circuit 520 has the first
And by adding the respective signals sequentially supplied via the second switch circuits 531 and 532,

[0073]

[Equation 11]

The composite color signals C ₁ , C ₂ , C ₃ shown in the fourteenth expression are output from the signal output terminal 55 in a dot-sequential manner.

The composite color signals C ₁ , C ₂ and C ₃ shown in the above fourteenth equation are as shown in the vector diagram of FIG.
For example, the modulation axis of C ₁ is 105 °, the modulation axis of C ₂ is 225
It is possible to provide the primary color three-phase modulated carrier color signal C equivalent to the carrier color signal in the NTSC system by setting the modulation axes of ° and C ₃ to -15 °.

Here, the matrix constants in the above equation 14 are r ₁ = 0.63, g ₁ = 0.63, g ₂ = 0.18, b ₁ = 0.4.
5, b ₂ = 0, the carrier color signal C is

C = C ₁ + C ₂ + C ₃ = 0.63 E _R exp (jω _SC t + 105 °) +0.63 E _G exp (jω _SC t + 225 °) + (0.45E _B + 0.18E _G ) exp (jω _SC t −15 °) ・ ・ ・ Formula 15

It can be represented by the following fifteenth expression.

[0079]

As is apparent from the above description of each embodiment, according to the present invention, matrix constants are switched in a digital matrix circuit for performing weighted addition of a plurality of input color signals to form another color signal. By providing a plurality of switch circuits, controlling the operation of the switch circuits by an external control signal, and selectively outputting a plurality of types of composite color signals, one digital matrix circuit combines a plurality of types of composites. The color signal can be obtained by designating it with an external control signal.

As described above, in the digital matrix circuit according to the present invention, since one digital matrix circuit can specify a plurality of kinds of composite color signals by the external control signal and selectively output them, A digital matrix circuit for color combination can be shared.

Further, in the digital matrix circuit according to the present invention, the matrix coefficients inside the matrix circuit are switched by the plurality of switch circuits to selectively output the plurality of kinds of composite color signals, thereby making it possible to output a plurality of kinds of composite color signals. A part of an adder, a subtractor, a multiplier or the like necessary for generating a composite color signal can be shared, and the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a digital matrix circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of a digital matrix circuit according to the present invention.

FIG. 3 is a time chart for explaining the operation of the second embodiment.

FIG. 4 is a block diagram showing a configuration of a third embodiment of a digital matrix circuit according to the present invention.

FIG. 5 is a block diagram showing a configuration of a fourth embodiment of a digital matrix circuit according to the present invention.

FIG. 6 is a vector diagram of a composite color signal obtained in the fourth embodiment.

FIG. 7 is a block diagram showing a configuration of a conventional example of a digital matrix circuit.

[Explanation of symbols]

10, 20, 30, 50 ... Digital matrix circuit 11, 12, 13, 21, 22, 23, 31, 32, 3
3, 51, 52, 53 ...
・ ・ ・ ・ ・ ・ ・ ・ ・ Signal input terminals 15, 26, 35, 36, 55
-Signal output terminals 101-113, 110-113, 201-216, 3
01, 302, 501-505 ...
........... Multiplication circuits 121-125, 221-227, 320, 520 ...
・ Adding circuit

Claims (1)

[Claims] 1. A digital matrix circuit for performing weighted addition of a plurality of input color signals to form another color signal, wherein a plurality of switch circuits for switching matrix constants are provided, and the operation of the switch circuits is controlled by an external control signal. , A digital matrix circuit characterized by selectively outputting a plurality of types of composite color signals.