JPS58186290A - Digital matrix circuit - Google Patents

Abstract

PURPOSE:To use a digital matrix circuit for various synthesis signal in common, by obtaining plural kinds of synthesized chrominance signals at a digital matrix circuit and attaining multi-function of the digital matrix circuit. CONSTITUTION:A blue ER signal is applied to a signal input terminal 11, a blue EB is applied to a signal input terminal 12, a green EG signal is applied to a signal input terminal 13 and the operation of switch circuits 131-133 is designated with an external control signal CTL of logical ''0''. Then, a ctrominance E1 signal of the NTSC system is obtained at a signal output terminal 15. The EG signal is applied to the terminal 11, the EB signal is applied to the terminal 12 and the signal ER is applied to the terminal 13 and the operation of the switch circuits 131-133 is designated with the CTL being logical ''1'', allowing to obtain a color EQ signal of the NTSC system at the terminal 15. Thus, the E1 or EQ signal of the NTSC system is designated and outputted with the CTL selectively. Thus, the digital matrix circuit 10 is circuit-integrated for a common component for the E1 and EQ signals.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital matrix I/J circuit that generates other color signals, and particularly to a digital matrix circuit that can specify and output a plurality of output color signals using an external control signal.

Generally, from the imaging output obtained by a color television camera, for example, NTs. In order to form a C-type color telephony signal, as shown in Fig.
Regarding the three primary color signals given as outputs, the first to third multi-color signals jl1, 2.

3, a luminance signal By and two color signals El are obtained by adding and combining them with predetermined weights.

EQ is generated, and encoding according to NTSC method 1 is performed using the three signals Ey, E+, and EQ.

Here, in the NTSC system, the three primary color signals are red signal E
R s green signal EG, blue signal EB, By=0
．． 3(lER+0.59Ey+0.11EB...
The first equation ζ can represent the trowel brightness signal EY. Moreover, each color signal E1, EQ is E+=0.74(En Ey)0.27(Ea-EY
)10. 60ER O. 2F3Ea O. 32Bn...
・2nd formula % formula %) 10. 21Ea-0.52Eo+0.41EB...
Equation 3: When the above-mentioned signals EY, B, and EQ are synthesized by digital processing, (where ai, =Σαijk"2, α1j-
There are h,000 liters in t, o, and t. ) The matrix element of the determinant shown in the fourth equation is, for example, the first
Set as shown in the table to obtain child 0.31En + 0.44ER + 0.13En - 5th formula % formula % ) "0.59EIO, 28EG (131EB - 6th formula I BQ - (-1 -) ER (l + 1) EG 432 232 + ('10') Ee 16 = (1'22Eh O,53Ea+α31Ea ・
. . . Digital addition calculations of the fifth, sixth, and seventh equations, which are the seventh equations, may be performed.

Table 1: Table showing an example of matrix elements of the Digicle 71127 circuit By the way, in the conventional digital matrix circuit, the first digital matrix circuit which performs the digital operation of the above formula 5 and synthesizes the BY times signal, and the above A second digital matrix circuit that performs the digital calculation of Equation 6 and synthesizes the EI multiplied signal, and a third digital matrix circuit that performs the digital calculation of Equation 7 and synthesizes the EQ multiplied signal are each configured separately. Since I was using EY signal only, E! Three types of integrated circuits were required: one dedicated to signals and one dedicated to EQ signals.

In view of the above-mentioned problems, the present invention aims to increase the functionality of the digital matrix circuit by making it possible to obtain multiple types of composite color signals with one digital matrix circuit. This is an attempt to standardize digital matrix circuits.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 2 showing the first embodiment of the IJ system circuit according to the present invention, the first to third signal input terminals 11, 12, and 13 are provided with signals obtained from a color television camera (not shown). Three primary color signals ER+ EG +
Each of the EBs is digitized by analog/digital processing and supplied as a digital signal indicating each signal level using, for example, an 8-bit BCD code.

The digital multiplex circuit 10 of this first embodiment includes 13 multiplier circuits 101, 102, 103°, 104.
105,106,107,108,109.110,1
11, 112, 113 and five adder circuits 121, 12
2, 123, 124, and 125, and three switch circuits 131, 1 that perform switching operations according to the logical value of an external control signal CTL supplied to an external control signal input terminal (not shown).
32°133, and is constructed as follows.

That is, the first signal input terminal 11 is connected to a first multiplier circuit 101 with a multiplier of "16J," a second multiplier circuit 102 with a multiplier of "2," and a third multiplier circuit 103 with a multiplier of "l." ing. The first to third multiplication circuits 101, 10
2.103 supplies each multiplication output to the first addition circuit 121.

Here, the second multiplication circuit 102 and the first addition circuit 1
A first switch circuit 131 is provided between the
The multiplication output from the second multiplication circuit 102 is supplied to the first addition circuit 121 via the first switch circuit 131.

The first switch circuit 131 receives an external control signal CT L
The opening/closing operation is controlled by the external control signal Ci.
” L becomes a closed state when logic 3! l I J, and the multiplication output from the second multiplier circuit 102 is supplied to the first addition circuit 121, and the external control signal CT L becomes logic [
0, the second multiplier circuit 10 becomes open and the second multiplier circuit 10 is opened.
2 is prohibited from being supplied to the first addition circuit 121.

Further, the second signal input terminal 12 is connected to a fourth multiplier circuit 104 with a multiplier of "8" and a fifth multiplier circuit 105 with a multiplier of "12".
and is connected to. The fourth and fifth multiplication circuits 1
04.105 supplies each multiplication method to the second addition circuit 122. c.) The second adder circuit 122 supplies its addition output to the third adder circuit 123 via the sixth multiplier circuit 106 with a multiplier of 1-1. Further, the third addition circuit 123 is supplied with the addition output from the first addition circuit 121, and the addition output is applied to the multiplier Ill.
and an eighth multiplication circuit 108 whose multiplier is 1=1.

Further, the third signal input terminal 13 has a multiplier of 18-
a ninth multiplier circuit 109 with a multiplier of 1, a tenth multiplier circuit 110 with a multiplier of 11, and an eleventh multiplier circuit 11 with a multiplier of [-1].
Connected to 1. The ninth to eleventh multiplication circuits 109, 110, and 111 supply their respective multiplication outputs to the fourth addition circuit 124. Here, the tenth and eleventh multiplication circuits 110, 111 (!: fourth addition circuit 1
A second switch circuit 132 is provided between the
Each multiplication output is selected by the second switch circuit 132 and supplied to the fourth addition circuit 124.

The second switch circuit 132 receives an external control signal C'I'.
The switching operation is controlled by L, and when the external control signal CTL is logic "0", the multiplication output from the tenth multiplication circuit 110 is supplied to the fourth addition circuit 124, and
When the external control signal CTL is logic "L", the multiplication output from the eleventh multiplication circuit 111 is transferred to the fourth addition circuit 124.
supply to.

The fourth adder circuit 124 then passes the addition output to the fifth multiplier circuit 112 whose multiplier is r-IJ.
It is supplied to the adder circuit 125.

Further, the multiplication outputs from the seventh and eighth multiplication circuits 107 and 108 are selectively supplied to the fifth addition circuit 115 via a third switch circuit 123.

The third switch circuit 133 receives an external control signal CTL.
The switching operation is controlled by the external control signal CT.
The multiplication output from the seventh multiplication circuit 107 is supplied to the fifth addition circuit 125 when L is logic "0", and the eighth multiplication circuit 108 is supplied when the external control signal CTL is logic "1". The multiplication output is supplied to the fifth addition circuit 125. . . . The fifth adder circuit 125 outputs the signal from the signal output terminal 15 via the adder 3.

In the first embodiment configured as described above, the Ea times signal is supplied to the first signal input terminal 11, the EB times signal is supplied to the second 1-go input terminal 12, and the third signal input terminal 12 is supplied with the EB times signal. An EG multiplied signal is supplied to the signal input terminal 13, and the first to third switch circuits I are controlled by an external control signal CT L having logic 10.1.
i! By specifying the operation of 3131.132.133, an EI multiplied signal in the NTS C system can be obtained at the signal output terminal 15.

That is, when the external control signal CTL is logic "0", the first addition circuit 121 calculates (16+2+1)
- An addition output of ER is obtained, and the fifth addition circuit 125 is connected to the seventh multiplication circuit 1 via the third switch circuit 133.
From 07 (16+2+1)・B++ -('8+2)
- A multiplication output called EB is supplied. First, the fourth addition circuit 124 obtains an addition output of (8+1)・EG, and the fifth addition circuit 125 has a twelfth multiplication circuit 1.
12 supplies a multiplication output of -(8+1)·Eo.

Therefore, in the fifth adder circuit 125, (12 + 1
)・ER'-(8+1)・EG-(8+2)・EB is obtained, and the output is sent to the signal output terminal 15 via the 13th multiplier circuit 113 as 0.59EB-0, 28EG O, 31EB
. . . An EI multiplied signal expressed by the eighth equation can be obtained.

Further, in the first embodiment described above, the first signal input 71
The EG multiplied signal is supplied to the terminal 11, and the second signal input terminal 12
EB multiplied signal is supplied to the third signal input terminal 13.
An ER multiplied signal is supplied to each switch circuit 131, 132.1 by an external control signal C'l''L of logic [1-1.
By specifying the operation of No. 33, an EQ multiplied signal in the NTSC system can be obtained at the signal output terminal 15.

That is, when the external control signal CTL is logic [1], the first addition circuit 121 obtains an addition output of (16+1)·E, and the fifth addition circuit 125 obtains a third output.
−(16+1)·1”;a+(3+2)·EB from the eighth multiplier circuit 108 via the switch circuit 133 of
A multiplication output is provided. In addition, the fourth addition circuit 12
4, an addition output of (8-2)·I×R is obtained, and a multiplication output of −(8-1)·EH is supplied to the fifth addition circuit 125 via the twelfth multiplication circuit 112. . Therefore, in the fifth addition circuit 125 -()11)・En -
An addition output of (16+1).Eo + (8+2).EB is obtained, and an EQ multiplied signal expressed by the ninth equation, which becomes the signal output terminal 15 via the thirteenth multiplication circuit 113, is obtained.

That is, in the first embodiment described above,...
・Perform the I-I+ calculation shown in Equation 10, which is Equation 1O, and selectively specify the E+ signal in the NTSC system or the EQ multiplied signal using the external control signal CT L to combine the signal and E.
It can be integrated into an integrated circuit as a common component for forming a Q-fold signal.

Next, in FIG. 3 showing a second embodiment of the digital matrix circuit according to the present invention, 21 is a first signal input terminal to which a BR multiplied signal is supplied, and 22 is a first signal input terminal to which a BG signal is supplied. 23 is a second signal input terminal.
is the third signal input terminal to which the EB multiplied signal is supplied. In addition, the above-mentioned ER signal-1Ea signal, the Ea times signal, the above-mentioned first
It is assumed that the signal level of each of the three primary color signals is indicated by a digital record as in the embodiment described above, and has a clock frequency of 41sc, which is four times the -carrier frequency fsc.

This second digital matrix circuit 20 includes 16 multiplication circuits 201, 202, 203, 204°205.20
6,207,208,209,210.211,212
, 213, 214, 215° 216 and seven adder circuits 221, 222, 223, 224, 225, 226, 2
27, and two switch circuits 231 and 222 that perform switching operations according to the logic value of external control (i. It is composed of

That is, the first signal input terminal 21 is connected to the first adder circuit 2.
21, and the ER multiplied signal is supplied to the first addition circuit 221 through the first signal input terminal 21. Further, the second signal input terminal 22 is connected to first and second multiplier circuits 201 and 202 with a multiplier of "-■" and a third multiplier circuit 203 with a multiplier of "32", respectively. The multiplier signal is passed through the second signal input terminal 22 to the 14f to third multiplier circuits 201, 202, and 203.
supplied to Further, the third signal input terminal 23 is connected to the second addition circuit 222, and the EB multiplied signal is supplied to the second addition circuit 222 through the third signal input terminal 23.

The first multiplication circuit 201 transmits its multiplication output to the first multiplication circuit 201.
is supplied to the adder circuit 221. Then, this first addition circuit 221 obtains an addition output of BR-EG,
The fourth multiplier circuit 204 has a multiplier of 8-1 and a multiplier of 12.
The fifth multiplication circuit 205 has a multiplier of 116, the seventh multiplication circuit 207 has a multiplier of 1-1, the eighth multiplication circuit 208 has a multiplier of 4-1, and the multiplier has a multiplier of 1-1. 1-8
The above addition output is supplied to the ninth multiplication circuit 209 of ``.

Further, the second multiplication circuit 202 supplies its multiplication output to the second addition circuit 222.

Then, this second addition circuit 222 obtains an addition output of EB -Ea, and the first O-th multiplication circuit 22 whose multiplier is "4"
10, an eleventh multiplication circuit 211 with a multiplier of "8", and a twelfth multiplication circuit 21 with a multiplier of "1-2".・Supply one-to-one addition output to 2.

The third multiplication circuit 203 supplies its multiplication output to the third addition circuit 223. Further, the fourth and fifth multiplication circuits 204 and 205 supply their respective multiplication outputs to a fourth addition circuit 224.

This fourth adder circuit 224 has (8+2)·(En−
EG) is obtained, and this addition output is supplied to the third addition circuit 223.Furthermore, the third addition circuit 223 is supplied with the multiplication output from the first O multiplication circuit 210. 32・E et al.+(g+2)
・(ER-Eo)+4・(EB-E,i) is obtained, and this addition output is multiplied by 1-! -j 13th
The signal is output from the second signal output terminal 25 via the multiplication circuit 213.

That is, in this second embodiment, the first signal output terminal 25 has E v ” ”−・(32・EC×(8+2)・(ER
-Ea)2 To4・(EB-Ec) =E(++0.31・(ER-EG)+0.12・(
EB-EG)...The luminance signal EY in the NTSC power formula expressed in the color difference format of the 11th formula is obtained.

Further, the sixth to ninth multiplication circuits 206, 207.
208 and 209 are the fifth addition circuit 225 for each multiplication output.
is supplied to. Here, a first sui-nochi circuit 231 is provided between the eighth and ninth multiplication circuits 208, 209 and the fifth JJII calculation circuit 225, and the eighth
The multiplication outputs of the ninth multiplication circuits 208 and 209 are selectively supplied to the fifth addition circuit 225 via the first switch circuit 231.

Furthermore, -F eleventh and twelfth multiplication circuits 211.
212 supplies each multiplication output to a sixth addition circuit 226. This sixth adder circuit 226 is (8+2)·(E
B −E+> ) is obtained, and this addition output is combined with the 14th multiplier circuit 214 with a multiplier of 1-1 and the multiplier with a multiplier of [1
] is supplied to the fifteenth multiplication circuit 215. The multiplication outputs of the fourteenth and fifteenth multiplication circuits 214 and 215 are selectively supplied to the seventh addition circuit 227 via the second switch circuit 232. The seventh adder circuit 227 is the fifth adder circuit 2
25 is supplied, and the 7JD calculated output is outputted from the second signal output terminal 25 via the 16th multiplication circuit 2216 whose multiplier is "-1".

Here, the first and second switch circuits 231.2
32, the switching operation side 1a4I is performed in conjunction with each other according to the logic value of the external control signal CT_L, and when the external control signal CT_L is logic [l], the first switch circuit 231 While selecting the eighth multiplier circuit 208, the second switch circuit 232 selects the fourteenth multiplier circuit 21.
4, and the above external side [present] signal C'I' L
is logic [0], the first switch circuit 23
1 selects the ninth multiplier circuit 209, and the second switch circuit 232 selects the fifteenth multiplier circuit 215. Furthermore, the external control No. 18 CTL controls the switching of the first and second switch circuits 231 and 232 at a frequency that is twice the subcarrier frequency fsc in the NTSC system [cock frequency 2·/'SC]. There is.

Therefore, in this second embodiment, the fifth adder circuit 225 outputs an addition output of (1(i+4-1)·(En -EC7)) to the seventh adder circuit when the external control signal CTL is the logic Ill. When the external control signal CTL is supplied to the adder circuit 227 and is at logic [0''-C'', (
, 16-8-1) (to ER-E) supplies the output of the lamp unit f to the seventh adder circuit 227. Therefore,
The seventh adder circuit 227 receives an external control signal C'I''
When L is logical rlJ, (16+4-1)・(E
R-Ea) (8+2)・(EB-Et; )
40, 59·(Iun-EG) −0,31·(EB−
Eo)... It is possible to output the E1 signal in the NTSC system expressed in the color difference format of the 12th equation. Further, when the external control signal C'I"l is at logic [0", the seventh adder circuit 227 outputs (16-8-■) (EH-1 ahead) + (8+2) (Ea-Ec)4C is obtained, and from the second signal output terminal 26 via the 16th addition circuit 216, -022・(E' EG)+0.31(EB-EG)
. . . The N'r SC method expressed in the color difference format of Equation 13 (equation 13) can output an EQ multiplied signal.

Therefore, in this second embodiment, as shown in FIG. 4, N 1' S
The El signal and the EQ multiplied signal in the C method are alternately outputted from the second signal output terminal 26.

That is, in the digital matrix circuit 20 in the second embodiment configured as described above, the first signal output terminal 2
5, the By-fold signal is obtained, and the second signal output terminal 26
An EI multiplied signal and an EQ multiplied signal can be obtained. Therefore,
Valley switch circuit 231.23 by external control signal CTL
2 can be dynamically controlled to obtain the dot-sequential color difference signal shown in FIG. 4, for example, to easily form a carrier color signal in the NTSC system.

Here, since the above-mentioned first embodiment and second implementation settings are used, for example, for an 8-hit tental signal, n logic [0]41'Roi' addition bits are added below the lowest hit. By giving the multiplier 11J when n-0,
Multiplier ``2'' when n = 2, multiplier 14 when n = 3
4. When n = 4, it is possible to perform the multiplier [-8 upper I+, when -5, the multiplier is 16, and when n = 6, the multiplier is 132. The third embodiment shown in FIG. 5 simplifies the digital matrix circuit 20 in the second embodiment described above and is suitable for use in a popular household video camera or the like. It was designed to be applied.

In this third embodiment, the first to third signal input terminals 31, 32, and 33 receive the three primary color signals ER1EG, which are tenckled with a clock frequency of 4 fsc, as in the second embodiment described above.

EH is supplied. The first to third signal input terminals 31, 32, and 33 are connected to a general matrix circuit 300 for forming luminance signals.
0 is the above three primary color signal EH.

E(=, bu) forms a luminance signal Ey, supplies this luminance signal 1'c to the subtraction circuit 320, and
The signal is output from the signal output terminal 35 of.

Further, the second and third signal input terminals 32 and 33 are connected to the subtraction circuit 320 via the first switch circuit 331.
The ER multiplied signal and the BB multiplied signal are selectively supplied to the subtraction circuit 320 by the first switch circuit 331 . This subtraction circuit 320 is
A subtraction output gR-Ey and a subtraction output EB-Ey are obtained alternately, and a first multiplication circuit 301 has a multiplier of IO, 877J, and a second multiplication circuit 302 has a multiplier of IO, 455j.
The above subtracted output is supplied to . The first and second multiplication circuits 301 and 302 selectively output the respective multiplication outputs from the second signal output terminal 36 via the 20th switch circuit 332. Here, the first and second switch circuits 331 and 332 are connected to an external control signal C having a clock frequency of 2fsc, which is supplied to an external leg input terminal (not shown).
Switching operation is performed outside and wholesale by TL.

In the digital matrix circuit 30 in the third embodiment configured as described above, the luminance signal EY in the NTSC system is obtained at the first signal output terminal 35, and the color difference signal 0 is obtained at the first signal output terminal 35.
877・(ER-BY).

0455・(EB-Ey) is the second signal input terminal. Next, CCD (Charge Coupled Dev
In a solid-state color video camera using a solid-state image sensor such as
An embodiment of the digital l-1x circuit according to the present invention, which is applied to a case where there are fewer than 9, will be described.

In the fourth embodiment shown in FIG. 6, the first to third signal input terminals 41, 42, 43 receive the three primary color signals El(
, EG, and EB are supplied. The E++ signal is supplied from the first signal input terminal 41 to the first addition circuit 421 via the first multiplication circuit 401 whose multiplier is [rl]. Further, the EB multiplied signal is supplied from the second signal input terminal 42 to the second addition circuit 422 via the second multiplication circuit 402 with a multiplier of rbrJ, and the multiplier is 1b2.
-1 is supplied to the first addition circuit 421 via the third multiplication circuit 403. Further, the EG multiplied signal is supplied from the third signal input terminal 43 to a three-man powered Sui-Nochi circuit 430 via a fourth adder circuit 424 with a multiplier of "gl", and a third signal input terminal with a multiplier of "gl". 5 multiplication circuit 4
05 to the second addition circuit 422.

-F first addition circuit 421 is rl-ER+b2・E
An addition output B is obtained and this addition output is supplied to the switch circuit 430. Further, the second addition circuit 42
2 obtains the addition output of byo・E, 10g2・EG,
This addition output is supplied to the switch circuit 430. This switch circuit 430 is supplied to an external control signal input terminal (not shown) and operates to generate composite color signals C1, C2, C3 expressed by the following equation 13.
are sequentially output from the signal output terminal 45.

The composite color signals C+ and C2 shown in the above equation 13.

C3 is, for example, CI as shown in the vector diagram of FIG.
By setting the modulation axis of C2 to 10 degrees, the modulation axis of C2 to 22 degrees, and the modulation axis of C3 to 11q, it is possible to provide a primary color three-phase modulated carrier color signal C equivalent to the carrier color signal in the NTSC system.

Here, the matrix constant in the above equation 13 is j, =
(163, g, = (163, g2 = (118, b + = α
45, with b2=0, the above carrier color signal C is C=C
1+C20C3 −〇, 63 E Reexp (Jω5ct−[05°)
(-0,63Ea eXp(Jωsc'+225°)+
(045Eu+Q, 18Ea) eXI) (j"sc'
15) It can be expressed by the 14th equation, and the white buff female can be maintained sufficiently.

Further, the digital norm 1-12 circuit which performs the -71-IJx operation shown in Equation 13 above can also be realized, for example, with a configuration as shown in FIG.

That is, the digital matrix circuit 50 in the fifth embodiment shown in FIG. switch circuit 531.532
and one adder circuit 520 are used. The first 1,000 circuits 30 are connected to the first signal input terminal 5.
1 through the first multiplier circuit number row.
The multiplication output ER and the second signal from the second signal input terminal 52
The multiplication output b+·EB supplied via the multiplication circuit 502 and the multiplication output gl·E(, supplied from the third signal input terminal 53 via the fourth multiplication circuit 504) are sequentially The selected signal is supplied to the addition circuit 520.The second switch circuit 531 also connects the second signal input terminal 5 to the addition circuit 520.
b2・supplied from 2 through the third multiplication circuit 503
A multiplier output called EB and a signal from the third signal input terminal 53 to the fifth
The multiplication output g2·E() is supplied via the multiplier circuit 505, and the logic 10 is supplied from the ground line, for example.
'' are sequentially selected and supplied to the adder circuit 520. The first and second switch circuits 531, 5
32 is controlled by an external control signal to perform switching operations in conjunction with each other, so that the signal output terminal 55 is connected to the fourth
This can be done by outputting point-sequential color signals c, , C2, C3 similar to the embodiment.

As is clear from the above description of the combination embodiment, according to the present invention, multiple input color signals are weighted in a digital matrix circuit that performs addition to form other color signals.
- A switch circuit for switching the number of soots is provided, and the operation of the switch circuit is controlled by an external control signal to selectively output multiple types of composite color signals. A composite color signal for multiple buildings can be specified and obtained using an external control signal using a digital matrix circuit. Therefore, the DigiGlue 71-I+Tsuku diagram for various color compositions can be shared.

In addition, by switching the matrix constant using an external control signal, a point-sequential output of various time-division multiplexed composite color signals can be obtained, and a color carrier signal compatible with standard television systems such as the NTSC system can be obtained. It is also easy to obtain. Therefore, according to the present invention, the intended purpose can be fully achieved.

[Brief explanation of the drawing]

Figure 1: It is a block diagram showing the configuration of a conventional example of an etenotal matrix circuit. 2 to 8 show one embodiment of the digital matrix circuit according to the present invention, FIG. 2 is a professional diagram showing the configuration of the first embodiment, and FIG. 3 is a diagram showing the configuration of the second embodiment. FIG. 4 is a time chart for explaining the operation of the second embodiment, and FIG. 5 is a block diagram showing the structure of the third embodiment. , FIG. 6 is a block diagram showing the configuration of the fourth embodiment, FIG. 7 is a -\ torque diagram of the composite color signal obtained in the fourth embodiment, and FIG. 8 is a block diagram showing the configuration of the fourth embodiment. The configuration of the example is not shown.
” This is a diagram. 10.20,30,40.50...Digital matrix circuit 11.12,13,21,22.23.31,32゜3
3.41, 42.43.51, 52.53...
Signal input terminal 15.26, 35, 36, 45.55... Signal output terminal 101.102, 103, 104, 105, 106゜1
or, 1 os, 1 os, 11 o,
111, i 12J. 113.201.202,203,204,205゜2
06.207,208,209,210,211゜21
2.213,214,215,216,301□302
．． 401.402,403,404,405゜501.
502, 503, 504.505...Multiplication circuit 121.122, 123, 124, 125, 221°2
22.223,224,225,226,227゜32
0.421, 422.520 ...Addition circuit 131.132, 133, 231, 232, 331゜3
32.430,531.532 ...Switch circuit patent applicant Sony Corporation agent Roshi I Kodo Koike 1) Sakae Mura −

Claims (1)

[Claims] Weighting of multiple input color signals is performed by adding the input color signals to form another color signal.
1. A digital/L/matrix circuit, comprising: a switch circuit for switching a matrix constant; and an external control signal controls the operation of the switch circuit to selectively output a plurality of types of composite color signals.