JPS62206989A - Chrominance signal processing circuit - Google Patents

Abstract

PURPOSE:To maintain a sample rate to the prescribed value, which does not cause the picture quality deterioration, without adding a smoothing circuit, etc., and to execute the chrominance adding a smoothing circuit, etc., and to execute the chrominance signal processing by using a basic clock and the inverting clock to the control signal of a multiplexer. CONSTITUTION:A multiplexer 104 is controlled by a control signal F3 of the same signal as a basic clock, a control signal F3 selects an I signal C3 at a 'H' level, when the inverting signal of the control signal F3 is the 'H' level, selects a Q signal C2, and during the image period of an input chrominance signal C0, a chrominance signal C1 is supplied through a multiplexer 105 to a multiplier 106 at every half period of the basic clock. Consequently, during the image period, a Q signal C2 and an I signal C3 are inputted as a multiplicand to a multiplier 106 and the second matrix coefficients RQ2'-BI2' are inputted as a multiplier respectively. The color difference signal obtained in such a way is equal to the signal using a smoothing circuit conventionally.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention provides a method for digitizing an analog video signal.
The present invention relates to a digital television device that performs signal processing, and particularly relates to a color signal processing circuit thereof.

[Technical background of the invention]

FIG. 4 shows the conventional color signal processing circuit described above. Is this color signal processing circuit 4? This method is described in Japanese Patent Application No. 59-117067, and after converting an analog video signal into a digital video signal, ACC control and color saturation adjustment matrix calculation are performed on the luminance and chromaticity separated chromaticity signals. This is a circuit that demodulates into color difference signals.

The above matrix calculation and color demodulation will be explained in detail below. The matrix calculation and color demodulation are performed by performing the calculation shown in the following equation (1) on the color signal 501 given by a Y/C separation circuit (not shown) during the image period.

Here, I and Q are color signal ratio Q, BI is a matrix coefficient, and -Y and B-Y are color difference signals. A C color signal 501 is input to the signal conversion circuit 401, and...Q, I, Q , I
... is converted into a color signal 502 consisting of 7 format data. The color signal 502 is input to the multiplexer 402 together with the ACC signal 505 output from the ACC circuit 405 . The multiplexer 402 selects the color signal 502 during the burst period and image period of the color signal 502, and selects the ACC signal 505 during other periods and outputs it to the multiplier 403. Further, 41 matrix coefficients RIQ1-B11, which are output signals of the control circuit 423, correspond to second matrix coefficients Q2-BI2., which are output signals of the registers 414-419. ! : Both multiplexers 407 to 41
2 respectively. Multiplexer 407-41
2 selects the second matrix coefficients RQ2 to BI2 in the image period of the color signal 502, and selects the first matrix coefficients RQI to BII in other periods and outputs them to the multiplexer 404 together with the ACC signal 505. 0 Now, the multiplexer 404 selects the ACC signal 505 during the burst period of the color signal 502, sequentially selects the second matrix signals Q2 to BIZ during the image period, and selects the first matrix signal Q2 to BIZ during periods other than the burst and image. Coefficient R
QI to B11 are sequentially selected and output to multiplier 403. During the burst period of the color signal 502, the multiplier 403 inputs the color signal 502 as a multiplicand and the ACC signal 505 as a multiplier, and performs multiplication. The signal 504 is input to an ACC circuit 405 and converted into a new ACC signal 505. Furthermore, in periods other than bursts and images, the ACC signal 505 is input as a multiplicand and the first matrix coefficients RQI to BII are sequentially input as multipliers to perform multiplication. What is the product 504? J! J2
The 7 trix coefficients RQ2 to BI2 are sequentially stored in register 4.
Stored in 14-419.

Further, in one image period, the color signal 502 is input as a multiplicand and the second matrix coefficient is used as a multiplier, and multiplication is performed.

The a504 is input to a color demodulation circuit 452 consisting of a delay circuit 406 and an adder 413, which calculates the above formula (1) and generates three color difference signals (R-Y, B-Y, G-Y).
)506K demodulated. The color difference signal 506 is input to a separation circuit 451 composed of registers 420 to 422 and is separated into a -Y signal 507, a G-Y signal SOS, and a 13-'Y signal 507.

By the way, the above-mentioned 几-Y signal 507, G-Y signal 508, B
-Y signal 509 is obtained at a sample rate of 1/6 of the basic clock. However, according to evaluations, when the basic clock is 4fsc, that is, four times the frequency of the color subcarrier, in signals with large color changes such as color bar signals, coarse grainy patterns are visible in the changing parts, which is a factor in image quality deterioration. becomes. FIG. 5 is a diagram for explaining this situation, and is a schematic waveform diagram of color difference signals 507 to 509 output from the separation circuit 451. The same figure (5a) is a signal waveform diagram when the sample rate power is 4 fsc (Msps), the same figure (5b
) is a signal waveform diagram in the case of 'X4fsc (MSPS). As is clear from comparing both figures, sample rate)
When t-1/6 K is reduced, the change is very gradual in the color change portion, resulting in deterioration of image quality. Therefore,
The obtained R-Y signal 507, G-Y signal 508, B-Y
Signal 509 is connected to register 424.426.428.43
3 to 435, adders 425, 427, and 429, and multiplexers 430 to 432.
50 and is converted into smoothed signals 510-512. FIG. 5(5d) shows a signal obtained by smoothing the signal in FIG. 5(5b). The smoothing method is Sample Ray) wo'7"
sc(MgF2) Vcl, the interpolated signal is derived by the average value of the previous and subsequent signals. This reduces the image quality deterioration.

[Problems with background technology]

In the conventional color signal processing method described above, software processing and time-sharing processing are used to normally require at least nine multipliers when performing ACC processing, color saturation, hue adjustment, and matrix calculation. Therefore, only one multiplier is required.

However, the smoothing circuit 450 is required to reduce image quality deterioration. The circuit scale of this smoothing circuit 450 is approximately 600
This is a problem if you want to reduce the circuit scale as much as possible when converting this type of circuit into an IC.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a color signal processing circuit that eliminates the above-mentioned problems and allows the circuit board to be reduced in size.

[Summary of the invention]

This invention uses a basic clock and its inverted clock as control signals for multiplexers, thereby sending the multiplier input signal, which was conventionally sent every lock unit, every half period of the basic clock. The color signal processing is performed while maintaining the sample rate at a predetermined value that does not cause image quality deterioration without adding a color smoothing circuit or the like.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention. A feature of the present invention is that it includes a signal conversion circuit 201 and a color demodulation circuit 202. Here, the basic clock is 4 of the color subcarrier fsc.
Double it. A color signal CO provided by a Y/C separation circuit (not shown) is input to a signal conversion circuit 201, and Q, I
, Q, I, Q, . . . The color signal C1 is sent to the multiplexer 1 together with the ACC signal C12 output from the ACC circuit 110.
05 is input. The output of multiplexer 105 is input to multiplier 106. The first matrix coefficient RQI" which is the output signal of the control circuit 127
' are respectively inputted to multiplexers 112-117 together with second matrix coefficients RQ2"-BI2' which are output signals of registers 121-126. Output signals 013-018 of multiplexers 112-117 are ACC
It is input to multiplexer 109 together with signal C12.

The output signal 019 of the multiplexer 109 is sent to the multiplier 106
is input.

During the burst period of the input color signal Co, the multiplier 106 uses the color signal C1 as the multiplicand and the ACC signal C1 as the multiplier.
2 is input, and its product C6 is output.

The product C6 is input to the ACC circuit 110 and outputs a new ACC signal C12. In a period other than the burst and image of the input signal Co, the multiplier 106 uses the human CC signal C12 as the multiplicand and the first matrix coefficient RQx° as the multiplier.
Input B11' sequentially. The product C6 is the second matrix coefficient RQ2'~BI2° and the registers 121~12
6 are sequentially stored.

Next, regarding the image period of the input color signal Co, FIG.
This will be explained using A. FIG. 2 shows output signals of each circuit, and FIG. 3 shows control signals of each circuit.

Note that FIG. 2 (2a) and FIG. 3 (3a) show basic clocks.

The input signal cm is converted by the signal converter 101 into a signal as shown in FIG.
The data format is converted into the data format shown in b).

The output signal C4 of the signal converter 101 is sent to the register 102゜1.
03. Register 102 sets the basic clock to 2
The frequency-divided clock F1 (FIG. 3 (3b)) separates the color signal C4 and Q signal C2 (FIG. 2 (2C)). On the other hand, the register 103 uses a clock F2 (FIG. 3 (2C)) which is an inversion of the clock F1. (3c)), the color signal C4 is separated from the color signal C3 (FIG. 2 (2d)).

The above Q signal C2 and ■signal C3 are both <multiplexer 10
4 is input. The multiplexer 104 is controlled by the control signal F3 (FIG. 3 (3d)), which is the same signal as the basic clock, and when the control signal F3 is at the ``H'' level, the output signal C3 is
is selected and the Q signal C2 is selected when the inverted signal of the control signal F3 is at the ``H'' level. The color signal C1 (
FIG. 2(2e)) is supplied.

On the other hand, the multiplexers 112 to 117 input the input color signal Co.
The matrix coefficient of temperature 2 during the image period aRQ2~BIz'
is selected and output to multiplexer 109.

The multiplexer 109 outputs control signals F4 to F9 (see FIG.
3e) to (3j)), the matrix coefficients RQ2° to BI2'' of the tube 2 are sequentially selected every half period of the basic clock and output to the multiplier 106. That is, the control signals F4 to F
9 are at the "H" level, the second matrix coefficients RQ2" to BI2° are selected, and the signal shown in FIG. 2 (2f) is output as the signal C19.

Therefore, during the image period, the Q signal C2 and the engineering signal C3 are input to the multiplier 106 as multiplicands, and the second matrix coefficients RQ2' to B I 2' are input as multipliers. The product 06 of the multiplier 106 is the register 107 and the adder 1
08 is input. Register 107 is clock FIO
Using the same clock as the clock F2 ((3k) in FIG. 3), the output signal C5 ((2g) in FIG. 2) is separated from the product C6. The adder 108 adds the output signal C5 and the product C6 of the multiplier 106. Output signal C7 of adder 108 is input to register 128. The register 128 uses the same clock as the clock F1 as the clock 11 ((31) in FIG.
)). This color difference signal C8 is sent to the register 118.
~120 respectively, and the 几-Y signal C9, G-Y
The signal Cl01B-Y signal C11 is separated and output.

At this time, the sample rate of the three color difference signals C9 to C11 is 4.78 (M8PS), and these color difference signals C9 to C11 are 4.78 (M8PS).
11 is schematically shown in FIG. 5(C). As is clear from a comparison with FIG. 5(d), the color difference signal obtained by the present invention is equivalent to that obtained using a conventional smoothing circuit.

Note that 81SC is used as the basic clock, only matrix calculations are operated with this 8fsc, and other logic parts are operated with 4fsc.
If it is operated at fsc, the sample rate of the obtained color difference signal can be increased to 4.78CMSP8).

〔Effect of the invention〕

According to the present invention described above, by adopting a circuit with a simple configuration (signal conversion circuit 201, color demodulation circuit 202) without using a large-scale smoothing circuit, the circuit scale does not increase even slightly. By setting the sample rate of the color difference signal to a predetermined value, image quality deterioration can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing one embodiment of the color signal processing circuit according to the present invention, FIG. 2 is a schematic diagram of output signals in each part of the color signal processing circuit, and FIG. 3 is a diagram of the color signal processing circuit. FIG. 4 is a waveform diagram of a clock signal supplied to each part, FIG. 4 is a circuit configuration diagram of a conventional color signal processing circuit, and FIG. 5 is a schematic diagram of a color difference signal. 101...Signal converter, 102.103,107,118-126,128...
・Register, 104.105, 109, 112-117
... Multiplexer, 106 ... Multiplier, 108
...Adder, 110...ACC circuit, 127...7 troll circuit, 201...Signal conversion circuit, 202...Color demodulation circuit. Agent Patent Attorney Nori Chika Hiroshi Uji, C4 (2b) ch to 91 1
92 I2 α3I3, C2 2nd @ 38th (5a) (5b) (5C)
(5d) Figure 5

Claims (1)

[Claims] a carrier color signal separated from a digital video signal obtained by digitizing an analog video signal; a first separating means for separating the carrier color signal into an I signal and a Q signal in an image period of the carrier color signal; and the I signal. and Q signals, and selects and outputs them every half cycle of the basic clock; and second selection means that sequentially selects and outputs the matrix coefficients every half cycle of the basic clock; a multiplier that uses the output of the first selection means and the output of the second selection means as a multiplier; a second separation means that separates the I signal or the Q signal from the output of the multiplier; It is characterized by comprising an adder that adds the output of the multiplier and the output of the second separation means, and color demodulation means that converts the output of the adder into a basic clock unit and demodulates it into a color difference signal. Color signal processing circuit.