JPS60167589A - Digital television circuit - Google Patents

Abstract

PURPOSE:To realize chrominance vertical profile correction with less hardware by sliding a point for isolating a luminance signal from a chrominance signal for a single horizontal period (1H), presetting a time axis difference between both signals and by automatically correcting with its time difference a chrominance signal delay produced when the chrominance signal is corrected in its vertical profile. CONSTITUTION:Color difference signals B-Y and R-Y are demodulated and derived from respective latch circuits 31 and 32. The color difference signal B-Y is inputted into a delay circuit 33 cascaded 1H delay circuits 331 and 332. Assuming input part signals in the circuits 331 and 332 to be B1, B2 and B3, the signals B1 and B3 are inputted into an adder 34; the signal B2 is inputted into an adder 36 through a coefficient multiplier 35. The adder 36 performs additional operation of the output signal B4 to a signal B2, thus performing a -B1+3B2- B3 operation and obtaining the color difference signal B-Y subjected to vertical profile correction from the adder 26.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The invention relates to a digital television circuit that processes a digital video signal converted into a digital signal, and is particularly characterized by vertical contour correction means for color signals. Be prepared.

[Technical background of the invention and its problems]

Most parts of conventional television receivers, except for some control circuits, are constructed from analog signal processing circuits. However, with recent advances in digital integrated circuit technology, it has become possible to replace the video signal processing section with a digital signal processing circuit.

Digital television receivers have the following advantages over conventional analog television receivers in terms of performance, functionality, and price. First, digital signals are stable without distortion, and by using a memory, operations on the p time axis are easy, and arithmetic processing between pixels on the screen can be performed with good performance. Therefore, image processing performed in ordinary television receivers, such as luminance and chromaticity (Y
/C) The performance of separation, contour correction, etc. is improved. Furthermore, by expanding the memory capacity, special effect processing of images, scanning line conversion, etc. can be performed. Furthermore, functions can be easily expanded by connecting to other digital equipment such as a personal computer. In terms of manufacturing, the process can be expected to be streamlined by reducing the number of external parts for integrated circuits and automating various adjustments.

Incidentally, among the items related to image quality improvement mentioned above, there is vertical contour correction. By emphasizing the vertical display change portions of the image, this method achieves a picture with a reduced tension that could not be obtained by simply emphasizing the horizontal contours, thereby significantly improving the image quality.

Here, separation of vertical contour components is performed by correlation processing of a total of three lines of video signals, one line and two lines adjacent above and below it, so there are two delay lines with at least one horizontal period (hereinafter referred to as IH). It becomes necessary. 4 fsc
In order to delay a digital video signal sampled at fac (color subcarrier frequency) by 2H, as many as 1820 unit delay elements whose delay time is the sampling period Ts ("" 47π) are required. When vertical contour correction is performed on a luminance signal with a wide band, such a delay circuit is required, and it accounts for a large proportion of the reason for the increase in price. Delay circuits are expensive, and even in the comb filter section for Y/C separation, one IH is required due to price constraints.
Most of them use delay lines.

Therefore, when considering the color signal, for example, the band of the color difference signal is as low as 0.5 MHz, so this is called f.
Even when sampled with a clock of s c/2, the original information is not lost. Therefore, the number of unit delay elements required to delay one color difference signal by 2H is only 227.5, and the total number of unit delay elements can be 445. That is, compared to delaying the luminance signal by 2H, it is possible to extract the vertical contour correction component with a much smaller hardware amount by delaying the color signal by 2H. However, the problem here is that
This is the phase (delay time) difference between the color signal C and the luminance signal Y.

That is, since the vertical contour signal of a certain line is obtained by calculation with the signals of the lines above and below it, the signal of the line after IH is the object of contour correction. Therefore, when performing vertical contour correction on the color signal C, it is necessary to delay the luminance signal by IH in order to align the time axes of the correction signal and the luminance signal. As a result, even if the vertical contour correction of color signals is achieved with a small amount of hardware,
Overall, this results in an unreasonable increase in the hardware associated with the delay line.

5- [Object of the Invention] The present invention has been made in view of the above circumstances, and provides a digital television circuit that can perform color signal vertical contour correction means with less hardware and can also align the time axes of color signals and luminance signals. The purpose is to provide

[Summary of the invention]

According to this invention, in the Y/C separation circuit 13 using a comb-shaped filter, the point t to be separated into a luminance signal and a color signal
l-1) Set the time axis difference between the two signals in advance by shifting f, and then the delay in the color signal that occurs when vertical contour correction is applied to the color signal is automatically set first. This is compensated for by a preset time difference. As a result, even if the vertical contour correction is performed focusing on the color signal and the hardware of the delay circuit is reduced, problems related to the time difference with the luminance signal will not occur.

゛ [Embodiments of the invention] Embodiments of this invention will be described below with reference to the drawings 6- do.

FIG. 1 shows a digital television according to the present invention.

The analog video signal AVD I is sampled and quantized at the timing of the sample pulse φB in an analog-to-digital (A/D) converter 11.
It is output as a digital video signal vD. The sample millimeter φB is 4 of the color subcarrier frequency f8c.
It has twice the frequency (4fsc), and its phase is ±(R
-Y), synchronized with the ±(B-Y) axis. The sample pulse φB is generated by the phase-locked loop circuit 12,
It is supplied to each circuit as a reference timing signal. A color timing pulse TPJ that provides timing for the BY axis among the four sample phases of the upper rudder is also output from the phase-locked Deleuzot circuit 12.

The digital video signal vD is separated into a luminance signal Y11 and a signal C in a Y/C separation circuit 13. Luminance signal Y
is subjected to contrast, contour, and brightness adjustment in the luminance signal processing circuit 14, and then to the matrix circuit 15.
is input to. On the other hand, the color signal C is input to the color signal processing circuit 17 after its gain is adjusted in the automatic color control circuit 16 based on the burst data. In this color signal processing circuit 17, vertical contour correction and color demodulation are performed on the color signal C to obtain a BY signal and a RY signal. The B-Y signal and the R-Y signal are transmitted through the matrix circuit 15.
is input.

In the matrix circuit 15, the luminance signal.

Predetermined digital calculations are performed on the B-Y signal and the R-Y signal, and the outputs are digital R and G signals.

A B signal is obtained. These digital R,G.

The B signal is converted into analog R, G, and B signals by a digital-to-analog (D/A) converter 18, and is applied to an electrode ray tube drive circuit via an output circuit.

The above is an explanation of the entire video signal processing circuit. Next, the η-order separation circuit 13 and the color signal processing circuit 17, which are particularly related to the present invention, will be explained in detail.

FIG. 2 shows the full isolation circuit 13 in detail. The digital video signal vD is input to the IH delay circuit 2 and output as the delayed video signal VD2. Address signal A generated by 22
A random access memory RAM controlled by D. The address circuit 22 counts the sample pulses of the frequency 4 fsc as 910e cycles and generates the address signal AD. Therefore, since the RAM constituting the IH delay circuit 21 writes and reads signals at intervals of 910 in steps of Mπ, the signals are output with a delay of the same amount.

Input digital video signal VDJ and delayed video signal VD2
is input to the subtracter 28, and a signal VDJ-VD2 is obtained as a result of the operation. This means that the color signal components included in the video signal VDJ are separated by correlation calculation with the video signal VD2 before IH. Signal VDI -VO2
is further Q- inputted to a pantone filter 23 having a band of Ic fsc = f = 0.5 MHz, where the color signal C is separated band-wise and output. Further, the previous video signals VDJ and VO2 are input to the adder 24. The frequency characteristics corresponding to this calculation are
When f=nfm, the gain is 2, and when f=(n-1-7)/H, the dyne is zero, which corresponds to removing the color signal component from the video signal VDJ or VO2. However, as it is, in addition to the color signal component, the vertical change (i=(n
+', /'u) where n is small)'! ! However, since this is removed, it is necessary to compensate for this in order to obtain a good luminance signal. Since the luminance signal Y that is ultimately required is separated from the video signal VD2, it is also necessary to separate the vertical variation to be compensated for from the video signal VI)2. To do this, the signal VD3 obtained by inverting the signal VD1-VD2 by the inverter 25 may be input to the low-pass filter 26, and the output of this signal and the output of the adder 24 may be added by the adder 27. The luminance signal Y thus obtained is separated from the video signal D2, and is delayed by 110-H compared to the color signal C separated from the video signal VDJ. Therefore, for color signal C,
Even if an IH delay is caused by the vertical contour correction described below, there is no need to perform an IH adjustment delay on the luminance signal Y.

FIG. 3 shows the color signal processing circuit 17 in detail.

The color signal C whose gain has been adjusted in the automatic color control circuit 16 and the color timing pulse TPi are input here.

Color timing pulse TPJ (c) This pulse is generated by the aforementioned phase-locked loop circuit 12, has a frequency of fsc/2, and is a pulse synchronized with the phase of the BY axis of the color signal C. This color timing pulse TPJ is also input to a delay circuit 5oyc having a delay amount of Lf8c, and the R
-Second color timing chart TP phase synchronized with Y axis
It is also converted to 2. FIG. 4 shows a timing chart of the color signal C and the color timing charts TPI and TP2.

Returning to FIG. 3, the color signal C is transmitted to the latch circuit 3.
1.32, each color timing pulse TPI
, latched at TP2. Therefore, each latch circuit 3
From 1.32 onwards, the color difference signals B-Y and R-Y are demodulated and extracted, respectively. The color difference signal B-Y is sent to IH delay circuits 331, . The signal is input to a delay circuit 33 formed by vertically connecting 9.92 and 9.92. Now, each delay circuit 331
The input/output part signals of ゜332 are BJ, B, ? , B, 9, the signals BJ and B3 are input to the adder 34, and the signal B2 is input to the adder 36 via the coefficient multiplier 35. This adder 36 performs an addition operation between the output signal B4 of the adder 34 and the signal B2. As a result, the calculation -B1+313'-83 is performed, and the adder 36 obtains a color difference signal B-Y that has undergone vertical contour correction. -B1+313'-8,9 means:
Vertical second-order differential signal -BJ+2B, ? -B,? The original signal B2 is added to the original signal B2. If necessary, dyne-adjusted (multiple A) second-order differential signal A(-B)+2B2-B
3) can also be added to the original signal B2 with some additional circuitry.

The procedure for obtaining the vertical contour corrected signal using the color difference signal R-Y is the same as that for the color difference signal B-Y, and the IH
Contour correction is performed by a delay circuit 37 in which delay circuits 97 J and 372 are connected in series, an adder 38, a coefficient multiplier 39, and an adder 40.

Note that the IH delay circuits 331, 332, 371, 372 are controlled by an address signal AD2 generated by the address circuit 41. The address circuit 41 counts color timing pulses TPJ having a frequency of f8c/2 with a period of 113, and generates an address signal AI)2. Therefore,
IH delay circuit 331°J, 92, 37J, ,
The RAM that makes up the 972 is
Perform a delay of 6/fsc.

However, this shortfall is compensated for by adding three more delay circuits of Mπ, forming an IH delay line as a whole.

As explained above, the present invention uses the color signal C13- to obtain a color signal subjected to vertical contour correction by the circuit shown in FIG. In this case, the color signal becomes a correction signal corresponding to the middle line of the three scanning lines, so in this circuit section, it becomes a signal delayed by IH with respect to the real-time luminance signal.

However, by delaying the luminance signal in advance by IH compared to the chrominance signal in the circuit section shown in FIG. 2, the time axes of the chrominance signal and the luminance signal eventually coincide. Note that the circuit configurations shown in FIGS. 2 and 3 are not limited to these, and various embodiments are possible. Vertical contour correction of color signals does not necessarily need to be performed in the demodulator.

〔Effect of the invention〕

As mentioned above, the time delay for the luminance signal due to the vertical contour correction of the color signal is compensated for by delaying the luminance signal in the delay circuit of the Y/C separation circuit. Vertical contour correction of the signal can be realized. At this time, if the luminance signal is delayed separately in order to match the time axes of the luminance signal and the chrominance signal, a RAM of approximately 14-7.5 kbits (when the word length of the luminance signal is 8 bits) or Although a shift register is required, according to the present invention, such components and their cost can be reduced. Moreover, in order to delay the color signal by 2H, approximately 3.2 bits of RAM (when the word length of the color signal is 7 bits) is required.
Alternatively, a shift register can be used, which is advantageous in improving image quality and reducing costs.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the overall configuration of a television receiver according to the present invention, and FIGS. 2 and 3 are circuit diagrams showing a Y/C separation circuit and a color signal processing circuit in an embodiment of the present invention. ,
FIG. 4 is an explanatory diagram showing digital color signals and demodulation timing pulses. 11...Analog-digital converter, 13...Y/C
Separation circuit, 17...color signal processing circuit. Applicant's agent Patent attorney Takehiko Suzue 15-

Claims (1)

[Scope of Claim] A digital television circuit that converts an analog video signal into a quantized digital video signal and performs signal processing, wherein the analog video signal is converted to a quantized digital video signal at a frequency four times the color subcarrier frequency and a predetermined hue. An analog-to-digital converter outputs a sampled and quantized digital video signal at a timing synchronized with the phase of the axis, and a one-horizontal period delay circuit to which the digital video signal is input. a luminance/chromaticity separation circuit that performs subtraction using a subtracter, adds the signals on the input side and the output side using an adder, and outputs a digital chrominance signal and a digital luminance signal whose phase is one horizontal period ahead of the digital chrominance signal; At least one latch means for inputting the digital color signal after undergoing gain adjustment, and latching and outputting data of a predetermined phase from among the digital color signals, and output signals from the latch means are inputted and sequentially delayed by one thousand cycles. A delay circuit outputs three signals (BJ, B2.B, 9) with different times, and the three signals are inputted to -B+2B2-B,? 1. A digital technology circuit comprising: arithmetic means for outputting a vertical contour signal by an arithmetic operation.