JPH06140601A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase memory cell current and improve speed by shortening only the effective gate length of the depletion type memory transistor of a NAND type memory cell array arranged in matrix. CONSTITUTION:Among gate electrodes 1A which have a multilayer structure, E-type memory transistors Tr1, Tr3 and Tr4 have the same width bottom layer polysilicon 5 and the top layer silicide 6 and a D-type memory transistor Tr2 is formed of polysilicon 5 which has a narrow width compared with the silicide 6. Among the plurality of insulating gate type transistors arranged in series, the effective channel length between the source and the drain of the D-type memory transistor Tr2 is shortened. Therefore, memory cell current that flows through the D-type memory transistor Tr2 is increased and as a result, the operation speed is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a mask ROM using NAND type memory cells.
The present invention relates to a memory cell structure for realizing (Mask Programmable Read-Only-Memory) speedup.

[0002]

2. Description of the Related Art Currently, a large-capacity mask R of 4 Mbits or more
In OM, the number of GND lines is small because of high integration N
It is common to use an AND type memory cell. First, the NAND type memory cell eye will be described. 7A and 7B are a plan view and a sectional view, respectively, showing the structure of a general NAND type memory cell array. In the figure, T _{r11 to} T _r35 are a plurality (15 = 5 × 3 in the figure) of memory transistors arranged in a matrix of a plurality of rows (five rows in the figure) and a plurality of columns (three columns in the figure). , These are composed of MOS transistors. WL ₁ ~
WL ₅ is a word line, each of which is formed integrally with the gate electrodes 1 of the plurality of memory transistors arranged in the corresponding row. 2 ₁₁ , 2 ₂₁ and 2 ₃₁ are drain regions, and 2 ₁₆ , 2 ₂₆ and 2 ₃₆ are source regions. B
L ₁ , BL ₂ , BL ₃ are drain regions 2 ₁₁ , respectively.
Bit lines connected to 2 ₂₁ and 2 _{31 through} contact holes. Memory transistors T _{r11 to} T _r15 , T _r21 to
T _r25 and T _{r31 to} T _{r35 share} the source / drain regions 2 ₁₂ to 2 ₁₅ , ₂₂₂ 2 to 2 ₂₅ , 2 ₃₂ to 2 ₃₅ , respectively, and are connected in series. Further, 4 is a substrate on which the above-mentioned drain region, source / drain region and source region are formed, and 3 is a gate insulating film of each memory transistor formed on this substrate 4. The gate insulating film 3 is omitted in FIG.

In order to form a memory cell array having the above structure, an oxide film (not shown) for element isolation is formed on one main surface of the silicon substrate 4, and ion implantation is performed according to the information to be stored. Memory transistor T by a method such as
_Determine the type of _{r11 to Tr35} , and _select each memory transistor T
_r11 After the gate electrode 1 through T _r35 are formed integrally with the word line WL ₁ to WL _5, each memory transistor T _r11 through T _r35
The drain region, the source / drain region and the source regions 2 ₁₁ to 2 ₃₆ are formed by, for example, diffusion. Next, contact holes are formed in the drain regions 2 ₁₁ , 2 ₂₁ , and 2 ₃₁ , which are connected to the bit lines BL ₁ , BL ₂ , and BL ₃ , respectively, and finally a protective film (not shown) is provided.

Next, the operation will be described. NAN in Figure 7
In the D-type memory cell array, for example, when selecting the memory transistor T _r22 , the memory transistor T _r22 is selected.
_The word line WL ₂ which is the gate electrode 1 of _r22 is set to a low level (“L”, usually ground potential), and the other non-selected memory transistors T _{r1n to} T _r3n (n = 1, 3, 4,
5) Word lines WL ₁ , WL _{3 to} W which are the gate electrodes 1
The L ₅ high level ( "H", normal power supply potential Vcc) to. The memory transistor T _r22 selected at this time is
When the information to be stored, that is, the writing information is “1”, it is made into a D type (depletion type) of OV or lower by, for example, an ion implantation method, and when it is “0”, E of OV or higher.
Type (enhancement type). FIG. 7C is a graph showing the relationship between the gate voltage Vgs of the memory transistor and the source / drain current Ids flowing in its channel. In the E type, since the memory transistor is off when the gate voltage Vgs is at the “L” level,
Although the drain current Ids does not flow, when the gate voltage Vgs is at “H” level, the memory transistor is turned on and the source / drain current Ids flows. On the other hand, in the D type, the source / drain current Ids constantly flows regardless of whether the gate voltage Vgs is the “L” level or the “H” level.

If the selected memory transistor T _r22 is of the D type, the source / drain current flows (ON state) even if the gate voltage is at the “L” level when the transistor is selected, as described above. In the case of the E type, no current flows at the "L" level (OFF state). At this time, the other non-selected memory transistors T _{r1n to} T _r3n (n =
1, 3, 4, 5) are in the ON state regardless of the stored contents because each gate voltage is at the “H” level, and therefore the potential of the bit line BL _{2 depends on} the stored contents of the memory transistor Tr _22. Is determined. That is, the potential of the bit line BL ₂ becomes “L” level when the stored information, that is, read information of the memory transistor T _r22 is “1” and becomes “H” level when it is “0”, which is connected to the subsequent stage. The signal is transmitted to the sense amplifier (not shown) and "0" or "1" is determined. In this way, the memory transistor T _r22 is selected.

[0006]

In the conventional semiconductor memory device as described above, since the memory transistors of the NAND type memory cell are connected in series, the memory cell current depends on the ON resistance of each transistor. When the resistance becomes high, it takes time to fully discharge the potential of the bit line, which hinders the speeding up of the operation.

The present invention has been made in order to solve such a problem, and changes the type and hence the shape of the memory transistor in accordance with the contents to be stored, thereby increasing the memory cell current to perform a high speed operation. The purpose is to obtain a semiconductor memory device.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising:
The gate length of the conductor of the first memory transistor of the first
Is shorter than the gate length of the conductor, and the distance between the source and drain of the second memory transistor is shorter than the distance between the source and drain of the first memory transistor.

In the semiconductor memory device according to claim 2 of the present invention, the source / drain region of the first memory transistor has a plurality of impurity concentrations, whereas the source / drain region of the second memory transistor has a single impurity concentration. It has an impurity concentration of.

[0010]

According to the first aspect of the invention, the effective channel length between the source and drain is changed according to the contents stored in the memory transistor to reduce the on-resistance of the second memory transistor. The memory cell current increases.

According to the second aspect of the present invention, the side wall formed to increase the withstand voltage of the memory transistor is removed according to the contents to be stored in the memory transistor to reduce the on-resistance of the second memory transistor. As a result, the memory cell current increases.

[0012]

EXAMPLES Example 1. 1 is a sectional view showing a first embodiment of a semiconductor memory device according to the present invention, and the same reference numerals as those in FIG. 7 designate the same or corresponding portions. In the figure, T _r1 ~
T _r4 is a memory transistor, and in the laminated gate electrode 1A, a transistor T _r1 in which a lower first conductor such as polysilicon 5 and an upper second conductor such as a silicide material 6 have the same width, T _r3 and T _r4 are the first memory transistors, for example, E-type memory transistors, and the polysilicon 5 in the lower layer is narrower than the silicide material 6 in the upper layer.
Transistor T _r2 is a second D-type memory transistor, for example. Memory transistors require a minimum channel length to function properly and not cause short channel effects. When the channel length is shorter than the minimum channel length, the memory transistor leaks. On the contrary, when the channel length is sufficiently long, the ON resistance becomes high. Particularly, in the D-type memory transistor, the ON resistance causes the memory cell to leak. The current is reduced, which hinders high-speed operation. Therefore, the effective channel length is selectively shortened only for the D-type memory transistor to prevent the short-channel effect of the E-type memory transistor and reduce the on-resistance of the D-type memory transistor.

Next, a method of manufacturing the semiconductor memory device shown in FIG. 1 will be described with reference to FIG. First, in process P1, an oxide film (not shown) for element isolation is formed on the silicon substrate 4, and in process P2, ion implantation for once making the entire memory transistor into E type is performed. Next, process P
In step 3, ion implantation for selectively forming desired D-type memory transistor T _r2 is performed on desired information, and process P is performed.
The gate electrode 1A is formed at 4. At this time, the E-type and D-type memory transistors T _{r1 to} T _{r4 have the} same shape, and the polysilicon 5 and the silicide material 6 are stacked in this order and patterned. Next, in process P5, the glass mask used in process P2 is used to perform selective masking again, and etching is performed to expose only the D-type memory transistor _Tr2 . At this time, the etching rates of the polysilicon 5 and the silicide material 6 are adjusted to be different, and the gate length of the polysilicon 5 is made shorter than that of the silicide material 6. next,
In process P6, ion implantation is performed to form a diffusion region of each memory transistor. At this time, an angle (incident angle) is provided for ion implantation to implant ions into the gate step of the D-type memory transistor _Tr2 . And process P
After forming the interlayer film in 7, contact holes are opened,
In process P8, a metal wiring to be the bit line BL ₂ is provided,
Finally, in process P9, a protective film is formed.

As described above, according to the first embodiment, the effective channel length between the source and drain of the D-type memory transistor T _r2 among the plurality of insulated gate transistors arranged in series is shortened. The memory cell current flowing through the D-type memory transistor T _r2 increases, and as a result, the operating speed improves.

Next, another method of manufacturing the semiconductor memory device shown in FIG. 1 will be described with reference to FIG. In the manufacturing method of the first embodiment described above, the step of ion implantation for forming the D-type memory transistor T _r2 was performed before the gate formation. Here, however, this step is performed by ion implantation from above the gate electrode material after the gate formation. ITP method (Ion Implant ThroughP)
olysilicon).

If the IITP method is used, in the process flow of FIG. 3, an oxide film for element isolation is formed on the silicon substrate 4 in the process P1, and ion implantation is performed in the process P2 to once make the entire memory transistor into the E type. After forming the gate electrode 1A in process P4, the D-type memory transistor T _{r2 is} selectively selected for desired information.
Selective etching (process P5) and ion implantation (process P3) for forming the mask can be performed, and the number of times of mask alignment can be completed once, and the process and the construction period can be shortened. After that, if processes P6 to P9 are performed in the same manner as in the first embodiment, the final memory transistors T _{r1 to} T _r4 become the same as those in the first embodiment, and the same effect can be obtained.

Example 2. FIG. 4 is a sectional view showing a second embodiment of the present invention, and the same reference numerals as those in FIG. 1 denote the same or corresponding portions. In the figure, an LDD (Lightl) in which a side wall such as an oxide film 7 is formed on the side surface of the gate electrode 1A
y Doped Drain) Structured memory transistor T
_r1 , T _r3 and T _r4 are E-type memory transistors, and the memory transistor T _r2 having no oxide film 7 on the side surface of the gate electrode 1A is a D-type memory transistor. Here, the LDD structure will be described. LDD is a well-known technique for increasing the gate breakdown voltage by changing the impurity concentration in the source / drain region between the vicinity of the gate electrode 1A and the other portions. The manufacturing method is
Before generating the oxide film 7 on the side surfaces of the gate electrodes 1A, once the soft-doped low source-drain region S2 ₂₂ impurity concentration of, S2 _24, S2 ₂₅ is formed, after forming an oxide film 7 on the gate electrode side wall is to form the original source and drain regions 2 _{22-2 25} by ion implantation. L
By adopting the DD structure, even if the gate length is shortened, the gate breakdown voltage is maintained and leakage is prevented. However, on the other hand, on the other hand, the region S2 ₂₂ formed by soft doping,
Since S2 ₂₄ and S2 ₂₅ have high resistance, they become a factor for increasing the on-resistance in the D-type memory transistor. Therefore, in this embodiment, the gate electrode 1 is provided only for the D-type memory transistor T _r2 .
The oxide film 7 on the side surface of A is selectively removed, and source / drain implantation is also performed on a region to be formed by soft doping.
The on resistance is kept low.

Next, a method of manufacturing the semiconductor memory device shown in FIG. 4 will be described with reference to FIG. First, in process P1, an oxide film (not shown) for element isolation is formed on the silicon substrate 4, and in process P2, ion implantation is performed to make the entire memory transistor once E-type. Next, in process P3, ion implantation for selectively forming desired D-type memory transistor T _r2 is performed with respect to desired information, and in process P4, gate electrode 1A is formed. In this case the gate electrode 1A are E-type, D-type memory transistor T _r1 through T _r4 polysilicon 5 are both in the same shape, they are stacked in this order silicide material 6 is patterned. Next, in process P10, soft doping is performed using the gate electrode 1A as a mask to form regions S2 ₂₂ , S2 ₂₄ , S2 ₂₅ having a low impurity concentration, and in process P11, the oxide film 7 is formed on the side surface of the gate electrode 1A.
To form. Then, in process P5, process P3
The oxide film 7 on the side surface of the gate electrode 1A is removed only for the D-type memory transistor _Tr2 using the mask used in
After that, the device is completed through processes P6 to P9 in the same manner as in the first embodiment. Thus, according to the second embodiment,
Among the plurality of insulated gate transistor arranged in series, so excluding the oxide film 7 of the gate electrode side is formed to increase the breakdown voltage with respect to D-type memory transistor T _r2, of the D-type memory transistor T _r2 The on-resistance is reduced, the memory cell current flowing through the D-type memory transistor T _r2 is increased, and as a result, the operation speed is improved.

Next, another method of manufacturing the semiconductor memory device shown in FIG. 4 will be described with reference to FIG. In the above-described manufacturing method of the second embodiment, the step of ion implantation for forming the D-type memory transistor T _r2 is performed before the gate is formed, but here, this step is performed after the gate is formed by using the ITIP method. is there.

In the process flow of FIG. 6, in process P1, an oxide film is formed on the silicon substrate 4 for element isolation, and in process P2, the entire memory transistor is once etched.
Ion implantation for forming a mold is performed, a gate electrode 1A is formed in a process P4, soft doping is performed to form a region having a low impurity concentration in a process P10, and an oxide film 7 is formed on a side surface of the gate electrode in a process P11. After forming,
Selective D-type memory transistor T for desired information
After forming _r2 , selective etching (process P5) and ion implantation (process P3) for removing the oxide film 7 on the side surface of the gate electrode of the D-type memory transistor T _r2 are performed, and thereafter, in the same manner as in the first embodiment. Process P6 to P9
Then, the final shape of the memory transistors T _{r1 to} T _r4 becomes the same as that of the second embodiment, and the same effect can be obtained.

Example 3. Further, in the above-described embodiment, the NAND type memory in which information is stored by the E type memory transistor and the D type memory transistor has been described.
The same effect can be obtained with a NAND memory in which the source and the drain are punch-through conducted instead of the D-type memory transistor.

[0022]

According to the first aspect of the present invention, the gate length of the first conductor of the second memory transistor is made shorter than the gate length of the first conductor of the first memory transistor. Since the distance between the source and drain of the second memory transistor is shorter than the distance between the source and drain of the first memory transistor, the on-resistance of the second memory transistor is reduced, and the memory cell current is reduced. Is increased and the operation speed can be increased.

According to a second aspect of the present invention, in the semiconductor memory device, the source / drain region of the first memory transistor has a plurality of impurity concentrations, whereas the source / drain region of the second memory transistor has a single impurity concentration. Since the second memory transistor has the above impurity concentration, the on-resistance of the second memory transistor is lowered, which in turn increases the memory cell current, and has the effect of speeding up the operation.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a process flow illustrating a method for manufacturing the first embodiment of the present invention.

FIG. 3 is a process flow explaining another method of manufacturing the first embodiment of the present invention.

FIG. 4 is a sectional view showing a second embodiment of the present invention.

FIG. 5 is a process flow for explaining a method of manufacturing the second embodiment of the present invention.

FIG. 6 is a process flow explaining another method of manufacturing the second embodiment of the present invention.

FIG. 7 is a diagram showing a conventional semiconductor memory device,
(A) and (b) are a plan view and a sectional view, respectively, showing the memory cell structure, and (c) is a diagram showing current characteristics during operation.

[Explanation of symbols]

T _r1 through T _r4 memory transistor 1A gate electrode 2 _{22-2 25} source and drain regions 5 of polysilicon 6 silicide material

Claims (2)

[Claims] 1. A first memory transistor, which is rendered non-conductive by receiving a low level signal when a transistor is selected, and a second memory transistor, which is rendered conductive by receiving the low level signal, are arranged in a matrix. A semiconductor memory device having a structure in which the gate electrodes of the first and second memory transistors have a structure in which a second conductor having a resistance value lower than that of the first conductor is laminated on the first conductor. The gate length of the conductor of the first memory transistor is shorter than the gate length of the first conductor of the first memory transistor, and the distance between the source and the drain of the second memory transistor is set to the source and the drain of the first memory transistor. A semiconductor memory device characterized in that the distance is shorter than the interval. 2. A semiconductor memory device in which a first memory transistor which is rendered non-conductive by receiving a low level signal when a transistor is selected and a second memory transistor which is rendered conductive by receiving the low level signal are arranged in a matrix. At
A semiconductor memory device, wherein the source / drain region of the first memory transistor has a plurality of impurity concentrations, while the source / drain region of the second memory transistor has a single impurity concentration.