JP2002368137A - Production method for semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a production method for semiconductor memory device, with which data can be programmed in the latter half of a production process and the data contents are difficult to analyze. SOLUTION: In each of memory cells, an n-type MOS transistor Q10a or a p-type MOS transistor Q10b is formed corresponding to the stored state. Since the n-type MOS transistor Q10a is operated as an ordinary n-type MOS transistor, it is turned on, by supplying a gate voltage which is higher than the threshold voltage. In the n-type MOS transistor Q10b, the p-type impurity of low concentration is introduced in an LDD region 8, and since drain side and source side n+ impurity regions 10 are separated from a channel-forming region by such a p- impurity region, the gap of drain and source is held in off state, even if the gate voltage is impressed. Since the LDD region 8 is formed later than a gate electrode 4, TAT from programming to forwarding can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a mask ROM (Read Only).
y Memory).

[0002]

2. Description of the Related Art Conventionally, a memory for storing data that does not need to be changed in a normal operation, such as an operating system (OS) of a device incorporating a microcomputer and data for device control, includes (1) OTP. ROM (o
One that can be electrically written only once, such as ne time programmable ROM, (2) One that can be electrically written multiple times, such as flash memory, (3) There are types such as a mask ROM in which the stored contents cannot be changed after the stored contents are written at the time of manufacturing.

[0003] The type (1) OTPROM and the type (2) flash memory can write the stored contents after the device is manufactured. It is used for short production early products. However, since the number of elements is increased and the chip size is increased due to a rewriting circuit including a high breakdown voltage transistor and the like, there is a problem that the cost increases. In addition, since the chip size and current consumption increase, it may not be possible to use the device even in the development stage.

The manufacturing process of the type (3) mask ROM is inexpensive because the manufacturing process is the same as that of a standard logic circuit or a process of adding about one mask thereto. Further, since a memory cell does not include a writing circuit and the number of elements of the circuit is small and the structure is simple as compared with the above-described OTPROM or flash memory, the cost for storage capacity is low and the degree of integration is easily increased. . Further, since stored data can be written to a large amount of memory at a time in the manufacturing process, the manufacturing cost for programming the memory is low and the mass productivity is excellent. Because of these advantages, there is no need to modify the stored data after development has ended,
This mask ROM is usually used in equipment that is regularly mass-produced.

[0005]

Here, three types of mask ROMs generally used conventionally will be described with reference to FIGS.

FIG. 15 is a schematic circuit diagram for explaining a first conventional mask ROM. The first shown in FIG.
The mask ROM has 18 memory cells MCjka arranged in a matrix of 6 rows and 3 columns, six word lines WLj connected to memory cells MCjka in the same row of the matrix, and a memory of the same column in the matrix. Cell MCjka
And three bit lines BLk connected thereto. Here, j represents an integer of 1 ≦ j ≦ 6, and k represents an integer of 1 ≦ k ≦ 3.

Each memory cell MCjka has an n-type MOS transistor Q1a or an n-type MOS transistor Q1b whose threshold voltage is adjusted according to the storage state.
The source of the n-type MOS transistor is connected to a ground line, and the drain is connected to a bit line BLk corresponding to each memory cell MCjka. The gate is connected to a word line WLj corresponding to each memory cell MCjka.

FIG. 16 shows the first mask RO shown in FIG.
M shows a schematic cross-sectional view of two adjacent memory cells MC32a and MC42a. The memory cells MC32a and MC42a have n-type MOS transistors Q1a and n1 having different thresholds.
Type MOS transistors Q1b are formed.

In these n-type MOS transistors Q1a and Q1b, gate insulating film 3 is formed on the surface of p-type semiconductor substrate 1,
A gate electrode 4 is formed via the gate insulating film 3.

On both sides of the gate electrode 4, side wall insulating films 9 are formed. An LDD doped with a relatively low concentration of an n-type impurity is formed in a surface region of the semiconductor substrate 1 facing the sidewall insulating film 9 via the gate insulating film 3.
(Lightly doped drain) regions 6 are formed corresponding to the respective sidewall insulating films 9.

In the surface region of the semiconductor substrate 1 in contact with the LDD region 6, an n + impurity region 10 into which a higher concentration of n-type impurities is introduced than in the LDD region 6 is formed. Adjacent memory cell MC32a and memory cell MC42a
, The drain side n + impurity region 10 of each n-type MOS transistor is shared.

N-type MOS transistor Q1a and n-type MOS transistor Q1b formed on semiconductor substrate 1
Is covered with an interlayer insulating film 11, and a wiring 13 (bit line BL <b> 2) is formed on the interlayer insulating film 11. The wiring 13 is connected to the drain side n via a contact 12 formed through the interlayer insulating film 11.
+ Impurity region 10.

The source side n + impurity region 10
The n + impurity region 10 on the drain side is shared by another two memory cells adjacent to the non-shared side. For example, in the examples of FIGS. 15 and 16, the source side n + impurity region 10 of the memory cell MC32a is shared with the source side n + impurity region 10 of the memory cell MC22a, and the source side n + impurity region 1 of the memory cell MC42a.
0 is the source side n + impurity region 1 of the memory cell MC52a
Shared with 0. This shared n + impurity region 1
0 is shared by the memory cells in the same row,
Further, they are electrically connected to a common ground potential line (not shown).

The threshold voltages of n-type MOS transistor Q1a and n-type MOS transistor Q1b are
In an impurity introduction step for adjusting a threshold voltage (also referred to as a channel doping step) performed after the formation of the field insulating film, control is performed in accordance with an introduction amount of an impurity (for example, boron). In the example of FIG. 15 and FIG.
These two n transistors are set such that the threshold voltage of S transistor Q1b is higher than that of n-type MOS transistor Q1a.
Different concentrations of impurities are introduced into the active region of the type MOS transistor.

For example, when the threshold voltage of the n-type MOS transistor Q1a is about 3V,
When the threshold voltage of b is set to 5 V or more, when a voltage of about 3 V is applied to each of the word line WLj and the bit line BLk of the storage address to be read,
The n-type MOS transistor Q1a is turned on, and the n-type MOS
Transistor Q1b is turned off. Therefore, n
A low-level voltage is output to the bit line BLk connected to the drain of the type MOS transistor Q1a, and a high-level voltage is output to the bit line BLk connected to the drain of the n-type MOS transistor Q1b. Thus, the first mask R
In the OM, data is stored according to a difference in threshold voltage of an n-type MOS transistor included in each memory cell.

Next, a second conventional mask ROM will be described. FIG. 17 is a schematic circuit diagram for explaining a conventional second mask ROM. Similar to the first mask ROM shown in FIG. 15, the second mask ROM shown in FIG. 17 includes memory cells MCjkb arranged in a matrix of 6 rows and 3 columns, and memory cells MCj in the same row of the matrix.
kb, and a bit line BLk connected to a memory cell MCjkb in the same column of the matrix.
And

Each memory cell MCjkb has an n-type MOS transistor Q2. The drain of the n-type MOS transistor Q2 is connected to the bit line BLk corresponding to each memory cell MCjkb or is disconnected according to the storage state. The gate is connected to a word line WLj corresponding to each memory cell MC, and the source is connected to a ground line.

FIG. 18 shows the second mask RO shown in FIG.
M shows a schematic cross-sectional view of two adjacent memory cells MC32b and MC42b. An n-type MOS transistor Q2 is formed in each of the memory cell MC32b and the memory cell MC42b.
These n-type MOS transistors are separated by a field insulating film 18 formed on the surface of the semiconductor substrate 1.

In the n-type MOS transistor Q2, the gate insulating film 3 is formed on the surface of the p-type semiconductor substrate 1 not covered by the field insulating film 18, and the gate electrode 4 is formed via the gate insulating film 3. Is formed.

Sidewall insulating films 9 are formed on both sides of the gate electrode 4. In the surface region of the semiconductor substrate 1 facing the sidewall insulating film 9 via the gate insulating film 3, LDD regions 6 doped with a relatively low concentration of n-type impurities correspond to the respective sidewall insulating films 9. Is formed.

In the surface region of the semiconductor substrate 1 that is in contact with the LDD region 6, an n + impurity region 10 into which a higher concentration of n-type impurities is introduced than in the LDD region 6 is formed. Adjacent memory cell MC32b and memory cell MC42b
At n + on the drain side of the n-type MOS transistor
The impurity regions 10 are separated from each other by a field insulating film 18.

The surface of the n-type MOS transistor Q2 formed on the semiconductor substrate 1 is covered with an interlayer insulating film 11, and a wiring 13 (bit line BL2) is formed on the interlayer insulating film 11. . Also, the interlayer insulating film 11
Is formed in accordance with the storage state of the memory cell, and the n + impurity region 10 on the drain side and the wiring 13 are electrically connected via the contact 12. That is, the n + impurity region 10 on the drain side is in a state of being connected to or separated from the wiring 13 via the contact 12, depending on the storage state of the memory cell. In the example of FIG.
In C32b, the n + impurity region 10 on the drain side and the wiring 13 are connected, and in the memory cell MC42b, they are disconnected.

The source side n + impurity region 10 is
The n + impurity region 10 on the drain side is the field insulating film 1
8 is shared by two memory cells adjacent on the side not separated by 8. This shared n + impurity region 10 is shared by the memory cells in the same row, and is further electrically connected to a common ground potential line (not shown).

Second mask ROM having the above configuration
, A voltage is applied to the word line WLk corresponding to the address to be read to turn on the n-type MOS transistor Q2 of each memory cell, and the bit line B
When a pull-up voltage is applied to Lj, when the bit line BLk (wiring 13) and the n + impurity region 10 on the drain side are connected via the contact 12, the channel formation region of the n-type MOS transistor Q is changed. A current flows from the bit line BLk to the ground potential via the bit line BLk, so that the voltage of the bit line BLk becomes low level. When the contact 12 is not formed, no current flows from the bit line BLk to the ground potential, so that the voltage of the bit line BLk is at a high level. Thus, in the second mask ROM, data is stored in accordance with the presence or absence of the contact 12 connecting the bit line BLk and the drain of the n-type MOS transistor.

Next, a third conventional mask ROM will be described. FIG. 19 is a schematic circuit diagram for explaining a third conventional mask ROM. The third mask ROM shown in FIG. 19 is a mask ROM shown in FIGS.
Similarly, memory cells MCjkc arranged in a matrix of 6 rows and 3 columns and memory cells M in the same row of the matrix
The word line WLj connected to Cjkc and the bit line B connected to memory cells MCjkc in the same column of the matrix
Lk.

Each memory cell MCjkc has, similarly to the mask ROM shown in FIG. 15, an n-type MOS transistor Q3a or an n-type MOS transistor Q3b whose threshold voltage is adjusted according to the storage state. The source of the n-type MOS transistor is connected to a ground line, and the drain is connected to a bit line BLk corresponding to each memory cell MCjkc. The gate is connected to each memory cell MCjk
It is connected to the word line WLj corresponding to c.

FIG. 20 shows the first mask RO shown in FIG.
M shows a schematic cross-sectional view of two adjacent memory cells MC32c and MC42c. The memory cells MC32c and MC42c have n-type MOS transistors Q3a and Q3a having different thresholds.
Type MOS transistors Q3b are respectively formed.

In the surface region of the p-type semiconductor substrate 1 where these n-type MOS transistors are formed, a field insulating film 18 is formed according to the storage state of the memory cell. The gate insulating film 3 is formed on the surface of the semiconductor substrate 1 where the field insulating film 18 is not formed. The gate electrode 4 of the n-type MOS transistor Q3a is formed on the surface of the semiconductor substrate 1 via the field insulating film 18, and the gate electrode 4 of the n-type MOS transistor Q3a is connected to the semiconductor via the gate insulating film 3. It is formed on the surface of the substrate 1.

On both sides of the gate electrode 4, side wall insulating films 9 are formed. An LDD doped with a relatively low concentration of an n-type impurity is formed in a surface region of the semiconductor substrate 1 facing the sidewall insulating film 9 via the gate insulating film 3.
Regions 6 are formed corresponding to the respective side wall insulating films 9.

In the surface region of the semiconductor substrate 1 in contact with the LDD region 6, an n + impurity region 10 into which a higher concentration of n-type impurities is introduced than in the LDD region 6 is formed. Adjacent memory cell MC32b and memory cell MC42b
At n + on the drain side of the n-type MOS transistor
Impurity regions 10 are shared with each other.

N-type MOS transistor Q3a and n-type MOS transistor Q3b formed on semiconductor substrate 1
Has a surface covered with an interlayer insulating film 11, and a wiring 13 (bit line BL2) is formed on the interlayer insulating film 11. The wiring 13 is connected to the drain side n by the contact 12 formed through the interlayer insulating film 11.
+ Impurity region 10.

The source side n + impurity region 10
The n + impurity region 10 on the drain side is shared by two memory cells adjacent to the non-shared side.
The shared n + impurity region 10 is shared by the memory cells in the same row, and is further electrically connected to a common ground potential line (not shown).

The n-type MOS transistor Q3b has an n-type M
Since the distance between the gate electrode 4 and the channel formation region is separated by the field insulating film 18 as compared with the OS transistor Q3a, the threshold voltage of the n-type MOS transistor Q3b is larger than that of the n-type MOS transistor Q3a. Therefore, also in the first mask ROM, data is stored according to the difference in the threshold voltage of the n-type MOS transistor included in each memory cell, as in the first mask ROM shown in FIG.

The first to third masks R
OM has the following problems. First mask R
In the OM, the storage data writing process is performed in a channel doping process. Since this process is performed at an early stage of a mask ROM manufacturing process, a period from when the storage data to be written is received from a user to when the manufacturing is completed is completed. (TAT: also known as turn around time) has a problem that it is prolonged.

In a normal logic circuit manufacturing process, a single concentration of impurity is uniformly introduced into an active region in a channel doping process. However, in a first mask ROM manufacturing process, stored data is A dedicated mask for introducing an impurity of a corresponding concentration into each memory cell is required. As a result, there is a problem that the manufacturing cost increases as compared with the normal manufacturing process.

Further, in the second mask ROM, the writing process of the stored data is performed in the contact forming step in the latter half of the manufacturing step rather than the channel doping step. Therefore, the TAT should be shortened as compared with the first mask ROM. Can be. Also, in this contact manufacturing step, the second
Since there is no need to manufacture a dedicated mask for the mask ROM, the cost for this mask can be reduced. However, since the presence or absence of a contact corresponds to the content of the stored data, there is a problem that the content of the stored data is easily analyzed. That is, there is a problem that tamper resistance is low.

In the third mask ROM, the memory data is written in the element isolation step in the first half of the channel doping step. Therefore, it is not necessary to prepare a dedicated mask.
There is a problem that it becomes longer than M. Further, since the presence or absence of the field insulating film for element isolation corresponds to the content of the stored data, there is a problem that the tamper resistance is low.

As described above, the conventional mask ROM has a problem that short TAT and high tamper resistance cannot be achieved at the same time. Also, when the TAT is short,
A dedicated mask for a mask ROM, which is not used in a normal logic circuit manufacturing process, is required, which causes a problem of increasing the manufacturing process cost.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor memory device in which storage data writing processing can be performed in the latter half of the manufacturing process, and it is difficult to analyze the contents of storage data. It is to provide a manufacturing method thereof.

[0040]

In order to achieve the above object, a method of manufacturing a semiconductor memory device according to a first aspect of the present invention comprises a drain region and a source region sandwiching a channel formation region on a semiconductor substrate. A step of forming the gate insulating film on the channel forming region, a step of forming a gate electrode on the gate insulating film, and forming the gate region on the drain region and the source region. Introducing a first concentration impurity having a conductivity type according to a storage state, forming an insulator sidewall on a side portion of the gate electrode, and removing a region covered by the insulator sidewall. Introducing a second concentration of impurities higher than the first concentration into the drain region and the source region except for the first region.

According to the method for manufacturing a semiconductor memory device according to the first aspect of the present invention, the gate insulating film is formed on the channel formation region, and the gate electrode is formed on the gate insulating film. Next, the first concentration impurity having a conductivity type according to a storage state is introduced into the drain region and the source region. Next, the insulator sidewall is formed on a side portion of the gate electrode, and a second concentration higher than the first concentration is applied to the drain region and the source region excluding a region covered by the insulator sidewall. Is introduced.

Further, a mask for separating a region in contact with the channel formation region and a region not in contact with the channel formation region and covering at least a part of the drain region or the source region may be formed according to the storage state. There may be a step of forming. In this case, the step of introducing the second impurity may be performed by introducing the second concentration impurity into the drain region and the source region except for the region covered with the insulator sidewall and the mask. good.

In addition, a region that separates a region that is in contact with the channel formation region from a region that is not in contact with the drain region or at least a part of the source region has a conductivity type according to the storage state. The method may include a step of introducing impurities.

A method of manufacturing a semiconductor memory device according to a second aspect of the present invention is a method of manufacturing a semiconductor memory device having a drain region and a source region with a channel formation region on a semiconductor substrate interposed therebetween, wherein Forming a gate insulating film on a formation region, forming a gate electrode on the gate insulating film, and introducing a first concentration of impurity into the drain region and the source region according to a storage state. Performing a step of forming an insulator sidewall on a side portion of the gate electrode, and separating a region that is not in contact with a region that is in contact with the channel formation region, wherein at least one of the drain region and the source region is separated. Forming a mask for covering a part of the region from the front side of the semiconductor substrate according to the storage state; To the drain region and the source region excluding the region covered Le and the mask, and a step of introducing impurities of the higher than first concentration second concentration.

According to the method for manufacturing a semiconductor memory device according to the second aspect of the present invention, a gate insulating film is formed on the channel region, and the gate electrode is formed on the gate insulating film. Next, the first concentration impurity is introduced into the drain region and the source region according to the storage state. Next, the insulator sidewall is formed on a side portion of the gate electrode, and is a region that separates a region that is in contact with the channel formation region from a region that is not in contact with the channel region, and at least a part of the drain region or the source region. A mask for covering the region from the front side of the semiconductor substrate is formed according to the storage state. Next, in the drain region and the source region excluding the region covered with the insulator sidewall and the mask,
A second concentration of impurities higher than the first concentration is introduced.

In addition, a region that separates a region that is in contact with the channel formation region from a region that is not in contact with the channel formation region, wherein at least a part of the drain region or the source region has a conductivity type according to the storage state. The method may include a step of introducing impurities.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic circuit diagram illustrating an example of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device shown in FIG. 1 has 18 memory cells MCmn arranged in a matrix of 6 rows and 3 columns, and 6 word lines W connected to memory cells MCmn in the same row of the matrix.
Lm, and three bit lines BLn connected to the memory cells MCmn in the same column of the matrix. Where m
Represents an integer of 1 ≦ m ≦ 6, and n represents an integer of 1 ≦ n ≦ 3.

Each memory cell MCmn has an n-type MOS transistor Q10a or an n-type MOS transistor Q10b according to the storage state. The n-type MOS transistor Q10a operates as a normal transistor, but the n-type MOS transistor Q10b has a region between the channel forming region and the drain region (or source region) for preventing conduction between the drain and source, as described later. Therefore, no current flows between the drain and the source even if a voltage is supplied to the gate. That is, n-type MOS transistor Q10b does not function as a transistor.

The source of each of these n-type MOS transistors is connected to the ground line, and the drain is connected to each memory cell MC.
mn is connected to the corresponding bit line BLn. The gate is connected to a word line WLm corresponding to each memory cell MCmn.

FIG. 2 is a schematic sectional view for explaining an example of the structure of the semiconductor memory device according to the first embodiment of the present invention. In the example of FIG. 2, two adjacent memory cells MC32 and MC42 are shown.
The memory cells MC32 and MC42 have n
Formed MOS transistor Q10a and n-type MOS transistor Q10b are formed.

N-type MOS transistors Q10a and n
In the type MOS transistor Q10b, a gate insulating film 3 is formed on the surface of a p-type semiconductor substrate 1, and a gate electrode 4 is formed via the gate insulating film 3. A sidewall insulating film 9 is formed on both sides of the gate electrode 4.
Are formed.

In the drain region and the source region of the semiconductor substrate 1 facing the sidewall insulating film 9 of the n-type MOS transistor Q10a, LDD regions 6 doped with a relatively low concentration of n-type impurities are formed. . In the drain region and the source region of the semiconductor substrate 1 which are in contact with the LDD region 6, n + impurity regions 10 in which a higher concentration of n-type impurity is introduced than in the LDD region 6 are formed.

In the drain region and the source region of the semiconductor substrate 1 facing the side wall insulating film 9 of the n-type MOS transistor Q10b, LDD regions 8 doped with a relatively low concentration of p-type impurities are formed. . In the drain region and the source region of the semiconductor substrate 1 in contact with the LDD region 8, n + impurity regions 10 having the same concentration as that of the n-type MOS transistor Q10a are formed.

The n + impurity region 10 on the drain side is connected to the adjacent memory cells MC32a and MC42a.
Are shared with each other.

The above-described n-type M formed on the semiconductor substrate 1
The surfaces of the OS transistor 10a and the n-type MOS transistor 10b are covered with an interlayer insulating film 11, and a wiring 13 (bit line BL) is formed on the interlayer insulating film 11.
2) is formed. The wiring 13 is electrically connected to the drain side n + impurity region 10 via a contact 12 formed through the interlayer insulating film 11.

The n + impurity region 10 on the source side is
The n + impurity region 10 on the drain side is shared by another two memory cells adjacent to the non-shared side. For example, in the example of FIGS.
The source side n + impurity region 10 of C32 is a memory cell MC
The source-side n + impurity region 10 of the memory cell MC42 is shared with the source-side n + impurity region 10 of the memory cell MC52. This shared source side n + impurity region 10
It is shared by the memory cells in the same row, and is further electrically connected to a common ground potential line (not shown).

The difference between n-type MOS transistor Q10a and n-type MOS transistor Q10b having the above-described structure is the conductivity type of the LDD region.
That is, the n-type MOS transistor Q10a has a low concentration of n-type impurity introduced into the LDD region, and operates as a normal n-type MOS transistor having an LDD structure. Therefore, at the time of reading stored data, a gate voltage higher than the threshold voltage of n-type MOS transistor Q10a is supplied to word line WLm and bit line BL
When the pull-up voltage is supplied to n, the n-type MOS transistor Q10a turns on. As a result, a current flows from bit line BLn to the ground potential, and bit line BLn
Becomes low level.

On the other hand, in n-type MOS transistor Q10b, a low concentration of p-type impurity is introduced into the LDD region, and the n-type impurity region 10 on the drain side and the source side is formed by the p- impurity region. Since it is separated from the formation region, conduction between the drain and the source does not occur even when a gate voltage is applied. That is, n-type M
The OS transistor Q10b does not function as a transistor. Therefore, when reading stored data,
A gate voltage higher than the threshold voltage of n-type MOS transistor Q10a is supplied to word line WLm, and bit line B
Even if a pull-up voltage is supplied to Ln, n-type MOS transistor Q10b remains off. in this case,
Since no current flows from the bit line BLn to the ground potential, the voltage of the bit line BLn goes high.

As described above, at the time of reading the stored data, in the memory cell in which the n-type MOS transistor 10a is formed, the transistor is turned on, the bit line BLn becomes low level, and the memory cell in which the n-type MOS transistor 10b is formed. In this case, the transistor does not conduct, and the bit line BLn goes high. Each memory cell stores binary data corresponding to a transistor to be formed (n-type MOS transistor Q10a or n-type MOS transistor Q10b).

As described above, according to the semiconductor device shown in FIGS. 1 and 2, the data stored in each memory cell is set according to the conductivity type of the LDD region. It is very difficult to analyze in a short time, and high tamper resistance can be obtained.

Next, a method of manufacturing the semiconductor memory device according to the present invention having the structure shown in FIGS. 1 and 2 will be described with reference to FIGS.

First, as shown in FIG. 3, for example, LOCOS (local oxidation of silicon)
After forming a field insulating film (not shown) by the method,
A sacrificial oxide film 2 is formed. Then, a p-type impurity such as boron is introduced into the surface of the semiconductor substrate 1 through the sacrificial oxide film 2, and channel doping for adjusting the threshold voltage of the transistor is performed. When a transistor is formed on a well, a p-type impurity is introduced through the sacrificial oxide film 2 to form a p-type well 1 and channel dope.

Next, as shown in FIG. 4, after removing the sacrificial oxide film 2 from the surface of the semiconductor substrate 1, a gate insulating film 3 is formed by a thermal oxidation method or the like. Further, for example, tungsten silicide or polycrystalline silicon is deposited by CVD (chem.
The gate electrode 4 is formed by depositing the gate electrode 4 by an ionic vapor deposition method or the like.

Next, as shown in FIG. 5, in the region where the n-type MOS transistor Q10a is to be formed, the surface of the semiconductor substrate 1
A type impurity is introduced at a relatively low concentration to form an n-impurity region serving as LDD region 6. In the region where the n-type MOS transistor Q10b is formed, the resist 5
To prevent the introduction of n-type impurities. Since the resist 5 is formed simultaneously in a p-type MOS transistor (not shown) on the semiconductor substrate 1, the resist 5
A dedicated mask for forming the mask is not required.

Next, as shown in FIG. 6, in the region where the n-type MOS transistor Q10b is to be formed, p-type impurities such as boron are relatively lightly doped on the surface of the semiconductor substrate 1 using the gate electrode 5 as a mask. Then, a p-impurity region to be the LDD region 8 is formed. In the region where the n-type MOS transistor Q10a is to be formed, a resist 7 is deposited to suppress the introduction of p-type impurities. This resist 7 is made of another n-type MO (not shown) on the semiconductor substrate 1.
Since the S transistor is formed at the same time, a dedicated mask for forming the resist 7 is not required.

Next, as shown in FIG. 7, an insulating film such as a silicon oxide film is deposited on the surface side of the semiconductor substrate 1 by, for example, the CVD method, and is etched back. A film 9 is formed.

Next, as shown in FIG. 8, high concentration n-type impurities are introduced using gate electrode 4 and side wall insulating film 9 as a mask, thereby forming n-type MOS transistors Q10a and Q10b. An n + impurity region 10 is formed on the source side and the drain side.

Next, as shown in FIG. 2, an interlayer insulating film 11 covering the n-type MOS transistor 10a and the n-type MOS transistor 10b is formed.
Then, a contact 12 connected to the drain side n + impurity region 10 is formed. Then, a wiring 13 (bit line BLn) connecting the contact 12 of each memory cell is formed on the interlayer insulating film 11.

According to the method of manufacturing a semiconductor memory device described above, data programming is performed after the formation of the gate electrode 4, and the channel doping process in the mask ROM of FIG. 15 and the element isolation process in the mask ROM of FIG. Since it is closer to the end of the manufacturing process,
T can be shortened. Further, the step of programming data is performed by an n-type MOS in a normal logic circuit.
The process can be performed simultaneously with the process of manufacturing the transistor and the p-type MOS transistor, and the dedicated mask for the semiconductor memory device described above is unnecessary, so that the manufacturing cost can be reduced. Further, since the data to be programmed corresponds to the conductivity type of the impurity introduced into the LDD region, a high tamper resistance against physical analysis of the program data can be obtained.

<Second Embodiment> Next, a second embodiment of the present invention will be described with reference to FIGS.
Note that a circuit example of a semiconductor memory device including a plurality of memory cells is the same as that in FIG. 1, and a description thereof will be omitted.

FIG. 9 is a schematic sectional view for explaining a structural example of a semiconductor memory device according to the second embodiment of the present invention. In the example of FIG. 9, two adjacent memory cells MC32 and MC42 are shown.
The memory cells MC32 and MC42 have n
Type MOS transistor Q10a 'and n-type MOS transistor Q10b' are formed, respectively.

The n-type MOS transistor Q10a 'has the same structure as the n-type MOS transistor Q10a in FIG.

Also in n-type MOS transistor Q10b ', gate insulating film 3 is formed on the surface of p-type semiconductor substrate 1, and gate electrode 4 is formed via gate insulating film 3. Sidewall insulating films 9 are formed on both sides of the gate electrode 4.

However, n-type MOS transistor Q10
In the drain region and the source region b ′, no impurity for forming the LDD region on the lower surface of the sidewall insulating film 9 is introduced. On the source side of the n-type MOS transistor Q10b ', the n-type MOS transistor Q10a' is located at a position self-aligned with the sidewall insulating film 9 on the source side.
N + impurity region 10 having the same concentration as that of n + is formed.
On the drain side of the n-type MOS transistor Q10b ',
An n-type MOS transistor Q10 is located at a position separated from the channel formation region and the lower surface of sidewall insulating film 9.
An n + impurity region 10 having the same concentration as a ′ is formed.

The drain side n + impurity region 10 is formed between adjacent memory cells MC32a and MC42a.
Are shared with each other.

N-type MOS transistor 10a 'and n-type MOS transistor 10 formed on semiconductor substrate 1
b ′ has a surface covered with an interlayer insulating film 11, and a wiring 13 (bit line BL) is formed on the interlayer insulating film 11.
2) is formed. The wiring 13 is electrically connected to the drain side n + impurity region 10 via a contact 12 formed through the interlayer insulating film 11.

The source side n + impurity region 10 is
The n + impurity region 10 on the drain side is shared by another two memory cells adjacent to the non-shared side. The shared source-side n + impurity region 10 is shared by the memory cells in the same row, and is further electrically connected to a common ground potential line (not shown).

N-type MOS transistor Q10a 'and n-type MOS transistor Q10 having the above-described structures
The difference in b ′ is the presence or absence of an n − impurity region on the lower surface of the sidewall insulating film 9 and the position of the n + impurity region on the drain side. That is, n-type MOS
The transistor Q10a 'has a low concentration of n-type impurity introduced into the LDD region, and operates as a normal n-type MOS transistor having an LDD structure. Therefore, when reading stored data, n-type MOS transistor Q
10a 'is turned on, and the voltage of the bit line BLn becomes low level.

On the other hand, n-type MOS transistor Q10b '
In this case, the n-type impurity is not introduced into the LDD region, and the n + impurity region 10 on the drain side connected to the contact 12 is separated from the channel forming region. There is no conduction between the drain and the source. That is, the n-type MOS transistor Q1
0b 'does not function as a transistor. Therefore,
At the time of reading stored data, n-type MOS transistor Q10b 'remains off and bit line BLn
Becomes high level.

As described above, each memory cell stores binary data corresponding to the transistor to be formed (n-type MOS transistor Q10a 'or n-type MOS transistor Q10b').

As described above, according to the semiconductor memory device shown in FIG. 9, the data stored in each memory cell is L
This corresponds to the presence / absence of impurities for forming the DD region and the presence / absence of a region for separating the n + impurity region 10 from the channel formation region, and it is very difficult to physically analyze the data contents. Therefore, high tamper resistance can be obtained as in the semiconductor memory device of FIG.

The region for separating n + impurity region 10 and the channel formation region may be formed on the source side, or may be formed on both the source and the drain.

Next, the structure having the structure shown in FIG.
FIG. 10 shows a method of manufacturing a semiconductor memory device according to the present invention.
This will be described with reference to FIG.

In the method for manufacturing a semiconductor memory device shown in FIG. 9, the above-described steps from FIG. 3 to FIG. 5 are the same as the method for manufacturing the semiconductor memory device shown in FIG. Here, the manufacturing process following FIG. 5 will be described.

N-type MOS transistor Q10 shown in FIG.
After the step of forming the n- impurity region 6 of a ', a resist 14 covering both the n-type MOS transistor Q10a' and the n-type MOS transistor Q10b 'is formed as shown in FIG. The introduction of p-type impurities in the process of forming the LDD region of the MOS transistor is suppressed.

Next, as shown in FIG.
An insulating film such as a silicon oxide film is formed on the semiconductor substrate 1 by a method.
Deposited on the surface side of the gate electrode and etched back to form a gate electrode 4
Are formed on both sides of the substrate.

Next, as shown in FIG. 12, for example, a part of the gate electrode 4 and a region including the drain side wall insulating film 9 and in contact with the channel forming region and a region not in contact with the channel forming region are separated by a predetermined distance. Resist 15 covering the area
Is formed. By introducing high-concentration n-type impurities using the resist 15, the gate electrode 4 and the sidewall insulating film 9 as a mask, the n-type MOS transistor Q
An n + impurity region 10 is formed on the source side and the drain side of 10a 'and n-type MOS transistor Q10b'. Note that the resist 15 may be formed on the source side, or may be formed on both the drain side and the source side.

Next, as shown in FIG. 9, n-type MOS transistor 10a 'and n-type MOS transistor 10a'
An interlayer insulating film 11 covering b ′ is formed, and a contact 12 connected to the drain side n + impurity region 10 is formed in the interlayer insulating film 11. Then, a wiring 13 (bit line BLn) connecting the contact 12 of each memory cell is formed on the interlayer insulating film 11.

The same effect as that of the first embodiment can be obtained by the method of manufacturing a semiconductor memory device described above. That is, the data program is performed by the gate electrode 4.
The TAT can be shortened since the process is performed after the formation of the substrate. Further, the step of programming data is performed by using an n-type MOS transistor or a p-type
The process can be performed simultaneously with the manufacturing process of the S transistor, and the dedicated mask for the semiconductor memory device described above is unnecessary. Further, since the data to be programmed corresponds to the presence / absence of the introduction of the impurity forming the LDD region and the presence / absence of the region separating the n + impurity region 10 from the channel formation region, the data for the physical analysis of the program data is not obtained. High tamper resistance can be obtained.

<Third Embodiment> Next, a third embodiment of the present invention will be described. Note that a circuit example of a semiconductor memory device including a plurality of memory cells is the same as that in FIG. 1, and a description thereof will be omitted.

FIG. 13 is a schematic sectional view for explaining a structural example of a semiconductor memory device according to the second embodiment of the present invention. In the example of FIG. 13, two adjacent memory cells MC32 and MC42 are shown. The memory cell MC32 and the memory cell MC42 have an n-type MOS transistor Q10a ″ and an n-type
S transistors Q10b ″ are formed respectively.

N-type MOS transistor Q10a ″ has the same structure as n-type MOS transistor Q10a in FIG.

Also in n-type MOS transistor Q10b ″, gate insulating film 3 is formed on the surface of p-type semiconductor substrate 1, and gate electrode 4 is formed via gate insulating film 3. Sidewall insulating films 9 are formed on both side portions of 4.

However, n-type MOS transistor Q10
In the drain region and the source region b ″, no impurity for forming an LDD region on the lower surface of the sidewall insulating film 9 is introduced. On the source side of the n-type MOS transistor Q10b ″, the source-side sidewall insulating film is formed. 9, at a position self-aligned with the n-type MOS transistor Q10a ″.
N + impurity region 10 having the same concentration as that of n + is formed.
On the drain side of the n-type MOS transistor Q10b ″,
A p + impurity region 17 is formed at a position that is self-aligned with sidewall insulating film 9. This p + impurity region 1
7, an n + impurity region 10 having the same concentration as that of the n-type MOS transistor Q10a ″ is formed in a region on the drain side separated from the channel formation region.

The drain side n + impurity region 10 is formed between the adjacent memory cells MC32a and MC42a.
Are shared with each other.

N-type MOS transistor 10a ″ and n-type MOS transistor 10 formed on semiconductor substrate 1
b ″ has a surface covered with an interlayer insulating film 11, and a wiring 13 (bit line BL) is formed on the interlayer insulating film 11.
2) is formed. The wiring 13 is electrically connected to the drain side n + impurity region 10 via a contact 12 formed through the interlayer insulating film 11.

The source side n + impurity region 10
The n + impurity region 10 on the drain side is shared by another two memory cells adjacent to the non-shared side. The shared source-side n + impurity region 10 is shared by the memory cells in the same row, and is further electrically connected to a common ground potential line (not shown).

N-type MOS transistor Q10a ″ and n-type MOS transistor Q10 having the above-described structures
The difference in b ″ is the presence or absence of an n− impurity region on the lower surface of the sidewall insulating film 9 and the presence or absence of a p + impurity region 17 formed on the drain side. Since a low concentration of n-type impurity is introduced into the region, the region operates as a normal n-type MOS transistor having an LDD structure. Therefore, when reading stored data, the n-type MOS
The transistor Q10a ″ is turned on, and the bit line B
The voltage of Ln becomes low level.

On the other hand, n-type MOS transistor Q10b ″
In this case, the n-type impurity is not introduced into the LDD region, and the n + impurity region 10 on the drain side connected to the contact 12 and the channel formation region are separated by the p + impurity region 17, so that the gate voltage Does not conduct between the drain and source. That is,
The n-type MOS transistor Q10b "does not function as a transistor. Therefore, at the time of reading stored data, the n-type MOS transistor Q10b" remains off, and the voltage of the bit line BLn goes high.

As described above, each memory cell stores binary data corresponding to the transistor to be formed (n-type MOS transistor Q10a ″ or n-type MOS transistor Q10b ″).

As described above, according to the semiconductor memory device shown in FIG. 13, the data stored in each memory cell depends on whether or not an impurity forming an LDD region is introduced and whether n +
This corresponds to the presence or absence of the p + impurity region that separates the impurity region 10 from the channel formation region, and it is very difficult to physically analyze the data content. Therefore, high tamper resistance can be obtained as in the case of the semiconductor memory devices of FIGS. 2 and 9.

The p + impurity region 17 separating the n + impurity region 10 and the channel formation region may be formed on the source side, or may be formed on both the source and the drain.

Next, a method of manufacturing a semiconductor memory device according to the present invention having the structure shown in FIG. 13 will be described with reference to FIG.

In the method of manufacturing the semiconductor memory device shown in FIG. 13, the steps shown in FIGS. 3 to 5 are the same as those in the method of manufacturing the semiconductor memory device shown in FIG. Steps up to 12 are the same as those in the method for manufacturing the semiconductor memory device shown in FIG. Here, the manufacturing process following FIG. 12 will be described.

After the step of forming a region for separating the channel formation region and the drain region on the contact connection side shown in FIG. 12, as shown in FIG. 12, a resist 16 for covering other regions except for this separation region is formed. Is formed. And
Using the resist 16 and the gate electrode 5 and the sidewall insulating film 9 in the example of FIG. 14 as a mask, a p-type impurity is introduced. Thus, p + impurity region 17 is formed in the isolation region formed in the step shown in FIG.

Next, as shown in FIG. 13, n-type MOS transistor 10a ″ and n-type MOS transistor
An interlayer insulating film 11 covering b ″ is formed, and a contact 12 connected to the drain-side n + impurity region 10 is formed in the interlayer insulating film 11. Then, a wiring 13 (connecting the contact 12 of each memory cell) is formed. The bit line BLn) is formed on the interlayer insulating film 11.

The same effects as those of the first and second embodiments can also be obtained by the method of manufacturing a semiconductor memory device described above. That is, since the data programming is performed after the formation of the gate electrode 4, TA
T can be shortened. Further, the step of programming data can be performed simultaneously with the step of manufacturing an n-type MOS transistor or a p-type MOS transistor in a normal logic circuit, and the dedicated mask for the semiconductor memory device described above is not required. Also, since the data to be programmed corresponds to the presence / absence of the introduction of the impurity for forming the LDD region and the presence / absence of the p + impurity region 17 for separating the n + impurity region 10 from the channel formation region, the physical data of the program data is obtained. High tamper resistance performance can be obtained for various analyzes.

The present invention is not limited to the above-described first to third embodiments, and various modifications are possible. For example, in the above embodiment, the transistor of the memory cell is an n-type M
Although the case where the transistor is an OS transistor is described as an example, the present invention is not limited to the conductivity type of the transistor, and therefore, for example, it may be a p-type MOS transistor. In the manufacturing process, the order of the step of introducing the p-type impurity and the step of introducing the n-type impurity are not limited to the above-described embodiment, but may be reversed. Further, the first to third embodiments may be combined with each other. For example, the n-type M shown in FIG.
OS transistor Q10b 'and n-type MOS of FIG.
A step of forming a p-type LDD region 8 similar to the n-type MOS transistor Q10b of FIG. 2 may be added to the transistor Q10b ″.

[0109]

According to the semiconductor memory device and the method of manufacturing the same of the present invention, the writing process of the stored data is performed in the latter half of the manufacturing process, so that the period from the writing of the stored data to the end of the manufacturing can be shortened. . Further, it is possible to make it difficult to analyze the contents of the stored data.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram illustrating an example of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a structural example of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view after a channel doping step in the manufacturing process of the semiconductor memory device shown in FIG. 2;

FIG. 4 is a cross-sectional view after a step of forming a gate electrode in a step following that of FIG. 3;

FIG. 5 is a cross-sectional view after a step of forming an n − impurity region to be an LDD region in a step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view after a step of forming a p-impurity region serving as an LDD region in a step subsequent to that of FIG. 5;

FIG. 7 is a cross-sectional view after the step of forming a sidewall insulating film in a step subsequent to FIG. 6;

FIG. 8 is a cross-sectional view after formation of an n + impurity region serving as a drain and a source in a step following FIG. 7;

FIG. 9 is a schematic cross-sectional view for explaining a structural example of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view after a resist is formed in a step following the step of FIG. 5 for introducing a p-type impurity.

FIG. 11 is a cross-sectional view after the step of forming a sidewall insulating film in a step subsequent to that of FIG. 11;

FIG. 12 is a cross-sectional view after a step of forming an isolation region in a step subsequent to that of FIG. 11;

FIG. 13 is a schematic cross-sectional view for explaining a structural example of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 14 is a cross-sectional view after a step of forming ap + impurity region in a step subsequent to that of FIG. 12;

FIG. 15 is a schematic circuit diagram for explaining a conventional first mask ROM.

FIG. 16 shows a first mask ROM shown in FIG.
FIG. 3 is a schematic cross-sectional view of two adjacent memory cells.

FIG. 17 is a schematic second circuit diagram for explaining a conventional second mask ROM.

18 is a diagram illustrating a second mask ROM shown in FIG.
FIG. 3 is a schematic cross-sectional view of two adjacent memory cells.

FIG. 19 is a schematic third circuit diagram for explaining a conventional third mask ROM.

FIG. 20 is a diagram showing a configuration of the third mask ROM shown in FIG. 19;
FIG. 3 is a schematic cross-sectional view of two adjacent memory cells.

[Explanation of symbols]

MC11 to MC63: memory cells, Q10a, Q10
a ′, Q10a ″, Q10b, Q10b ′, Q10b ″
... n-type MOS transistors, WL1 to WL6 ... word lines WL, BL1 to BL3 ... bit lines BL, SL1 to SL3
... source line, 1 ... semiconductor substrate or well, 2 ... sacrifice oxide film, 3 ... gate insulating film, 4 ... gate electrode, 6 ... n-impurity region, 8 ... p-impurity region, 9 ... sidewall insulating film, 10 ... n + impurity regions, 11 ... interlayer insulating film, 12
... Contacts, 13 ... Wiring, 5, 7, 14, 15, 16
... resist, 17 ... p + impurity region, 18 ... field insulating film.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor memory device having a drain region and a source region with a channel formation region on a semiconductor substrate interposed therebetween, comprising: forming the gate insulating film on the channel formation region; A step of forming a gate electrode on the gate insulating film; a step of introducing a first concentration impurity having a conductivity type according to a storage state into the drain region and the source region; Forming an insulator sidewall; and introducing an impurity having a second concentration higher than the first concentration into the drain region and the source region except for a region covered with the insulator sidewall. A method for manufacturing a semiconductor memory device. 2. A mask, which separates a region in contact with the channel formation region from a region not in contact with the channel formation region and covers at least a part of the drain region or the source region, according to the storage state. Forming the second impurity in the drain region and the source region excluding a region covered with the insulator sidewall and the mask. The method for manufacturing a semiconductor memory device according to claim 1, wherein the method is adopted. 3. A region separating a region in contact with the channel formation region and a region not in contact with the channel formation region, wherein at least a part of the drain region or the source region has a conductivity type according to the storage state. 3. The method according to claim 2, further comprising the step of introducing an impurity. 4. A method for manufacturing a semiconductor memory device having a drain region and a source region with a channel formation region on a semiconductor substrate interposed therebetween, the method comprising: forming the gate insulating film on the channel formation region; Forming the gate electrode on a gate insulating film; introducing a first concentration of impurity into the drain region and the source region according to a storage state; A step of forming a wall, a region that separates a region that is not in contact with a region that is in contact with the channel formation region, and a mask that covers at least a part of the drain region or the source region;
A step of forming in accordance with the storage state, and introducing a second concentration impurity higher than the first concentration into the drain region and the source region except for the region covered with the insulator sidewall and the mask. And a step of manufacturing the semiconductor memory device. 5. A region separating a region in contact with the channel formation region and a region not in contact with the channel formation region, wherein at least a part of the drain region or the source region has a conductivity type according to the storage state. The method for manufacturing a semiconductor memory device according to claim 4, further comprising a step of introducing an impurity.