JPH06139710A - Digital audio signal measuring instrument - Google Patents

Abstract

PURPOSE:To easily and speedily perform the detection of the specified pattern of a C or U bit and the catch of the relevant information block of detection. CONSTITUTION:This digital audio signal measuring instrument for inputting digital audio signals is provided with a C bit and U bit comparator circuit 110 for comparing the pattern of the received C bit or U bit with a specified pattern designated by an operator and outputting the compared result, and a C bit and U bit fetcking circuit 109 for stopping the fetch of the C bit or U bit corresponding to a fetch synchronizing signal 114 from the C bit and U bit comparator circuit 110. Thus, the detection of the specified pattern of the C bit and U bit and the catch of the relevant information block can be easily and speedily performed effectively for fault analysis or the confirmation of the operation of the instrument.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio signal measuring device for measuring various characteristics of a digital audio signal.

[0002]

2. Description of the Related Art In recent years, digitization and broadcasting of audio equipment such as CDs (compact discs) and DATs (digital audio tapes) in the consumer market
With the spread of digital audio equipment in studios, a standard (digital audio interface standard) for connecting these digital audio equipment has been established. Standards are established by regional or international standardization organizations, but in Japan, E
Established in July 1987 as CP-340 by IAJ (Japan Electronic Opportunity Association).

As shown in FIG. 7, the format of a digital audio signal defined by CP-340 is such that one block includes 192 frames, one frame is composed of two subframes, and each subframe is composed of two subframes. , Bit 0 to 3 with sync preamble, bit 4
Audio sample data is arranged from bit 27 to bit 27, V, U and C bits are arranged from bit 28 to bit 30, respectively, and a parity bit is arranged in bit 31. Bits 4 to 31 are modulated by the bi-phase mark method in order to provide an interface irrelevant to the clock recovery from the DC component suppression data of the transmission line and the connectivity.

The V bit (validity bit) represents the validity of audio sample data, and the U bit (user bit) carries information individually defined by the medium (CD, DAT, etc.). The information block length and the meaning of each bit are also determined for each medium. The C bit (channel status bit) represents the nature and source of information in the data part such as word length of audio sample data / pre-emphasis presence / absence / sampling frequency. One information block is represented by 192 bits. Constitute. The P bit (parity bit) is a bit for detecting a transmission error or a device failure, and the P bit is set so that the number of logical "1" s of bit values from bit 4 to bit 31 is an even number. Add.

A digital audio signal measuring instrument has an input terminal defined by such a digital audio interface standard, and receives an input digital audio signal.
It is a device that measures various characteristics of an audio signal.

FIG. 8 shows the configuration of a conventional digital audio signal measuring apparatus, which includes a CPU 801 and a ROM which constitute a general microcomputer basic system.
802, RAM 803, display circuit 804, display device 80
5, input device (keyboard or mouse) 806, storage device 807 for writing / reading measurement conditions and measurement result data, and CPU bus 8 for connecting them
18, an input physical level conversion circuit 811 for converting the input digital audio signal 817 to a signal level (normally TTL level) inside the device and sending it as an input channel coding signal 816, and demodulating the input channel coding signal 816. , Various timing signals 815 are generated and supplied to other blocks, and received audio sample data 812 and received C-bit data 81
3 and the reception U-bit data 814 are separated and supplied to the audio sample analysis circuit 808 and the C-bit and U-bit capturing circuit 809, respectively, and the reception audio sample data 812 is controlled by the CPU 801. The audio sample analysis circuit 808 for measuring various characteristics, the received C bit data 813 and the received U bit data 814 are stored in the CPU 80.
It has a C-bit and U-bit fetch circuit 809 for fetching so that it can be processed by 1.

Next, the operation of the above conventional example will be described. In FIG. 8, an input digital audio signal 817 of a predetermined electric level or optical level input from the digital audio interface is converted into a signal level inside the device by an input physical level conversion circuit 811, and an input channel coding signal is obtained. It is input to the reception separation circuit 810 as 816.

In the receiving / separating circuit 810, the audio / sample data and the V / U / C / P bits are time-division-multiplexed and bi-phase mark modulated.
The coding signal 816 is demodulated, and various timing signals 815 necessary for processing other blocks, for example, a block head timing, a frame timing, as shown in FIG.
Generates bit timing, etc.
Separate the sample data from the C bit and U bit, and receive audio sample data at each timing 8
12, the received C-bit data 813 and the received U-bit data 814 are input to the audio sample analysis circuit 808 and the C-bit and U-bit capturing circuit 809.

The audio sample analysis circuit 808
It has a function of measuring various characteristics such as voltage value / distortion rate / frequency / voltage ratio between channels of the received audio sample data 812 which is a quantized audio signal, and has a function of controlling the CPU 801 according to an operator's instruction. To work. The measurement result is processed by the CPU 801 and displayed on the display device 80.
It is displayed in 5. At that time, the measurement result can be stored in the storage device 807 according to an instruction from the operator.

C bit and U bit capture circuit 80
The CPU 9 receives the reception C bit data 813 and the reception U bit data 814 separated by the reception separation circuit 810 from the CPU.
It has a function of recording in a RAM or the like in a format that can be processed by 801. The fetched C-bit and U-bit data is processed by the CPU 801 and displayed on the display device 805 in a binary format. At that time, the measurement result can be stored in the storage device 807 according to an instruction from the operator.

[0011]

However, in the above-mentioned conventional apparatus, the C-bit or U-bit observer observes the result displayed on the display device by the operator (user), so that the device failure occurs. Alternatively, it has been difficult to reliably capture an abnormal state in which a specific bit value momentarily changes due to a transmission failure, a software bug, or the like. Also, not only for abnormalities but also for temporarily checking the state where a specific bit pattern occurs and testing the normality of the device, etc., be sure to capture it under the condition that the rate of change of bit value exceeds the range that humans can recognize. I couldn't. Furthermore, when a specific pattern is detected in a specific field, it is not possible to capture the information in other fields or the contents of the entire information block, which requires a lot of time and effort for failure analysis and operation confirmation during development. I was spending.

The present invention solves such a conventional problem, and is an excellent digital type capable of easily and quickly detecting a specific pattern of C bits or U bits and displaying the corresponding information block at the time of detection. It is an object of the present invention to provide an audio signal measuring device.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention has a conventional configuration, in which C bits and U bits for comparing received C bits or U bits with a specific pattern.
It is provided with a bit comparison circuit.

The present invention also comprises means for synchronizing the C-bit and U-bit fetch circuit and the C-bit and U-bit comparison circuit.

[0015]

Since the present invention includes the C-bit and U-bit comparison circuit for comparing the received C-bit or U-bit with a specific pattern, the specific pattern of C-bit or U-bit can be detected with certainty. .

The present invention also includes a synchronization means for the C-bit and U-bit fetch circuit and the C-bit and U-bit comparison circuit, so that the corresponding information block is detected when a specific pattern of the C-bit or U-bit is detected. be able to.

Therefore, according to the present invention, it is possible to easily and quickly analyze the failure and confirm the operation of the device.

[0018]

1 shows the configuration of a digital audio signal measuring apparatus according to an embodiment of the present invention. In FIG. 1, 101 is a CPU constituting a general microcomputer basic system, 102 is a ROM, 103 is a RAM, 104 is a display circuit, 105 is a display device, and 106.
Is an input device (keyboard or mouse), 107 is a storage device for writing / reading measurement conditions and measurement result data, and these are connected by a CPU bus 121. Reference numeral 108 denotes an audio sample analysis circuit that measures various characteristics of the received audio sample data 115 under the control of the CPU 110.
Reference numeral 9 is a C for receiving the received C-bit data 116 and the received U-bit data 117 so that the CPU 801 can process them.
Bit and U bit capture circuit. Reference numeral 110 compares the value of the received C-bit data 116 or U-bit data 117 with a specific pattern to be detected specified by the operator, and if a pattern match is detected, the pattern match detection interrupt signal 113 to the CPU 101 and the C bit And a synchronizing signal 1 for taking in the U-bit taking circuit 109
14 is a C-bit and U-bit comparison circuit for generating 14. 111 demodulates the input channel coding signal 119, generates various timing signals 118 and supplies them to other blocks, and separates the received audio sample data 115 from the received C bit data 116 and the received U bit data 117. , An audio sample analysis circuit 108, a C bit and U bit capture circuit 109, and a C bit and U bit comparison circuit 1, respectively
10 is a receiving separation circuit that supplies the signal to Reference numeral 112 denotes an input physical level conversion circuit which converts the input digital audio signal 120 into a signal level inside the device (usually a TTL level) and sends it as an input channel coding signal 119.

Next, the operation of the above embodiment will be described. In FIG. 1, an input digital audio signal 120 of a predetermined electric level or optical level input from the digital audio interface is converted into a signal level inside the device by an input physical level conversion circuit 112, and an input channel coding signal is obtained. It is input to the reception separation circuit 111 as 119.

The receiving / separating circuit 111 demodulates the input channel coding signal 119 in which audio sample data and V, U, C, P bits are time-division-multiplexed and subjected to bi-phase mark modulation, and the processing of other blocks is performed. Various kinds of timing signals 118 (block start timing, frame timing, bit timing, etc.) necessary for the above are generated, and the audio sample data part and the C bit and U bit are separated, and the received audio sample data 115, The received C bit data 116 and the received U bit data 117 are output. The received audio sample data 115 is input to the audio sample analysis circuit 108, and the C bit data 116 and the received U sample data are received.
The bit data 117 includes a C bit and U bit fetch circuit 110 and a C bit and U bit comparison circuit 110.
Entered in and.

The audio sample analysis circuit 108
The received audio sample data 115, which is a quantized audio signal, has a function of measuring various characteristics such as voltage value / distortion rate / frequency / voltage ratio between channels, and is a basis of control of the CPU 101 according to an operator's instruction. To work. The measurement result is processed by the CPU 101, and the display device 105
Is displayed in. At that time, the measurement result can be stored in the storage device 107 according to an instruction from the operator.

C bit and U bit capture circuit 10
9 receives the received C bit data 116 and the received U bit data 117 separated by the reception separation circuit 111 from the CPU 1
01 has a function of recording in a RAM or the like in a format that can be processed. The captured C-bit data 116 and U
The bit data 117 is processed by the CPU 101 and displayed on the display device 105 in a binary or hexadecimal format. At that time, the measurement result is stored in the storage device 107 according to an instruction from the operator.
Can be stored in.

C bit and U bit comparison circuit 110
Is a pattern match detection interrupt signal to the CPU 101 when the operator compares the specific pattern to be detected input from the input device with the bit pattern of the received C bit data 116 or U bit data 117, and detects a pattern match. 113 and a fetch sync signal 114 to the C bit and U bit fetch circuit 109 is generated.

FIG. 2 shows an example of a display screen used for setting the detection pattern. In this example, the target of detection is C
In this example, bits are selected. In the detection target column 201, C
It is set whether the bit is a pattern detection target or the U bit is a pattern detection target. In the case of C bits, in principle, the same value is transmitted to channel 1 and channel 2, but either one channel can be selected, or both channels can be selected as targets. The bit position display field 202 displays the bit positions of the pattern data and the bit mask. A bit pattern to be compared is set in the pattern data setting field 203. In the case of C bits, since one information block is composed of 192 bits (24 bytes), there is a pattern setting field for 24 bytes. In the bit mask setting field 204, whether or not the bit is to be compared is set in bit units. When the value of the bit mask data is logical "0", the bit is not treated as a comparison target. By doing so, pattern comparison can be performed in bit units.

FIG. 3 shows the configuration of the C-bit and U-bit comparison circuit 110 in the above embodiment. In FIG. 3, reference numeral 301 denotes a comparison data storage RAM when executing the comparison operation.
A comparison address generation circuit for generating a comparison address 309 for 303, and the value of the comparison address output to the comparison address line 309 is the block start timing 3
It is cleared by 07 and is incremented by one address at the timing of the address count timing 308. 302 is a comparison data storage RAM address line 31
This is an address switching circuit for switching whether 0 is connected to the CPU address bus 305 or the comparison address line 309. Reference numeral 303 denotes a comparison data storage RAM that stores comparison data. 304 is a comparison data storage RAM
A data switching circuit that switches whether the data line 311 is connected to the CPU data bus 306 or the comparison data output bus 319. A CPU address bus 305 is connected to the comparison data storage RAM address line 310 when writing comparison data to the comparison data storage RAM 303. 306 is a CPU data bus,
When writing comparison data to the comparison data storage RAM 303, the comparison data storage RAM 303 is connected to the comparison data storage RAM data line 311. 307 is an information block (C bit or U bit)
Block start timing indicating the start timing of
Reference numeral 8 is an address count timing for counting up the comparison address, 309 is a comparison address line indicating an address generated by the comparison address generation circuit, 310 is a comparison data storage RAM address line, and 311 is a comparison data storage RAM data line. Reference numeral 312 is a mask data line, which is connected to bit 1 of the comparison data output bus 319. Reference numeral 313 is a comparison data line, which is connected to bit 0 of the comparison data output bus 319. Reference numeral 314 is received C-bit data or received U-bit data to be compared. Reference numeral 315 is a bit comparison timing indicating a 1-bit comparison timing. 31
Reference numeral 6 is a comparison result status signal indicating the status of the comparison result up to that point (whether a mismatch has occurred up to that point). 31
Reference numeral 7 is a block comparison result timing indicating the timing for determining the comparison result of one information block. Reference numeral 318 is a signal indicating the comparison result of one information block, and is a block comparison result output that outputs a positive logic pulse when they match. Reference numeral 319 is a comparison data output bus connected to the comparison data storage RAM data bus when the comparison operation is executed.

Next, the operation of the C-bit and U-bit comparison circuit 110 will be described. When performing the comparison operation, the comparison data storage RAM 303 is previously stored in FIG.
The pattern data and the bit mask data input by the operator are written on the screen used for setting the detection pattern shown in FIG.

FIG. 4 shows an example of data arrangement in the comparison data storage RAM 303, and shows a case where C-bit channels 1 and 2 are targeted. Data is arranged so that one subframe corresponds to one address.

After the comparison data and the mask data have been written in the comparison data storage RAM 303, the comparison operation becomes effective when the connection is switched to the B side in the address switching circuit 302 and the data switching circuit 304.

FIG. 5 shows an operation timing example of the C-bit and U-bit comparison circuit 110. The address corresponding to the received subframe is output from the comparison address generation circuit 301, and correspondingly, the comparison data 313 and the mask data 312 are output from the comparison data storage RAM 303. The received C-bit data 314 is compared with the comparison data 313 by the gate 1 (Ex-OR), and if they do not match, the output of the gate 1 becomes "H" level. Gate 2
The (AND) output is "L" (matched) regardless of the output value of the gate 1 if the mask data value corresponding to the bit is "0", and the gate data is "1" regardless of the output value of the gate 1. When the output of 1 is "H" (mismatch), a positive logic pulse (indicating that a mismatch has occurred) is generated at the timing of the bit comparison timing 315. The FF1 holds that a mismatch has occurred within one information block period, and the comparison result of one information block is output from the gate 3 at the timing of block comparison result timing 317 after the end of comparison of the last bit of one information block. It is output as the block comparison result output 318.

The block comparison result 318 is stored in the CPU of FIG.
The pattern match detection interrupt signal 113 is connected to the interrupt line of the bus 121 to notify the CPU 101 of the occurrence of the pattern match, and the operator is notified of the pattern match by a method of displaying this information on the screen by software. Notice.

Further, the block comparison result 318 is inputted to the C bit and U bit fetch circuit 109 as a fetch sync signal 114 to the C bit and U bit fetch circuit 109, and the C bit or U bit is fetched by this sync signal. By stopping the operation, the information block itself in which the specific pattern designated by the operator is detected can be reliably captured.

FIG. 6 shows an example of the stored contents of the C-bit and U-bit fetch circuit 109 in the above embodiment. One subframe (1
Bit) C bit or U bit information, a block head stator indicating that the subframe is the head subframe of the information block, and a capture end status indicating that the capture operation is completed in the subframe. . A commercially available RAM is used as the storage buffer, and the storage is performed cyclically while sequentially incrementing the address. The CPU 101, which has recognized that the pattern matching has occurred by the pattern matching detection interrupt signal 113, has already fetched the synchronization signal 11
In step 4, the fetching end address of the C bit and the U bit fetching circuit 109 in the storage buffer of the fetching buffer 109 is searched to determine the fetching end address. The C-bit or U-bit information stored at this address is the final bit information of the information block in which the specific pattern is detected. Next, the bit of the block head status is detected by tracing back the address from the fetch end address. The C-bit or U-bit information stored in the address where the block head status is detected for the first time is the head bit information of the information block in which the specific pattern is detected. In this way, the information block in which the pattern has been detected can be captured.

The C-bit and U-bit comparison circuit 110 of the above-described embodiment uses the received C-bit data 116 or the received U-bit.
The bit data 117 is configured to be serially compared bit by bit, and compared to parallel comparison, the number of parts used is small and the circuit is simple. Also, comparison data storage R
A commercially available inexpensive RAM can be used for the AM 303, and the capacity can be easily increased.

If the block comparison result 318 is output to the outside, it can be used as a trigger signal at the time of pattern detection.

In the above embodiment, C bit and U
A signal indicating that pattern matching has been detected is input to the bit capturing circuit 109 as a capture synchronization signal 114, but a means for detecting a parity error / out-of-synchronization / V-bit state / CRC error of channel status is provided. If provided and the detection result is input as the capture synchronization signal 114, the C-bit or U-bit information synchronized with the detection of these states can be captured.

In the above embodiment, C bit or U
Detecting the match of a specific pattern of bits, but by inverting the logic of the block comparison result timing,
It is also possible to detect a mismatch with a specific pattern of C bits or U bits. In this case, it is possible to easily and surely catch an abnormal state that temporarily occurs due to a transmission failure on the interface, a device failure, a bug, or the like.

[0037]

As is apparent from the above embodiment, the present invention includes the C-bit and U-bit comparison circuit, so that the specific pattern of C-bit or U-bit can be surely detected.

Since the present invention also includes a synchronization means for the C-bit and U-bit fetch circuit and the C-bit and U-bit comparison circuit, the corresponding information block is detected when a specific pattern of the C-bit or U-bit is detected. be able to.

Therefore, according to the present invention, it is possible to easily and quickly analyze a failure and confirm the operation of the device.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of a digital audio signal measuring apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a screen used for setting a detection pattern in the same device.

FIG. 3 is a schematic block diagram showing a configuration of a C-bit and U-bit comparison circuit in the same device.

FIG. 4 is a schematic diagram showing a data arrangement row of a comparison data storage RAM in the same device.

FIG. 5 is a timing chart showing the operation of a C-bit and U-bit comparison circuit in the same device.

FIG. 6 is a schematic diagram showing an example of stored contents of a C-bit and U-bit fetch RAM in the same device.

FIG. 7 is a data structure diagram showing a format of a digital audio signal.

FIG. 8 is a schematic block diagram showing the configuration of a conventional digital audio signal measuring device.

FIG. 9 is a timing chart showing the operation of the reception separation circuit in the same device.

[Explanation of symbols]

 101 CPU 102 ROM 103 RAM 104 Display Circuit 105 Display Device 106 Input Device 107 Storage Device 108 Audio Sample Analysis Circuit 109 C-bit and U-bit Capture Circuit 110 C-bit and U-bit Comparison Circuit 112 Input Physical Level Conversion Circuit 113 Pattern Match Detection Interrupt signal 114 Capture synchronization signal 115 Received audio sample data 116 Received C bit data 117 Received U bit data 118 Various timing signals 119 Input channel coding signal 120 Input digital audio signal 121 CPU bus 201 Detection symmetry column 202 Bit position indication 203 Pattern data setting column 204 Bit mask setting column 301 Comparison address generation circuit 302 Address switching circuit 303 Comparison Data storage RAM 304 Data switching circuit 305 CPU address bus 306 CPU data bus 307 Block start timing 308 Address count timing 309 Comparison address line 310 Comparison data storage RAM address line 311 Comparison data storage RAN data line 312 Mask data line 313 Comparison data line 314 Reception C bit data / Reception U bit data 315 Bit comparison timing 316 Comparison result status signal 317 Block comparison result timing 318 Block comparison result output 319 Comparison data output bus

Claims (2)

[Claims] 1. A reception separation circuit that receives, demodulates, and separates an audio input signal, and an audio signal that analyzes the reception audio sample data separated by the reception separation circuit.
A sample analysis circuit, a C bit and U bit fetch circuit for fetching the received C bit and the received U bit separated by the reception separation circuit, and preset C bit pattern data or U bit pattern data by the reception separation circuit. Separated reception C bit or reception U
A digital audio signal measuring device comprising a C-bit and U-bit comparing circuit for sequentially comparing bits and detecting pattern matching. 2. A reception separation circuit for receiving, demodulating and separating an audio input signal, and an audio unit for analyzing the reception audio sample data separated by the reception separation circuit.
C-bit and U-bit comparison for sequentially comparing the sample analysis circuit and preset C-bit pattern data or U-bit pattern data with the received C-bit or received U-bit separated by the reception separation circuit Circuit, and a C-bit and U-bit fetch circuit that periodically fetches the received C-bit and the received U-bit separated by the reception separation circuit, and stops the capturing by the pattern match detection signal from the C-bit and U-bit comparison circuit. And a digital audio signal measuring device having.