KR100480413B1 - An auxiliary digital data extractor in a television - Google Patents

Abstract

The auxiliary digital data extractor in the television receiver comprises a source of the composite video signal. The composite video signal comprises an auxiliary digital data component, the component comprising a first frame code having a predetermined number of bits and auxiliary data in a first format, or an equal number of bits and auxiliary in a second format. One of the second frame codes with data. The frame code detector is coupled to the composite video signal source. The frame code detector responds to one subset of the frame code bits to detect the first frame code, and a different subset of the frame code bits to detect the second frame code. The auxiliary data utilization circuit is coupled to the composite video signal source and the frame code detector. The auxiliary data utilization circuit receives auxiliary data in either the first format when the first frame code is detected or the second format when the second frame code is detected.

Description

AUXILIARY DIGITAL DATA EXTRACTOR IN A TELEVISION

The present invention relates to a television receiver comprising a system for identifying and extracting auxiliary digital data having one of a number of formats inserted in a vertical blanking interval of a television video signal.

In general, auxiliary data such as, for example, closed captioning information and eXtended Data Service (XDS) information are transmitted in digital form during the vertical blanking interval of a standard television signal. The closed caption information indicates closed caption characters, and the XDS information includes various auxiliary data. This information is inserted at a known position in the vertical blanking interval of the television video signal and formatted in a known manner. In an NTSC television signal in the United States, line 21 in field 1 is reserved for closed caption information, and line 21 of field 2 is reserved for XDS information.

1 is a waveform diagram useful in understanding the operation of the present invention.

2 is a block diagram of a portion of a television receiver incorporating the present invention.

3 is a more specific block diagram of a vertical blanking interval data extractor in accordance with the present invention.

FIG. 4 is a more detailed diagram, partially in block form and partially in logic form, illustrating a frame code detector that may be used in the vertical blanking interval data extractor shown in FIG.

Figures 5 and 6 are more specific views, in part block form and in part logic form, showing portions of the controller circuit shown in Fig. 3;

Referring to FIG. 1, the closed caption signal is shown in the second waveform from the top labeled CC SIG. This signal includes a first interval of 10.5 kHz with which the signal nominally remains at 0 IRE amplitude. This is followed by a clock run-in interval of 14 ms that includes seven periods of a 500 Hz sine wave clock signal, which clock signal is peak-to-peak equal to subsequent closed caption data. -to-peak) amplitude. Peak-to-peak amplitude is nominally 50 IRE. The run-in interval is followed by a 3 ms interval of the 0 IRE signal. After a 3 ms 0 IRE signal interval, the start bits of the 2 ms duration are followed by 16 data bit intervals, and in each of the 2 ms duration, the data is non-return-to-zero (NRZ). ) Is sent in the format. In this way, two bytes of the closed caption information are transmitted. The closed caption processor in the receiver extracts the closed caption data from the position in the vertical blanking interval and displays the information on the television display device.

Digital assistant information, eg, television program scheduling information, except closed captions and XDS information may also be transmitted in the vertical blanking interval using the same format. The scheduling service is provided by a Starsight company, where the scheduling information is transmitted in the vertical blanking interval of the video signal, using the same format as the closed caption information. The scheduling processor at the receiver allows the viewer to select a TV program based on the displayed scheduling data, extract the scheduling data from the position in the vertical blanking interval, and display the information. Recently, however, another format for auxiliary digital data, in particular TV program scheduling data, has been proposed by the Gemstar company.

No position in the vertical blanking interval is reserved for StarSite or Gemstar scheduling information. Thus, a different broadcaster may store this information within any vertical blanking interval, except for those positions reserved for closed caption information and XDS information (lines 21 in fields 1 and 2). Include freely on site. In addition, the data transmitted to the proposed Gemstar system may sometimes be in the closed caption format described above, and sometimes in a newly proposed format called the Gemstar format in the remainder of this application.

The Gemstar format signal is shown in FIG. 1 with the third waveform from the top labeled GS SIG. The Gemstar format line in the vertical blanking interval also starts with 10.5 Hz of the nominal 0 IRE signal. However, the interval is only followed by 5 cycles of 500 Hz, nominally 50 IRE peak-to-peak, sinusoidal run-in clock signal. The run-in clock signal is immediately followed by a digital 9 bit frame identifying a code with a predetermined value of 011101101. Each bit in the frame code acquires 1 ms and exists in NRZ format. The frame code is immediately followed by 32 data bits, each of which also acquires 1 ms in the NRZ format. In this way, 4 bytes of scheduling data are transmitted at the closed caption position in the vertical blanking interval. Again, the scheduling processor at the receiver extracts the scheduling data from the position in the vertical blanking interval and allows the viewer to select based on the scheduling data.

It would be desirable to provide an auxiliary information decoder that reliably decodes a number of auxiliary data formats, such as both Gemstar format data and closed caption data. A problem that may occur when decoding auxiliary data is that signal noise may cause the data to be decoded incorrectly. For example, noise can cause one or more bits of the frame code to be incorrect. As a result, the frame code detector may process frame codes that include errors related to noise and may incorrectly indicate the type of data present in a particular portion of the television signal. For example, a decoder that processes gemstar frame code that includes an erroneous bit may incorrectly indicate that the line spacing associated with the frame code does not include gemstar data. As a result, the decoder can preferably ignore the line spacing rather than decode the data.

According to the principles of the present invention, an auxiliary digital data extractor in a television receiver processes a composite video signal comprising an auxiliary digital data component, the component having a predetermined number of bits and auxiliary data in a first format. One frame code, or a second frame code having the same number of bits and auxiliary data in the second format. The frame code detector responds to one subset of the frame code bits to detect the first frame code and to a different subset of the frame code bits to detect the second frame code. The auxiliary data utilization circuit receives the auxiliary data in either the first format when the first frame code is detected or the second format when the second frame code is detected.

According to another aspect of the present invention, the auxiliary information decoder has a first mode of operation for detecting any occurrence of auxiliary information in the signal, and a second mode of operation for detecting a particular occurrence of auxiliary information in the signal. Has

The invention will be explained with reference to the drawings.

In the remainder of this application, the term television receiver will refer to a system capable of receiving and processing television signals, whether the system can render video images and associated audio components. For example, the term television receiver refers to a standard television receiver with a display and speakers, and also refers to a video cassette recorder (VCR) or a circuit in a set-top cable or satellite box, all of which The device includes circuitry capable of receiving and processing television signals, but cannot display the image represented by the television signal or render the voice. Moreover, in the remainder of this application, the auxiliary digital information will refer to either closed caption information or gemsta scheduling information.

2 is a block diagram of a portion of a television receiver incorporating the present invention. In FIG. 2 only those parts of the receiver needed to understand the operation of the present invention are shown. Those skilled in the art can understand what other elements are required in a working television receiver and how they are interconnected with the elements shown in FIG.

In Fig. 2, the input terminal 5 is coupled to a source (not shown) of the composite video signal. For example, in a standard television receiver, such sources include antenna or cable connections, RF and IF amplifiers, detectors, and it is possible to include elements for separating audio components from video components. As another example, in a standard VCR, the source may include a tape transfer mechanism, a tape read head, and a read-back amplifier. Input terminal 5 is coupled to each input terminal of synchronous component separator 10 and to a data slicer 30. The composite synchronization signal output terminal S of the synchronization component separator 10 is coupled to a corresponding input terminal S of the vertical blanking interval (VBI) data extractor 20. The output terminal of the data slicer 30 is coupled to the VBI signal input terminal V of the VBI data extractor. The output terminal of the crystal oscillator 40 is coupled to a clock input terminal (CLK) of the VBI data extractor 20.

Microprocessor 50 is coupled to the VBI data extractor by a bidirectional 8-bit data bus. The control input terminal of the microprocessor 50 is coupled to the corresponding input terminal of the VBI data extractor 20, while the interrupt request output terminal of the VBI data extractor 20 is connected to the corresponding input terminal of the microprocessor 50. Combined.

When in operation, the composite video signal at input terminal 5 is a standard composite video signal, such as the NTSC composite video signal in the United States, and includes a video component and a sync component (among other components not suitable for the understanding of the present invention). do. The sync component separator 10 operates in a known manner to separate the composite sync component from the composite video signal and to supply the sync component to the VBI data extractor 20.

The data slicer 30 generates a serial stream of digital bit signals representing the composite video signal in a known manner. When the composite video signal value is greater than the slice level value, the slicer 30 output signal is at the first logic level, and when the value of the video signal is less than the slice level value, the digital output signal is at the second logic level. exist. In the exemplary embodiment described herein, the first and second logic levels correspond to logic '1' and logic '0', respectively. Referring to Fig. 1, the second waveform CC SIG from above shows a closed caption format data signal. The run-in signal constituting the seven sine wave periods has the same peak-to-peak value as the subsequent NRZ data signal. The base value of a sine wave is nominally 0 IRE and the peak value is nominally 50 IRE. Thus, the slicing level signal selected to be midway between the base and peak values is nominally 25 IRE, as shown by the CC SIG waveform. The base and peak values of the received run-in signal can, of course, be changed, but should still be the same as the value of that portion of the subsequent NRZ data. Thus, the slicing level can be set in a known manner to the center point between the actually received base value and the peak value of the run-in signal.

Starting at the last two periods of the run-in signal, 9 ms of output from the data slicer 30 representing the frame code is shown on the CC SIG signal. When the CC SIG signal is greater than the shown slicing level of 25 IRE, the digital output signal from slicer 30 becomes a logic '1' signal, and when the CC SIG signal is less than the shown slicing level, the value of the digital output signal. Becomes a logic '0' signal. Therefore, the binary frame code generated by the data slicer 30 in response to the CC SIG signal is 101000011.

The microprocessor 50 supplies the VBI data extractor 20 with data specifying a line of vertical blanking interval from which auxiliary digital data is to be extracted, via a data bus and a control signal. This data may be stored in a register in the VBI data extractor 20 in a known manner.

The VBI data extractor 20 operates to process the digitized VBI signal from a VBI horizontal line predefined by the microprocessor 50 in the manner described in more detail below. The VBI data extractor 20 determines the presence and format of the data in the VBI and extracts the data. At the end of the VBI horizontal line, the microprocessor 50 is informed by the abort request on the IRQ output terminal. In response to the abort request, as described in more detail below, the microprocessor 50 determines if the VBI data is present on the horizontal line, and if present, via the control output terminal the VBI data extractor 20. The extracted data is transmitted from the VBI data extractor 20 to the microprocessor via a data bus with a read enable signal supplied thereto.

3 is a more specific block diagram of a vertical blanking interval data extractor 20 in accordance with the present invention. In FIG. 3, input terminal V receives the digitized VBI component of the video signal from data slicer 30 (FIG. 2). The input terminal V is coupled to the serial data input terminal SI of a 32 bit shift register 204. The 32-bit parallel output terminal PO of the shift register 204 is coupled to each input terminal of the parity generator 206, the frame code detector 208 and the latch 210. The 4-bit output terminal of parity generator 206 is coupled to the corresponding input terminal of latch 210.

The first and second output terminals of the frame code detector 208 that generate each signal CC FRAME and GS FRAME (more specifically described below) are coupled to corresponding input terminals of the controller circuit 212. The input terminal S receives the composite synchronization signal from the synchronization signal separator 10 (Fig. 2). The input terminal S is coupled to the corresponding input terminal of the controller circuit 212. The 4 MHz clock signal from the crystal oscillator 40 (FIG. 2) is coupled to the clock signal input terminal of the controller circuit 212.

A first output terminal of the controller circuit 212 that generates a shift clock signal is coupled to a shift clock input terminal of the shift register 204. Second and third output terminals of the controller circuit 212 that generate signals GS MODE and CC MODE (described in more detail below) are coupled to corresponding input terminals of the latch 210, respectively. A fourth output terminal of the controller circuit 212 that generates the LINE signal is coupled to the clock input terminal CLK of the latch 210.

A fifth output terminal of the controller circuit 212 that generates the abort request signal IRQ is coupled to an output terminal IRQ coupled to the microprocessor 50 (FIG. 2). The CNTRL input terminal is coupled to the control output terminal of the microprocessor 50. The CNTRL input terminal is coupled to the corresponding input terminal of the controller circuit 212 and five enable input terminals, that is, ENB 1, ENB 2, ENB 3, ENB 4 and ENB S of the latch 210. An 8-bit bidirectional data bus terminal is also coupled to the microprocessor 50. The data bus terminal is coupled to an input terminal of the controller circuit 212 and five 8-bit output terminals, namely DO 1, DO 2, DO 3, DO 4 and DO S of the latch 210.

In normal operation, the microprocessor 50 (FIG. 2) registers data in the controller circuit 212 that specifies, in a known manner, the horizontal line in the vertical blanking interval via the data bus and control signals at the CNTRL input terminal. Send to (REG). The controller circuit 212 monitors the composite synchronization signal from the input terminal S. When the horizontal line specified in register REG occurs, from data slicer 30, the VBI signal serial data stream for the horizontal line is moved from shifter register 204 in response to a shift clock signal from controller circuit 212. . The frame code detector 208 monitors 32 bits at the parallel output terminal of the shift register 204 to detect the frame code of either the closed caption format signal or the Gemstar format signal.

When the closed caption format signal is detected, an indication that the closed caption format data is available is supplied to the latch 210 via the CC MODE signal. When a gemsta format signal is detected, an indication that gemsta format data is available is supplied to latch 210 via a GS MODE signal. In one of these cases, the auxiliary digital data in the detected format is extracted by the shift register 204 and stored in the latch 210, along with the associated parity information from the parity generator 206. If no format signal is detected, an indication that no data is available is stored in latch 210. At the same time, the information is stored in latch 210 and the abort signal is supplied to microprocessor 50 via an IRQ signal line. In response to the abort request signal, the microprocessor 50 reads the contents of the latch 210 via the data bus and enable signals on the CNTRL input terminals, in all manners described further below.

Although the illustrated embodiment includes latch 210, those skilled in the art will appreciate that it is not entirely required. The microprocessor 50 responds to the IRQ signal and before the next occurrence of a particular VBI line interval (VBI line interval specified by the data in the register (REG) in FIG. 3), the GS MODE and CC MODE signals, and auxiliary digital data and If the parity data can be retrieved, the latch 210 can be omitted. In this case, the microprocessor 50 reads data directly from the controller circuit 212, the shift register 204 and the parity generator 206.

The controller circuit 212 includes a counter of a known device and associated circuitry (not shown) for monitoring the composite sync signal from an input S terminal that detects a vertical field and counts a horizontal line. The controller circuit 212 also includes circuitry of the known apparatus to compare the current horizontal line with the horizontal line specified by the data in the register REG. The LINE signal is activated at the beginning of the 'active portion' of the specified horizontal line (ie, logic '1' as in the illustrated embodiment), otherwise left inactive (logical '0'). Referring to FIG. 1, the best waveform shows the LINE signal with respect to the horizontal line in the vertical blanking interval specified by the data in the register REG.

As soon as the LINE signal is activated, the controller circuit 212 begins to provide a 4 MHz shift clock to the shift register 204. In this way, the serial bit stream representing the VBI video signal from data slicer 30 (FIG. 2) is clocked through shift register 204. In the illustrated embodiment, the shift register 204 is clocked at the leading edge of the shift clock signal. As mentioned above, the VBI data signal has the format shown in either the CC SIG waveform or the GS SIG waveform of FIG. 1. After an initial 10.5 ms interval and five periodic run-in clock intervals, the gemsta format signal (GS SIG) is followed by a 9 ms interval, which is a frame code signal having a digital value (011101101) when digitized. Include. During the same 9 ms time interval, the closed caption format signal (CC SIG) comprises a digital bit stream having a value (101000011).

In the illustrated embodiment, the frame code interval is an initial 10.5 ms interval and a 9 ms interval following five periodic run-in clock intervals, which interval is common to all format signals. That is, the frame code interval starts at the first point where two different format signals have different values, and ends where the digital auxiliary data for all format signals begins. Those skilled in the art will appreciate that the definition of the frame code interval is arbitrary and may include any portion of the signal sufficient to distinguish data in one format from data in another format.

Frame code detector 208 monitors the 32-bit state at the parallel output terminal of shift register 204. Frame code detector 208 operates in one of two modes of operation. The first mode is a search mode in which the detector is searching for any generation of auxiliary information such as a frame code. That is, in the seek mode, it is not known if auxiliary digital data in either the closed caption format or the gemsta format is included in the video signal, and if so, it is not known which line contains the data. Such data may be included from any horizontal line in the vertical blanking interval, for example, from line 10 to line 20 in either field 1 or field 2. Moreover, data in other formats can be inserted into lines in the vertical blanking interval. In order to increase the certainty of detection as the desired format signal and to minimize false identification of any signal, the criteria for detecting either closed caption or gemsta frame code are enhanced in search mode. All available frame codes in the received digitized VBI signal are compared with the corresponding bits in one of the 01110110 Gemstar frame code or 101000011 closed caption code, perhaps for one or more sequential video frames during the seek mode. Once the presence and location of auxiliary digital data in the closed caption format or gemsta format are identified, the search mode is terminated.

When the search mode is terminated, the frame code detector 208 enters a second mode of operation called a locked-on mode in the remainder of this application while a particular occurrence of auxiliary information is detected. . That is, in the lock-on mode, the position of the auxiliary data in the vertical blanking interval is determined, and the data representing that position is stored in the register REG in the controller circuit 212. Thus, the detector can find the appearance of the desired assistance information at a particular line interval indicated by the data stored in the register REG. In a method to be described in more detail below, the frame code detector 208 continuously monitors 32 bits from the shift register 204 to detect either a gemsta frame code of 01110110 or a closed caption frame code of 101000011. . However, in the lock-on mode, the detection criteria for detecting closed caption or gemsta frame code are relaxed in proportion to the criteria of the seek mode in order to minimize disruption of the presence of the noise signal. The remainder of this application will describe lock-on mode operation, even though the seek mode is explicitly specified.

Each time the gemsta frame code of 011101101 is detected by the frame code detector 208, a GS FRAME pulse signal is generated, as shown in FIG. In a similar manner, although not shown in FIG. 1, whenever a closed caption frame code of 101000011 is detected by the frame code detector 208, a CC FRAME pulse signal is generated in all the ways to be described in more detail below. .

The controller circuit 212 receives the CC FRAME and GS FRAME signals from the frame code detector 208. To increase the accuracy of the detection of the frame code, the controller circuit 212 generates a FRAME WINDOW signal. The FRAME WINDOW signal is derived from the composite sync signal in a known manner and is activated for a time interval surrounding the nominal time when either GS FRAME or CC FRAME pulses can occur exactly (embodiment shown) Is a logic '1' signal, otherwise it is disabled (logical '0'). In the illustrated embodiment, the FRAME WINDOW signal is activated over a 5 ms interval around the nominal time when a GS FRAME or CC FRAME pulse should occur, which is 29.5 ms from when the LINE signal is activated. This is shown by the waveform FRAME WINDOW in FIG.

During the time interval when the FRAME WINDOW signal is activated, the CC FRAME and GS FRAME signals are monitored by the controller circuit 212. If a pulse is detected in the GS FRAME signal (as shown in the GS FRAME signal in FIG. 1), the controller circuit 212 activates the GS MODE signal as shown in the GS MODE signal in FIG. In the example, the logic is '1'. This indicates that Gemstar format data is on the specified horizontal line and the data follows. Gemstar format data exists in the form of a 32-bit NRZ data stream. As described above, each bit interval is 1 ms. In response to the detection of the GS FRAME signal, the controller circuit 212 shifts the sampling signal (ie, leading edge) such that a sampling signal (ie, leading edge) is generated in the middle of each gemstar data bit interval as shown in the GS SAMPLE CLOCK signal in FIG. The clock signal is supplied to the shift register 204. Thus, for the first portion of the line, that is, until the GS FRAME signal is detected, the shift clock signal is a 4 MHz clock signal. For the second portion of the line, i.e., until the GS FRAME pulse is detected, the shift clock signal is a phased 1 MHz signal such that the leading edge (i.e., the sampling signal) is synchronized at the center of the Gemstar data bit interval. .

In a similar manner, although not shown in FIG. 1, if a pulse is detected in the CC FRAME signal, the controller circuit 212 causes the CC MODE signal to be activated (logic '1' in the illustrated embodiment). This indicates that the closed caption format is on the specified horizontal line and the data follows. Closed caption format data exists in the form of a 16-bit NRZ data stream, with each bit interval being 2 ms. In response to the detection of the CC FRAME signal, as shown in the CC SAMPLE CLOCK signal in FIG. 1, the controller circuit 212 causes the sampling signal (ie, leading edge) to be generated in the middle of each closed caption data bit interval, The shift clock signal is supplied to the shift register 204. Thus, for the first portion of the line, that is, until the CC FRAME pulse is detected, the shift clock signal is a 4 MHz clock signal. For the second portion of the line, i.e. after the CC FRAME pulse is detected, the shift clock signal is a phased 500 Hz signal such that the leading edge (i.e., the sampling signal) is synchronized to the center of the closed caption data bit interval.

While the FRAME WINDOW signal is active, if no CC FRAME signal or GS FRAME signal is detected by the frame code detector 208, no GS MODE or CC MODE signal is generated and the frequency and phase of the shift clock signal No change takes place.

In response to the altered shift clock signal, the shift register 204, as selected by the CC FRAME and GS FRAME signals, bit for either the Gemstar format (GS SIG in FIG. 1) or the closed caption format (CC SIG). The digital signal is sampled from the data slicer 30 (FIG. 2) in the middle of the interval. At the distal end of the active portion of the VBI horizontal line, shift register 204 contains the VBI data. This data is present in the parallel output terminal PO of the shift register 204 and supplied to the latch 210. The 32 bits are divided into four 8-bit bytes. At the same time, parity generator 206 calculates four parity bits, one corresponding to each of the bytes divided from shift register 204. The parity bit is also fed to latch 210.

When the active portion of the VBI horizontal line ends, the LINE signal is deactivated again by the controller circuit 212, as shown in FIG. The LINE signal is coupled to the clock input terminal CLK of the latch 210. In response to the LINE signal being deactivated, latch 210 latches the VBI data signal from shift register 204, latches the GS MODE and CC MODE signals from controller circuit 212, and the parity signal from parity generator 206. Latch. Four bytes from the shift register 204 are latched into each four bytes of the latch 210. The four parity bits are latched into four bits of the fifth byte of the latch 210, called the status byte. Finally, the GS MODE and CC MODE signals from the controller circuit 212 are latched into the fifth and sixth bits of the fifth status byte in the latch 210.

The controller circuit 212 also generates an interrupt request signal IRQ supplied to the microprocessor 50 (FIG. 2) in response to the LINE signal being deactivated and latching the data and status information to the latch 210. FIG. do. In a known manner, in response to the IRQ signal, the microprocessor 50 executes an interrupt handler routine. The abort handler routine enables the microprocessor 50 to read the status byte from the latch 210 by activating the status byte enable signal ENB S. In response to the status byte enable signal ENB S, the output terminal DO S of the latch 210 that generates the status byte is coupled to the microprocessor 50 data bus and the data is driven by the microprocessor 50. Is read. The abort handler tests the data bits containing the GS MODE and CC MODE signals. When the GS MODE bit is enabled, 32 bits of auxiliary digital data are sent on the VBI line, and all 4 data bytes are read by the microprocessor 50. In this case, the microprocessor sequentially activates the data byte enable signals ENB 1, ENB 2, ENB 3 and ENB 4. In response to the ENB 1 signal, the latch 210 places the contents of the first data byte on the data bus at the data output terminal DO 1, and the data is read by the microprocessor 50. Similarly, at each of the data output terminals DO 2, DO 3 and DO 4, the second, third and fourth bytes are in response to the data byte enable signals ENB 2, ENB 3 and ENB 4 respectively. Is located on. If desired, microprocessor 50 may also check the parity of these data bytes by analyzing the four parity bits present in the status byte.

When the CC MODE signal is activated, this indicates that closed caption information was transmitted during the VBI line. In this case, however, only 16 bits, or 2 bytes of auxiliary digital data are transmitted, and only data bytes at the data output terminals DO 3 and DO 4 contain valid information. The microprocessor reads these data bytes after providing each enable signal. Thereafter, the received data bytes may be processed in a suitable manner, such as extracting scheduling information and displaying such information to the viewer.

FIG. 4 is a more specific view, partially in block form and partially in logic form, showing a portion of frame code detector 208 operating during lock-on mode. In Fig. 4, the same elements as those shown in Fig. 3 are designated by the same reference numerals and will not be described in detail. In FIG. 4, the shift register 204 is shown with a serial input terminal SI and a mobile clock input terminal CLK, and 32 single-bit parallel output terminals. The leftmost output terminal, labeled "0", contains the most recently received bit.

Each output terminal 0 and 4 is coupled to the first and second input terminals of a negative output AND (NAND) gate 302. Each output terminal 8, 12 and 16 is coupled to the first, second and third input terminals of the negative output OR (NOR) gate 304. Each output terminal 8, 12, 20 and 28 is coupled to the first, second, third and fourth input terminals of the second NAND data 306. The output terminal 4 is coupled to the first input terminal of the second NOR gate 308. The output terminal of the first NAND gate 302 is coupled to the fourth input terminal of the NOR gate 304, and the output terminal of the second NAND gate 306 is coupled to the second input terminal of the second NOR gate 308. do. An output terminal of the first NOR gate 304 generates a CC FRAME signal, and an output terminal of the second NOR gate 308 generates a GS FRAME signal.

Referring to FIG. 1, the digital bit stream from slicer 10 (FIG. 2) is sampled at 4 MHz rate in response to the GS FRAME signal or the CC FRAME signal being generated. Since each bit in the frame code portion of the signal has a duration of 1 ms, each such bit is oversampled by the shift register 204 four times. That is, each bit is stored in four adjacent positions in the shift register 204. Thus, to properly sample the different bits in the frame code, it is processed by the frame code detector for every fourth bit in the shift register 204.

In the current embodiment, only eight of the nine frame code bits can be stored in the 32-bit shift register 204, so only those eight bits are available for processing to detect valid gemstar or closed caption frame codes. . However, in the illustrated embodiment, only a subset of 5 bits of the available set of 8 bits is processed to determine if there is a closed caption frame or gemsta frame. Such 5 bits, and value, is (x) xxx00011 to detect a valid closed caption frame code and (x) 1x1x110x to detect a valid Gemstar frame code, where (x) is the ninth unavailable bit ( unavailable bit), and x represents a 'don't care' bit.

In FIG. 4, the leftmost bit of the frame code first reaches the shift register 204 and is shifted out first. Thus, the first bit of the frame code is shifted completely out of range through the shift register 204 before the last bit is received. Conversely, the last bit of the frame code (extreme right bit) is the bit most recently shifted into the shift register 204 and is at the far left bit position (bit 0) in the shift register 204 as shown in FIG. .

In Fig. 4, if both of the shift registers 204 bits 0 and 4, representing the extreme left two bits of the frame code, are logical '1' bits, then the output of the first NAND gate 302 is a logical '0' signal, Otherwise, it is a logic '1' signal. The output of the first NOR gate 304 if the shift register 204 bits 8, 12, and 16 are all logical '0' signals, representing the next three bits of the frame code and the output from the first NAND gate 302. The signal CC FRAME at the terminal is a logic '1' signal indicating that a closed caption frame code has been detected.

If bits 8, 12, 20, and 28 from the shift register 204 are all logic '1' signals, then the output from the second NAND gate 306 is a logic '0' signal. If the bit 4 from the shift register 204 and the output of the second NAND gate 306 are both logical '0' signals, then the signal GS FRAME at the output terminal of the second NOR gate 308 is gemsta. Logic '1' signal indicating that a frame code has been detected. Since the frame code bits are 1 microsecond each in duration and oversampled by a 4 MHz clock (ie, four consecutive samples of each frame code bit are stored in the shift register), the GS FRAME signal is shifted four times. It remains valid for clock cycles.

The particular subset of 5 bits chosen for use by the frame code detector of the present invention is selected based on an experiment aimed at maximizing detection of a valid frame code in a weak signal state, wherein the weak signal state is arbitrary, or It is equivalent to a signal containing white noise (correlated noise may produce different results). By implementing the frame code detector as shown, only a few relatively simple gates are needed if the performance is substantially the same as the detector that processes all the frame code bits. However, implementing a frame code detector that handles all frame code bits includes a larger shift register (44 shift register bits to accommodate all 11 frame codes of the Gemstar frame code), and those 11 bits (closed captions). It requires substantially more complex combinatorial logic circuitry to handle 8 bits for the frame code.

FIG. 5 is a more detailed view, partially block-shaped and partially logic, showing a portion of the controller circuit 212 shown in FIG. 3, wherein the controller circuit 212 is in the GS FRMAE and CC FRAME signals, respectively. In response, it generates GS MODE and CC MODE signals. In FIG. 5, the 4 MHz clock signal from the crystal oscillator 40 (FIG. 2) is coupled to the input terminal of the inverter 402. The output terminal of the inverter 402 is coupled to each clock input terminal of the first D flip flop 404 and the second D flip flop 406, and the first input terminal of the closed caption (CC) frame detector circuit 420. do. As described above, the FRAME WINDOW signal generated internally from the composite synchronization signal is coupled to the first input terminal of the AND gate 408 and the second input terminal of the CC frame detector 420.

The GS FRAME signal from frame code detector 208 (FIG. 3) is coupled to the second input terminal of AND gate 408. An output terminal of the AND gate is coupled to the D input terminal of the first D flip flop 404 and the first input terminal of the first NAND gate 410. The Q output terminal of the first flip flop 404 is coupled to the second input terminal of the first NAND gate 410. The output terminal of the first NAND gate is coupled to the first input terminal of the second NAND gate 412. The output terminal of the second NAND gate 412 is coupled to the D input terminal of the second flip flop 406. The Q output terminal of the second flip flop 406 generates a GS MODE signal coupled to the latch 210. The Q output terminal of the second flip flop 406 is also coupled to the input terminal of the second inverter 414. The output terminal of the second inverter 414 is coupled to the second input terminal of the second NAND gate 412. The combination of the AND gate 408, the first D flip flop 404, the second D flip flop 406, the first NAND gate 410, the second NAND gate 412, and the inverter 414 is a gemsta ( GS) form a frame detector.

The CC FRAME signal from frame code detector 208 (FIG. 3) is coupled to the third input terminal of CC frame detector 420. CC frame detector 420 is configured identically to GS frame detector 416 and operates in the same manner (more specifically described below). The output terminal of the CC FRAME detector generates a CC MODE signal and is coupled to the latch 210.

During operation, at the beginning of each horizontal line, the first and second D flip flops 404 and 406 are driven by circuitry (not shown) of known design, ie in response to the horizontal sync component in the composite video signal. A reset signal is generated and reset by supplying the reset signal to a reset input (not shown in FIG. 5) of each flip flop 404 and 406. Thus, the signal at the Q output terminals of the first and second D flip flops 404 and 406 at the beginning of the horizontal line are both logical '0' signals. Therefore, the GS MODE output signal is a logic '0' signal. Moreover, the GS FRAME input signal is a logic '0' signal until the gemsta frame code is detected (as shown in FIG. 1). As long as the FRAME WINDOW signal remains a logic '0' signal, the AND gate 408 will cause the Q output terminal of the first D flip-flop 404 to be a logic '0' signal when clocked by the inverted 4 MHz clock signal. Are generated continuously, which becomes a disabled state and generates a logic '0' signal. The first NAND gate 410 is thus deactivated and generates a logic '1' signal. The output of inverter 414 is similarly a logic '1' signal. Thus, the output of the second NAND gate 412 is a logic '0' signal, where the second D flip-flop 406 is logic '0' at the Q output terminal when the signal is clocked by an inverted 4 MHz clock signal. Generate the signal continuously. The GS frame detector 416 remains in this state unless any GS FRAME signal pulses are received.

The GS frame detector 416 recognizes receipt of a valid gemsta frame code as long as the code occurs in two consecutive periods of a 4 MHz clock signal (a valid frame code signal is available in four consecutive periods of a 4 MHz clock signal). This is due to the oversampling of one microsecond frame code bit by the 4 MHz clock as described above). This improves the accuracy of the frame code detection process. The AND gate 408 is possible when the FRAME WINDOW signal that defines the time window in which the valid frame code occurred is activated (as shown in FIG. 1). If the FRAME WINDOW signal is activated, any pulse on the GS FRAME signal will pass through the AND gate 408. Otherwise, AND gate 408 remains inactive and generates a logic '0' signal at the output terminal.

If a logic '1' pulse occurs on the GS FRAME signal while the FRAME WINDOW signal is active, the logic '1' is supplied to the D input terminal of the first flip flop 404. The first D flip-flop 404 is clocked by an inverted 4 MHz clock signal, ie a clock signal delayed by half of the period compared to the 4 MHz clock signal. When the first D flip flop 404 is clocked, a logic '1' signal appears at the Q output terminal. This enables the first NAND gate 410.

If the GS FRAME signal remains a logic '1' signal for the period following the 4 MHz clock signal, then the GS FRAME signal causes the first NAND gate 410 to generate a logic '0' signal. Since the Q output terminal of the second flip flop 406 is still a logic '0' signal, the output terminal of the inverter 414 generates a logic '1' signal. However, a logic '0' signal from the first NAND gate 410 causes the second NAND gate 412 to generate a logic '1' signal at the output terminal. This logic '1' signal is clocked through the second flip flop 406 in the next period of the inverted 4 MHz clock signal. The Q output terminal of the second flip flop 406, and the GS MODE signal, become a logic '1' signal, as shown in FIG. The logic '1' signal at the output of the second flip flop 406 causes the inverter 414 to generate a logic '0' signal at the output terminal. This causes the second NAND gate 412 to alternate between generating a logic '1' signal. This causes the second flip flop 406 to continuously generate a logic '1' GS MODE signal when clocked by the inverted 4 MHz clock signal. Thus, as described above, when the GS FRAME signal is detected in two consecutive 4 MHz clock signal periods, the GS MODE signal is activated and remains active until reset at the beginning of the next horizontal line.

However, if the GS FRAME signal does not remain a logic '1' signal in the next consecutive period of the 4 MHz clock signal, then the AMD gate 408 returns a logic '0' that returns the first flip flop 404 to a stopped state. Generates a signal, i.e., the Q output terminal generates a logic '0' signal. Thus, the first NAND gate 410 is deactivated to generate a logic '1' signal. This causes the second NAND gate 412 to generate a logic '0' signal that alternately holds the second flip flop 406 in the stopped state, i.e., the Q output terminal generates a logic '0' signal. Thus, the GS MODE signal remains logic '0' when the GS FRAME signal is active for only one 4 MHz clock period.

As mentioned above, the CC FRAME detector 420 is configured identically to the GS FRAME detector 416 and, when the FRAME WINDOW signal is active, the logic '1 when the CC FRAME signal is present for two consecutive 4 MHz clock periods. It works the same way to generate the CC MODE signal. After that, the CC MODE signal remains a logic '1' signal until the start of the next horizontal line.

FIG. 6 shows a portion of the controller circuit 212 of FIG. 3 controlling the SHIFT CLOCK signal supplied to the shift register 204, in partly block form and partly in logic form. In FIG. 6, as described above, the LINE signal generated therein in response to the composite synchronization signal is coupled to the first input terminal of the first inverted input OR gate 502 and the input terminal of the inverter 504. The output terminal of the inverter 504 is coupled to the first input terminal of the NOR gate 506, and to the interrupt request signal output terminal IRQ coupled to the microprocessor 50 (FIG. 2).

The 4 MHz clock signal from the crystal oscillator 40 (FIG. 2) is input to the input terminal of the counter 508, the clock input terminal of the D flip-flop 510, and the first input terminal of the first NAND gate 512. Combined. The first output terminal of the counter 508 generates a gemstar clocking signal GS CLOCK coupled to the first input terminal of the second NAND gate 514. The second output terminal of the counter 508 generates a closed caption clocking signal CC CLOCK coupled to the first input terminal of the third NAND gate 516. An output terminal of the first NAND gate 512 is coupled to a first input terminal of the second inverted input OR gate 518. The output terminal of the second NAND gate 514 is coupled to the second input terminal of the second OR gate 518, and the output terminal of the third NAND gate 516 is the third input terminal of the second OR gate 518. Is coupled to. The output terminal of the second OR gate generates a SHIFT CLOCK signal coupled to the clock input terminal of the shift register 204 (FIG. 3). In combination, the NOR gate 506, the first, second and third NAND gates 512, 514 and 516 and the second OR gate 518 form a multiplexer 560.

From the mode signal control circuit shown in FIG. 5, the GS MODE signal includes a second input terminal of the NOR gate 506, a first input terminal of the third OR gate 520, and a second input terminal of the second NAND gate 514. 2 is coupled to the input terminal. The CC MODE signal from the mode signal control circuit is coupled to the third input terminal of the NOR gate 506, the second input terminal of the third OR gate 520, and the second input terminal of the third NAND gate 516. do. As shown in FIG. 1, the output terminal of the NOR gate 506 generating the FAST CLOCK signal is coupled to the second input terminal of the first NAND gate 512.

An output terminal of the third OR gate 520 is coupled to the D input terminal of the D flip flop 510 and the first input terminal of the fourth NAND gate 522. The Q output terminal of the D flip flop 510 is coupled to the input terminal of the second inverter 524. The output terminal of the second inverter 524 is coupled to the second input terminal of the fourth NAND gate 522. In combination, the third OR gate 520, the D flip flop 510, the second inverter 524, and the fourth NAND gate 522 form a counter reset circuit 550. An output terminal of the fourth NAND gate 522 is coupled to a second input terminal of the first OR gate 502. The output terminal of the first OR gate 502 is coupled to the reset input terminal R of the counter 508.

During operation, the shift register 204 (FIG. 3) is set to four speeds before the valid frame code is detected during the active portion of the VBI horizontal line specified by the data in the register REG in the controller circuit 212. It is clocked at one of the following: a high clock rate of MHz, a Gemstar data rate of 1 MHz after the Gemstar frame code is detected, and a closed caption data rate of 500 Hz after the closed caption frame code is detected. Counter 508 receives the 4 MHz clock signal and, in a known manner, i.e., using a flip-flop divider step, a 1 MHz gemstar clocking signal GS CLOCK, and a 500 Hz closed caption clocking signal CC. Frequency division of the 4 MHz clock signal to produce a CLOCK. The 4 MHz clock signal, i.e., the GS CLOCK signal and the CC CLOCK signal, is supplied to the data input terminal of the multiplexer 560. The multiplexer 560 is controlled by the inverted LINE signal, GS MODE signal, and CC MODE signal to generate the SHIFT CLOCK signal at the appropriate frequency.

As described above, as shown in FIG. 1, the LINE signal, GS MODE signal, and CC MODE signal are logical '0' signals at the beginning of each horizontal line. In response to the logic '0' LINE signal, the first OR gate 502 provides a logic '1' signal to the reset input terminal R of the counter 508, which remains in the reset state. The LINE signal becomes a logic '1' signal during the active portion of the VBI horizontal line specified by the data in the register REG in the controller circuit 212. In response to the logic '1' LINE signal, the first OR gate 502 provides a logic '0' signal to the reset input terminal R of the counter 508, which begins to operate normally.

The LINE signal is inverted by the first inverter 504. Thus, the inverted LINE signal is a logic '0' signal during the active portion of the VBI horizontal line specified by the data in the register REG, otherwise it is a logic '1'. Thus, at the beginning of the active portion of the designated line, both the inverted LINE signal, GS MODE signal, and CC MODE signal are logic '0'. In response to both the inverted LINE signal, the GS MODE signal, and the CC MODE signal, which are logic '0' signals, the NOR gate 506 generates a logic '1' signal that activates the first NAND gate 512. When activated, the first NAND gate 512 delivers a 4 MHz clock signal to the output terminal and, at the same time, sends a GS CLOCK signal from the second OR gate 518 in response to a GS MODE signal of logic '0'. The blocking second NAND gate 514 is deactivated, and in response to the CC MODE signal being a logic '0' signal, the third NAND gate 516 blocking the CC CLOCK signal from the second OR gate 518 is deactivated. . The second OR gate 518 delivers a 4 MHz signal to an output terminal, which is alternately coupled to the clock input terminal of the shift register 204. Thus, at the beginning of the active portion of the designated horizontal line, the moving clock is a 4 MHz signal.

If no gemsta or closed caption frame code is detected at the specified horizontal line, the shift clock signal control circuit of Figure 6 remains in this state until the end of the active portion of the line. At the end of the active portion of the line, the LINE signal becomes a logic '0' signal and the inverted LINE signal becomes a logic '1' signal. As noted above, a logic '0' LINE signal places the counter 508 in a reset state. The logic '1' inverted LINE signal sets a condition on the NOR gate 506 to generate a logic '0' signal at the output terminal, where the logic '0' signal has a second OR gate 518 and a shift register ( Blocking the 4 MHz signal at clock input terminal of 204 disables first NAND gate 512.

When the gemsta frame code is detected, as described above and shown in FIGS. 4 and 5, the GS MODE signal becomes a logic '1' signal. In response to the logic '1' GS MODE signal, the NOR gate 506 deactivates the first NAND gate 512 and blocks the 4 MHz signal to the second OR gate 518 to block the 4 MHz signal. from the second OR gate (518)}, generating a logic '0' signal at the output terminal. At the same time, a logic '1' GS MODE signal activates a second NAND gate 514, which passes a GS CLOCK signal from the counter 508 to the second OR gate 518, Transfer to the clock input terminal. The final waveform is shown in Figure 1 as the GS SAMPLE CLOCK waveform.

When the closed caption frame code is detected, the CC MODE signal becomes a logic '1' signal. In response to the logic '1' CC MODE signal, the NOR gate 506 generates a logic '0' signal at the output terminal, which causes the first NAND gate 512 to be deactivated and the second Block the 4 MHz signal to the OR gate 518. At the same time, a logic '1' CC MODE signal activates the third NAND gate 516, which passes the CC CLOCK signal from the counter 508 to the second OR gate 518, and shifts the shift register ( To the clock input terminal of 204. The final waveform is shown in FIG. 1 as the CC SAMPLE CLOCK waveform.

To adjust the phase of the shift register 204 to the center of the data bit period, the counter 508 is reset when either the GS MODE or CC MODE signal becomes a logic '1' signal. At the beginning of each horizontal line, both GS MODE or CC MODE signals are logical '0' signals. This causes the third OR gate 520 to generate a logic '0' signal. This logic '0' signal causes the NAND gate 522 to be deactivated and applied to the fourth NAND gate 522, which generates a logic '1' COUNTER RESET signal. At the same time, a logic '0' signal at the output terminal of the third OR gate 520 is clocked through the D flip flop 510 at each 4 MHz clock period at the Q output terminal. The logic '0' signal at the Q output terminal of flip flop 510 is inverted by a second inverter 524 which provides a logic '1' input signal to the fourth NAND gate 522 (deactivated).

The logic '1' COUNTER RESET signal from the fourth NAND gate 522 is supplied to the first OR gate 502. In response to this logic '1' signal, the first OR gate 502 provides a logic '0' signal to the reset input terminal R at the counter 508. In response to a logic '0' reset signal, counter 508 operates normally.

When either the GS MODE or CC MODE signal becomes a logic '1', the third OR gate 520 generates a logic '1' signal at the output terminal. This signal activates the fourth NAND gate 522. The activated fourth NAND gate 522 generates a logic '0' signal at the output terminal as a COUNTER RESET signal in response to a logic '1' signal from the second inverter 524. The logic '0' COUNTER RESET signal causes the first OR gate 502 to provide a logic '1' signal to the reset input terminal R of the counter 508 which is placed in the reset state.

In the next 4 MHz clock period, a logic '1' signal from the third OR gate 520 is latched through the D flip flop 510 and appears at the Q output terminal. This logic '1' signal again deactivates the fourth NAND gate and is inverted by the second inverter 524, which supplies a logic '0' signal to the fourth NAND gate 522. Thus, the fourth NAND gate 522 again generates a logic '1' signal, causing the first OR gate 502 to generate a logic '0' signal, from the stopped and zeroed state. Except that, the counter 508 is back to normal operation.

Thus, the counter will generate GS CLOCK and CC CLOCK signals with a sampling time (ie, leading edge) properly aligned in the middle of each Gemstar and closed caption data bit interval.

Although the illustrated embodiment is described with respect to gemstar and closed caption data, those skilled in the art will appreciate that the present invention can be used in any data transmission system in which the frame code can be used to identify the format of subsequent auxiliary digital data.

Claims (11)

An auxiliary digital data extractor in a television receiver, comprising: a) a first frame code having a predetermined number of bits and auxiliary data in a first format, b) a second having the predetermined number of bits and auxiliary data in a second format An auxiliary digital data extractor in a television receiver comprising a source of a composite video signal comprising an auxiliary digital data component, the frame code of one of the frame codes, A predetermined number, coupled to the composite video signal source, responsive to a first suitable subset of the predetermined number of frame code bits to detect the first frame code, and to detect a second frame code A frame code detector, responsive to a second suitable subset of frame code bits of; The composite video signal source and the source to selectively receive auxiliary data of the first format in response to the detection of the first frame code, and auxiliary data of the second format in response to the detection of the second frame code. Auxiliary digital data extractor in a television receiver, characterized by an auxiliary data utilization circuit coupled to a frame code detector. The method of claim 1, A slicer, coupled to the composite video signal source, to generate a digital bit stream representing the composite video signal; A register coupled to the slicer for storing samples of the digital bit stream from the slicer, the register having an output terminal responsive to a clocking signal and generating the predetermined number of bits; At a first rate when storing a digital bit stream sample representing a frame code, at a second rate when storing a sample representing ancillary data of the first format, and at a third rate when storing a sample representing the secondary data of the second format; Further comprising a register controller coupled to the frame code detector for adjusting the register to sample the digital bit stream, the register controller having an output terminal for generating the clocking signal for the register, The frame code detector is coupled to the register, responsive to a first subset of register output terminal bits corresponding to the first subset of frame code bits to detect the first frame code, and reconstruct the second frame code. And a second subset of register output terminal bits corresponding to the second subset of frame code bits to detect. 3. The register clocking of claim 2 wherein the register controller is adapted to adjust the register to oversample a signal representing the composite video signal from the slicer when storing a digital bit stream sample representing the frame code. Circuitry for generating a signal at said first rate, The frame code detector further comprises circuitry for detecting one of the first and second frame codes only when one of the first and second frame codes is detected for two consecutive digital bit stream samples. Auxiliary digital data extractor in a television receiver. The method of claim 2, wherein the frame code detector, A first combinational logic circuit coupled to the first subset of register output terminal bits to generate a signal when the signal at the first subset of register output terminals corresponds to the first frame code; Further comprising a second combinational logic circuit coupled to the second subset of register output terminal bits to generate a signal when the signal at the second subset of register output terminals corresponds to the second frame code. An auxiliary digital data extractor in a television receiver. The method of claim 1, A slicer coupled to the composite video signal source to produce a digital bit stream representing the composite video signal; A register coupled to the slicer for storing samples of the digital bit stream from the slicer and having an output terminal responsive to a clocking signal and generating frame code bits less than the predetermined number of frame code bits Wow, At a first rate when storing a digital bit stream sample representing a frame code, at a second rate when storing a sample representing ancillary data of the first format, and at a third rate when storing a sample representing the secondary data of the second format; Further comprising a register controller coupled to the frame code detector and having an output terminal for generating the clocking signal for the register to adjust the register to sample the digital bit stream, The frame code detector is coupled to the register, responsive to a first subset of register output terminal bits corresponding to the first subset of frame code bits to detect the first frame code, and reconstruct the second frame code. And a second subset of register output terminal bits corresponding to the second subset of frame code bits to detect. The method of claim 5, The register controller is adapted to store a register clocking signal for the register at the first rate such that when storing a digital bit stream sample representing the frame code, the register is adjusted to oversample a signal representing the composite video signal from the slicer. Circuitry for generating The frame code detector further comprises circuitry for detecting one of the first and second frame codes only when one of the first and second frame codes is detected for two consecutive digital bit stream samples. Auxiliary digital data extractor in a television receiver. The method of claim 5, wherein the frame code detector, A first combinational logic circuit, coupled to the first subset of register output terminal bits, for generating a signal when the signal at the first subset of register output terminals corresponds to the first frame code; Further comprising a second combinational logic circuit, coupled to the second subset of register output terminal bits, to generate a signal when the signal at the second subset of register output terminals corresponds to the second frame code. An auxiliary digital data extractor in a television receiver. 2. The auxiliary digital data extractor of claim 1, wherein the first and second suitable subsets are different suitable subsets of the predetermined number of frame code bits. The apparatus of claim 1, wherein the frame code detector operates in a first mode of operation to detect any occurrence of auxiliary information of the composite video signal, and detects any occurrence of auxiliary information during the first mode of operation. In response, operating in a second mode of operation to detect a particular occurrence of auxiliary information of the composite video signal. 10. The method of claim 9, wherein during the first mode of operation the frame code detector is responsive to the predetermined number of all frame code bits to detect any occurrence of auxiliary information of the composite video signal, and wherein the second operation And during said mode, said frame code detector is responsive to said first suitable subset or said second suitable subset of said predetermined number of frame code bits to detect said specific occurrence of auxiliary information of said composite video signal. Auxiliary digital data extractor in a television receiver. delete