MXPA00006183A - An auxiliary digital data extractor in a television. - Google Patents

Abstract

An auxiliary digital data extractor in a television receiver includes a source of a composite video signal. The composite video signal includes an auxiliary digital data component which is either a first frame code having a predetermined number of bits and auxiliary data in a first format, or a second frame code having the same number of bits and auxiliary data in a second format. A frame code detector is coupled to the composite video signal source. The frame code detector is responsive to one subset of the frame code bits to detect the first frame code and to a different subset of frame code bits to detect the second frame code. An auxiliary data utilization circuit is coupled to the composite video signal source and the frame code detector. The auxiliary data utilization circuit receives auxiliary data in the either first format when the first frame code is detected or the second format when the second frame code is detected.

Description

AN EXTRACTOR OF AUXILIARY DIGITAL DATA ON A TELEVISION The present invention relates to a television receiver that includes a system for identifying and extracting auxiliary digital data, having a plurality of formats, inserted in the vertical extinction range of a video signal of TV. At present, the auxiliary data, such as for example, subtitling information and extended data service information (XDS) is transmitted in a digital form during the vertical extinction interval of standard television signals. The subtitling information represents the subtitling characters, and the extended data service information includes a variety of auxiliary data. This information is inserted into known locations in the vertical extinction range of the television video signal and is formatted in a known manner. In the NTSC television signal in the United States of America the line 21 in field 1 is reserved for subtitling information, and line 21 of field 2 is reserved for extended data service information. With reference to Figure 1, the subtitling signal is illustrated in the second waveform of the upper part, called SUBTITULATION SIGNAL. This signal includes a first interval of 10.5 microseconds (μe) in which the signal nominally remains at 0 IRE of amplitude. This is followed by a clock operation input interval of 14 μß containing seven cycles of a 500 kHz sine wave clock signal having a peak-to-peak amplitude which is the same as the subtitling data, which follows . The peak-to-peak amplitude is nominally \., 50 IRE. The operating input interval is followed by a period of 3 μß of signal 0 IRE. After the signal interval of 0 IRE of 3 μß, a start bit of 2 μß duration occurs, followed by 16 data bit intervals, each also of a duration of 2 μe, in which the data is transmitted in a non-return to zero (NRZ) format. In this way two bytes of x are transmitted. , the subtitling information. A subtitling processor in a receiver extracts subtitling data from its location in the vertical extinction range and displays that information in the television display device. The auxiliary digital information other than extended data service and subtitling information may also be transmitted in the vertical extinction range, using the same format eg television program schedule information. The Starsight company has provided a programming service in which the programming information was transmitted in the vertical extinction range of the video signal, using the same format as the subtitling information. A programming processor in a receiver extracts programming data from its location in e! vertical extinction interval and displays that information, allowing the viewer to make 25 selections of television program based on the programming data displayed. However, recently, the company Gemstar has proposed another format for auxiliary digital data, specifically television program programming data. No location in the vertical extinction range has been reserved for the Starsight or Gemstar programming information. Therefore, different transmitters can freely include it in any location in the vertical extinction range, except for the locations (lines 21 in fields 1 and 2) reserved for subtitling information and extended data service information. Also, the data transmitted in the proposed Gemstar system, can sometimes be in the subtitling format, described above, and other times be in a recently proposed format, called the Gemstar format in the rest of this application. The signal of the Gemstar format is illustrated in Figure 1 as the third waveform from the top called GEMSTAR SIGNAL. A Gemstar format line in the vertical extinction range also starts with a 10.5 IRE nominal signal. But that interval is followed by only 5 cycles of a 500 kHz sine wave operation input clock signal, peak to peak of 50 IRE nominally. The operating input clock signal is immediately followed by a frame of nine digital bits identifying the code that has the default value of 011101101. Each bit in the frame code takes 1 μe, and is in non-return to zero format. The frame code is immediately followed by 32 bits of data, each also taking 1 μß, in non-return to zero format. In this way, four bytes of programming data are transmitted at the subtitling location in the vertical extinction range. Again, a programming processor in the receiver extracts the programming data from its location in the vertical extinction range and allows the viewer to make selections based on the programming data. It is desirable to provide an auxiliary information decoder that reliably decodes multiple auxiliary data formats such as Gemstar format data and subtitling data. One problem that can arise when decoding auxiliary data is that signal noise can cause data to be decoded incorrectly. For example, noise can cause one or more bits of a frame code to be incorrect. As a result, a frame code detector can process a frame code that contains errors related to noise and incorrectly indicate the type of data that exists in a particular portion of a television signal. For example, a decoder that processes a Gemstar frame code that contains erroneous bits may incorrectly indicate that the line interval associated with the frame code does not contain Gemstar data. As a result, the decoder can ignore the line interval instead of decoding the data as desired.

In accordance with the principles of the present invention, an auxiliary digital data extractor in a television receiver processes a composite video signal including auxiliary digital data components having either a first frame code having a predetermined number of bits and auxiliary data in a first format, or a second frame code having the same number of bits and auxiliary data in a second format. A frame code detector responds to a subset of the frame code bits to detect the first frame code and a different subset of frame code bits to detect the second frame code. An auxiliary data utilization circuit receives auxiliary data in either the first format when the first frame code is detected or the second format when the second frame code is detected. In accordance with another aspect of the invention, an auxiliary information decoder has a first mode of operation for detecting any occurrence of auxiliary information in a signal and a second mode of operation for detecting a particular occurrence of auxiliary information in the signal. The invention will be explained with reference to the drawings in which: Figure 1 is a waveform diagram useful in understanding the operation of the present invention; Figure 2 is a block diagram of a portion of a television receiver incorporating the present invention; Figure 3 is a more detailed block diagram of a vertical extinction range data extractor according to the present invention; Figure 4 is a more detailed, partly block-like, and partly in logic form illustrating a frame code detector that can be used in a vertical extinction range data extractor illustrated in Figure 3; and Figures 5 and 6 are more detailed diagrams, partly in block form, and partially in logical form illustrating portions of the controller circuit illustrated in Figure 3. In the remainder of this application, the term "television receiver" will refer to a system capable of receiving and processing a television signal, regardless of whether or not that system is capable of providing the video image and the associated audio component. For example, the term "television receiver" is intended to refer to a standard television receiver with a display and speakers, as well as refer to the circuits in a video tape recorder (VC R) or satellite box or cable on top of the apparatus, all of which contain circuits capable of receiving and processing a television signal, but not to display the image or provide the sound represented by a television signal. In addition, in the rest of this application, the auxiliary digital information will refer to either subtitling information or Gemstar programming information. Fig. 2 is a block diagram of a portion of a television receiver incorporating the present invention. In Figure 2, only the portions of the receiver necessary to understand the operation of the present invention are illustrated. Those skilled in the art will understand that other elements are necessary to operate a television receiver, and how to interconnect those elements with the elements illustrated in Figure 2. In Figure 2, an input terminal 5 is coupled to a source (not shown). ) of a composite video signal. For example, in a standard television receiver, this source may include an antenna or cable connection, radio frequency and intermediate frequency amplifiers, a detector, and possibly an element for separating the audio component from the video component. As another example, in a standard video tape recorder, the source may include a tape transport mechanism, tape reading head and re-reading amplifiers. The input terminal 5 is coupled to respective input terminals of a synchronization component separator 10., and a data separator 30. A composite synchronization signal output terminal S of the synchronization component separator 10 is coupled to a corresponding input terminal S of a vertical extinction interval data extractor (VBI). An output terminal of the data separator 30 is coupled to a vertical extinction range signal input terminal V of the vertical extinction range data extractor. A salt terminal of a crystal oscillator 40 is coupled to a clock input terminal (CLOCK) of the vertical extinction range data extractor 20. A microprocessor 50 is coupled to the vertical extinction range data extractor via an eight-bit bidir-ec data bus. A control output terminal of the microprocessor 50 is coupled to a corresponding input terminal of the vertical extinction interval data extractor 20, while an output terminal of the vertical extinction interval data extractor 20 is coupled to a corresponding input terminal of the microprocessor 50. In operation, the composite video signal in i5 is a standard composite video signal, such as, in the United States of North America, the composite video signal NTSC, and contains a component of video and a synchronization component (among other components not applicable to the understanding of the present invention). The synchronization component separator 1 0 operates in a known manner to separate the composite synchronization component from the composite video signal and provides that synchronization component to the vertical extinction range data extractor 20. The data separator 30 produces a serial current of digital bit signals representing the composite video signal in a known manner. When the value of the composite video signal is greater than the value of a separation level, the digital output signal of the separator 30 is at a first logical level, and when the value of the video signal is less than the value of the Separation level, the digital output signal is in a second logical level. In the exemplary embodiment described herein, the first and v | second logical levels correspond to the logical values "1" and logical "0", respectively. With reference to Figure 1, the second waveform of the upper SUBTITUTE SIGNAL illustrates the subtitle format data signal. The operating input signal, which consists of seven sine wave cycles, has a peak-to-peak value that is the same as the signal from the non-return to zero data that follows. The base value of the sine wave is nominally 0 I R E and the peak value is nominally 50 I RE. Therefore, the separation level signal, selected to be halfway between the base and peak values, is nominally 25 IRE, as illustrated in the waveform of the SIGNAL SUBTITUTE LATION. The base and peak values of the received operation input signal may, of course, vary, but it is anyway equal to the values of the corresponding portions of the following non-return to zero data. Therefore, the level of separation can be established at the midpoint between the values 2. Real base and peak received from the operating input signal in a known manner. Starting with the last two cycles of the operating input signal, 9 ß of the output of the data separator 30. which represent the frame code, are illustrated in the SIGNAL OF SUBTITU LATION. When the SEAL OF ITS BTITUlATION is greater than the illustrated separation level of IRE, the digital output signal of the separator 30 is a logical signal "1", and when the BITULATION SIGNAL is smaller than the level of illustrated separation, the value of the digital output signal is a logical signal "0". Therefore, the binary frame code produced by the data separator 30 in response to the SUBTITULATION SIGNAL, is 1010001 1. The microprocessor 50 provides data specifying the line of the vertical extinction range from which the auxiliary digital data is to be extracted to the vertical extinction range data extractor 20 via the data bus and control signals. This data can be stored in a register in the vertical extinction interval data extractor 20 in a known manner. The vertical extinction range data extractor 20 operates, in a manner described in more detail below, to process the digitized vertical extinction range signal of the horizontal line of vertical extinction range previously specified by the microprocessor 50. The extractor of vertical extinction interval data 20 determines the presence and format of, and extracts the data in the vertical extinction range. At the end of that horizontal line of vertical extinction range, the microprocessor 50 is notified by a request for interruption in the output terminal I RQ. In response to the interrupt request, the microprocessor 50 determines whether the vertical extinction interval data was present on that line, and if so, transfers the extra data from the vertical extinction interval data extractor 20 to the microprocessor. via the data bus by means of read activation signals provided to the vertical extinction interval data extractor 20 via the control output terminal, as described in more detail below. Figure 3 is a block diagram in more detail of a vertical extinction range data extractor 20 in accordance with the present invention. In Figure 3, an input terminal V receives the digitized vertical blanking interval component of the video signal of the data separator 30 (of Figure 2). The input terminal V is coupled to a serial data input terminal SI of a 32-bit shift register 204. A 32-bit parallel output terminal PO of the shift register 204 is coupled to respective input terminals of a parity generator 206, a frame code detector 208 and a holding circuit 210. A four-bit output terminal of the parity generator 206 is coupled to a corresponding input terminal of the holding circuit 210. The first and second Exit terminals of the 208 frame code detector, which produce the respective signals of their LATIN BATTERY and GEMSTAR BOX (described in more detail below) are coupled to corresponding input terminals of a controller circuit 2 1 2. An input terminal S, receives the signal from compound synchronization of the synchronization component separator 10 (of Figure 2). The input terminal S is coupled to a corresponding input terminal of the control circuit 212. The 4MHz clock signal of the crystal oscillator 40 (of FIG. 2) is coupled to a clock signal input terminal of the controller circuit 212. A first output terminal of the controller circuit 212, which produces a shift clock signal, is coupled to a shift clock input terminal of the shift register 204. The second and third output terminals of the circuit controller 212, which produce the signals GEMSTAR MODE and MODE OF YOUR LATTON BTITU. respectively, (described in greater detail below) are coupled to corresponding input terminals of the holding circuit 210. A fourth output terminal of the controller circuit 212, which produces a LINE signal, is coupled to a clock input terminal. R ELOJ of holding circuit 210. A fifth output terminal of controller circuit 212, which produces an interrupt request signal I RQ, is coupled to an output terminal I RQ, which is coupled to microprocessor 50 (of FIG. 2). ). A CONTROL input terminal is coupled to a corresponding input terminal of the controller circuit 212, and to five input terminals: EN B 1, ENB 2, ENB 3, EN B 4 and IN BS of a holding circuit 21 0. An eight-bit bidirectional data bus terminal is also coupled to the microprocessor 50. The data bus terminal is coupled to an input terminal of the controller circuit 212 and to five eight-bit data output terminals: DO 1, DO 2, DO 3, DO 4 and DO S of the holding circuit 210. In the general operation, the microprocessor 50 (of Figure 2) transfers data specifying a horizontal line in the vertical extinction range to a REG record in the circuit controller 212, via the data bus and the control signals at the CONTROL input terminal, in a known manner. The controller circuit 212 monitors the composite synchronization signal of the input terminal S. When the horizontal line specified in the REG register occurs, the serial data stream of the signal of the vertical extinction range for that horizontal line, of the separator of data 30 moves through the shift register 204 in response to the displacement clock signal from the driver circuit 212. The frame code detector 208 monitors the 32 bits at the parallel output terminal of the shift register 204 for detect the frame code of either a subtitle format signal or a Gemstar format signal. If a subtitle format signal is detected, an indication that the subtitle format data is available is provided to the holding circuit 210 via the SUBTITLE MODE signal: If a Gemstar format signal is detected, an indication of the that the Gemstar format data are available is provided to the holding circuit 210 via the signal MO DE G EMSTAR. In either of these cases, the auxiliary digital data in the detected format is extracted by the shift register 204 and, together with the associated parity information of the parity generator 206, also stored in the holding circuit 210. If not detected no format signal, an indication that no data is available is stored in the holding circuit 210. At the same time that the above-mentioned information is stored in the holding circuit 210, an interruption signal is provided to the microprocessor 50 via the IRQ signal line. The microprocessor 50, in response to the interrupt request signal, reads the contents of the holding circuit 210, via the data bus and the activation signals of the CONTROL input terminal, all in a manner that will be described with more detail below. Although the illustrated embodiment includes the retention circuit 210, it will be understood by those skilled in the art that it is not absolutely required. If the microprocessor 50 can respond to the I RQ signal, and recover the signals of GEMSTAR MODE and MODE OF ITS BTITU LATION, and the associated digital data and associated parity data before the next occurrence of the line interval of 20 particular vertical extinction range (the vertical extinction range line interval specified by the data in the R EG register in Figure 3) then the holding circuit 210 can be omitted. In this case, the microprocessor 50 reads the data directly from the controller circuit 212, the shift register 204 and the parity generator 206.

The controller circuit 212 includes counters and associated circuits (not shown) of a known configuration, for monitoring the composite synchronization signal of the input terminal S in order to detect vertical fields and count horizontal lines. The controller circuit 212 also includes circuits, also of known configuration, for comparing the current horizontal line with the horizontal line specified by the data in the R EG register. The LINE EA signal is activated (eg, a logic "1" as in the illustrated mode) at the start of the "active portion" of the specified horizontal line, and remains inactive (logical "0") in another way. With reference to Figure 1, the uppermost waveform illustrates the LINE signal EA for the horizontal line in the vertical extinction range specified by the data in the REG record. At the same time that the LINE signal is activated, the controller circuit 21 2 begins to provide a 4 M Hz shift clock to the shift register 204. In this manner, the serial bit stream of the data separator 30 (of Figure 2) which represents the vertical extinction interval video signal, is measured in time through the shift register 204. In the illustrated embodiment, the shift register 204 is measured in time at the major edges of the signal scroll clock. As mentioned above, the vertical extinction interval data signal has the format illustrated in the SIGNAL waveform of its LAT ION or the GEMSTA SIGNAL waveform of Figure 1. The Gemstar format signal GEMSTAR SIGN after an initial period of 10.5 e and an operating clock period of five cycles, it is followed by a range of 9 μe which, when digitized, contains a frame code signal having the digital value of 011101101. During the same time interval of 9 μß, the SUBTITLE SIGNAL subtitle format signal includes a digital bitstream having the value 101000011. In the illustrated mode, the frame code range is the 9 μd interval that follows to the initial period of 9 = and the operating clock entry period of five cycles, which is common to both format signals. That is, the frame code interval begins at the first point where two different format signals have different values, and ends where the auxiliary digital data for both format signals begins. Those skilled in the art will understand that the definition of a frame code period is arbitrary and can include any portion of the signal that is sufficient to distinguish data in a data format in the other format. The frame code detector 208 monitors the status of the 32 bits in the parallel output terminal of the shift register 204. The frame code detector 208 operates in one of two modes of operation The first mode is a search mode during which the detector searches for any occurrence of auxiliary information such as a box code. That is, in the search mode, it is not known if the auxiliary digital data in the subtitling or Gemstar format is included in the video signal and if so, it is not known which line contains which data. These data could be included in any horizontal line in the vertical extinction interval s: for example, from line 10 to 20 in field 1 or 2. Additionally, it is possible that the data in other formats will be inserted in lines in the vertical extinction interval. To increase the detection certainty and minimize the false identification of an arbitrary signal as the desired format signal, the criteria for detecting the subtitle box code or Gemstar are set in the search mode. All the frame code bits available in the received digitalized vertical extinction interval signal are compared to corresponding bits in the Gemstar frame code of 01 1 101 10 or in the code of I 5 subtitling box of 10100001 1, possibly for more than one sequential video frame during the search mode. Once the presence and location of the auxiliary digital data has been verified in the subtitling or Gemstar format, the search mode is terminated. When the search mode is terminated, the frame code detector 208 enters the second mode of operation, called the setting mode in the remainder of this request, during which a particular occurrence of auxiliary information is detected. That is, in the fix mode, the location of the auxiliary data 5 in the vertical extinction range has been determined and the data representing that location is stored in the REG register in the controller circuit 212. Therefore, the detector it can search for the occurrence of the desired auxiliary information in the particular line interval that is indicated by the data stored in the REG record. The frame code detector 208, in a manner to be described in more detail below, continues to monitor the 32 bits of the shift register 204 to detect either the Gemstar frame code of 01 1 101 10 or the frame code Substitution of 10100001 1. However, in the setting mode, to minimize the interruption in the presence of a noisy signal, the detection criteria to detect either the subtitle box code or the Gemstar picture code are relaxed in relation to those in the search mode. The remainder of this request will describe the fix operation mode, unless the search mode is explicitly specified. Each time the frame code detector 208 detects the Gemstar frame code of 01 1 1 101, a pulse signal GEMSTAR BOX is generated, as shown in Figure 1. Similarly, although not illustrated in Figure 1, each time the frame code detector 208 detects the subtitle frame code of 10100001 1, a pulse signal is generated. TABLE OF ITS BTITUlATION, all the way will describe in more detail below. The control circuit 212 receives the signals C UMBER OF ITS BATTERY AND G EMSTA R SECTOR of the frame code detector 208. To increase the detection accuracy of the frame code, the control circuit 212 generates a signal of PICTURE WINDOW. The TABLE WINDOW signal is derived from the composite synchronization signals, in a known manner, and is active (it is a logical signal "1" in the illustrated mode) by a time interval surrounding the nominal time when either a pulse of GEMSTAR PICTURE or a SUBTITUTE PICTURE could validly occur and is inactive (logical "O") otherwise. In the illustrated mode, the TABLE WINDOW signal is active for a range of 5 μß around the nominal time when a pulse of GEMSTAR PICTURE or SUBTITLE PICTURE should occur, which is 29.5 e of the time when the LINE signal EA is activated. This is illustrated as the TABLE WINDOW waveform in Figure 1. During the time interval when the WINDOW signal PICTURE is active, the signals of its BATTERY CHART and GEMSTAR CUTTER are monitored by the control circuit 212. If a pulse is detected in the GEMSTAR PICTURE signal (as illustrated in the GEMSTAR PICTURE signal in Figure 1) the control circuit 212 causes the GEMSTAR MODE signal to be active (logic "1" in the illustrated mode) as illustrated in the GEMSTAR MODE signal in Figure 1. This indicates that the Gemstar format data is present in the specified horizontal line, and that data follow. The Gemstar format data is in the form of a 32-bit non-return to zero data stream, each bit interval is 1 μ3, as mentioned above. In response to the detection of the GEMSTAR PICTURE signal, the driver circuit 212 provides a shift clock signal to the shift register 204 so that the sampling signals (e.g., leading edges) are generated in the middle of each Gemstar data bit range as illustrated in FIG. the GEMSTAR SAMPLE CLOCK signal in Figure 1. Therefore, for the first portion of the line, for example, until the GEMSTAR PICTURE pulse is detected, the m displacement clock signal is a clock signal of 4 MHz. For the second portion of the line, for example after the GEMSTAR PICTURE pulse is detected, the shift clock signal is a 1 MHz signal in phase so that the leading edges (eg, sampling signals) are synchronized to the center of the Gemstar data bit intervals. Similarly, although not illustrated in FIG. 1, if a pulse is detected in the signal of its BATTERY LATION, the controller circuit 21 2 causes the signal of MODE OF SUBTITULATION is active (logic "1" in the illustrated mode).

This indicates that the subtitling format is present in the specified horizontal line, and that data follows. The subtitle format data is in the form of a 16-bit non-return to zero data stream, each interval being 2 μe. In response to the detection of the PICTURE OF YOUR BITU LATION signal. The circuit The controller 212 provides a shift clock signal to the shift register 204 so that the sampling signals (e.g., the leading edges) are generated in the middle of each subtitle data bit period, as illustrated in FIG. SUBTITLE SAMPLE CLOCK signal in Figure 1. Therefore, for the first portion of the line, for example until the SUBTITULATION PICTURE pulse is detected, the displacement clock signal is a clock signal of 4 MHz. For the second portion of the line, for example after the SUBTITLE PICTURE pulse is detected, the displacement clock signal is a 500 kHz signal in phase so that the main edges (for example, signals from sampling) are synchronized to the center of the subtitle data bit intervals. If the frame code detector 208 does not detect a SUBTITLE PICTURE signal or a GEMSTAR PICTURE signal while the PICTURE WINDOW signal is active, then neither the GEMSTAR MODE nor the SUBTITLE MODE is generated, and no change of frequency and phase occurs in the displacement clock signal. In response to the shift clock signal, the shift register 204 samples the digital signal from the data separator 30 (of FIG. 2) in the middle of the bit slots for the Gemstar format (GEMSTAR SIGNAL of FIG. 1) ) or the subtitling format (SUBTITULATION SIGN) selected by the SUBTITULATION BOX and GEMSTAR PICTURE signals.

At the end of the active portion of the vertical line of vertical extinction range, the shift register 204 contains the data of the vertical extinction range. These data are present in the parallel output terminal PO of the shift register 204, and are supplied to the holding circuit 210. The 32 bits are divided into 4 bytes of 8 bits. Simultaneously, the parity generator 206 calculates four parity bits, one corresponding to each of the divided bytes of the shift register 204. The parity bits are also supplied to the holding circuit 210. When the active portion of the horizontal line of the The vertical extinction interval ends, the LINE signal is made inactive again by the controller circuit 212, as shown in Figure 1. The LINE signal is coupled to the clock input terminal R ELOJ of the holding circuit 210. In response to the LINE signal EA becoming inactive, the holding circuit 210 retains the data signals of the vertical extinction range of the shift register 204, the signals of GEMSTAR MODE and LATAM BATTERY MODE of the driver circuit 212, and the parity bits of the parity generator 206. The four bytes of the shift register 204 are retained in the respective four bytes 12. The four parity bits are retained in four bits of a fifth byte, called the status byte, of the holding circuit 21 0. Finally, the signals of the GEMSTA R MODE and the MODE OF ITS BTI TU LAC ION of the control circuit 212 are retained in the fifth and sixth bits of the fifth state byte in the holding circuit 210. Also in response to the LINE signal becoming inactive, and at the same time the retention n of data and status information in the latch circuit 210, the controller circuit 212 generates an interrupt request signal IRQ, which is provided to the microprocessor 50 (of Figure 2). In a known manner, in response to the IRQ signal, the microprocessor 50 executes an interrupt manipulator routine. The interrupt manipulator routine conditions the microprocessor 50 to read the status byte of the latch circuit 210 by activating the signal to activate the state byte EN B S. In response to the signal to activate the ENB S state byte, the terminal output of the holding circuit 210 that produces the status byte, DO S is coupled to the data bus of the microprocessor 50 and the data is read by the microprocessor 50. The interrupt handler tests the data bits containing the MODE signals OF GEMSTAR AND MODE OF HIS BTITU LAC IO N. If the EMSTAR G MODE bit is active, then the 32 bits of the auxiliary digital data were transmitted on the line of the vertical extinction range, and the four bytes of data are read by the microprocessor 50. In this case, the microprocessor sequentially activates the data byte activation signals ENB 1, EN B 2, EN B 3, and ENB 4. In response to the signal EN B 1, the holding circuit 2 10 places the contents of the first data byte in the data output terminal DO 1 in the data bus, and that data is read by the microprocessor 50. Likewise, the second, third and fourth bytes, in the output terminals D02.DO 3 and DO 4, respectively , they are placed on the data bus in response to the data byte activation signals ENB 2, ENB 3 and ENB 4, respectively. If desired, the microprocessor 50 can also verify the parity of these data bytes by analyzing the four parity bits present in the status byte. In the event that the MODE OF YOUR BITU LATION signal is active, this indicates that subtitling information was transmitted during the line of the vertical extinction interval. However, in this case, only 16 bits or two bytes of auxiliary digital data were transmitted, and only bytes of data in the data output terminals DO 3 and DO 4 contain valid information. The microprocessor reads these bytes of data after providing the respective activation signals. Then, the received data bytes can be processed in the proper manner, such as extracting lines of programming information and displaying this information to the viewer. Figure 4 is a more detailed, partly block-shaped, and partly in a logical form, illustrating the portion of the frame code detector 208 operative during the fixing mode. In Figure 4, the elements that are the same as those illustrated in Figure 3 are designated by the same reference number and are not described in detail. In Figure 4, the shift register 204 is illustrated with the serial input terminal SI and the CLOCK shift clock input terminal, and with 32 parallel one-bit output terminals. The most left output terminal, named "0" contains the most recently received bit. The respective output terminals 0 and 4 are coupled to the first and second input terminals of a negative output gate "Y" ("NAND") 302. The respective output terminals 8, 12 and 16 are coupled to the first, second and third input terminals of a negative output gate "OR" ("OR") 304. The respective output terminals 8, 12, 20 and 28 are coupled to the first, second, third and fourth input terminals of a second gate "NAND" 306. The output terminal 4 is coupled to a first input terminal of a second gate "OR" 308. An output terminal of the first gate "NAN D" 302 is coupled to a fourth input terminal of the "ÑOR" gate 304, and an output terminal of the second gate "NAND" 306 is coupled to a second input terminal of the second gate "ÑOR" 308. An output terminal of the first gate "OR" 403 produces the sign of SUBTITULATION PICTURE, and an output terminal of the second "OR" gate 308 produces the signal CUA DRO DE G EMSTA R. With reference to Figure 1, to the point where a GEMSTA R CADROAD signal or a SUBTITULATION BOARD signal is generated, the digital bitstream of the separator 10 (of FIGURE 2) is sampled at a speed of 4 MHz in response to the RE LOJ signal from MU ESTRA DE GEMSTA R. As each bit in the frame code portion of the signal is 1 μe in duration, each bit is over sampled four times by the shift register 204. That is, each bit is stored in four adjacent locations in the shift register 204. Therefore, in order to properly sample the different bits in the frame code, every fourth bit in the shift register 204 is processed by the detector of frame code. In the current mode, only eight of the nine frame code bits can be stored in the 32-bit shift register 204, consequently, only those eight bits are available for processing to detect a valid subtitle or Gemstar frame code . However, in the illustrated embodiment only a 5-bit sub-series of the available eight-bit series is processed to determine whether a subtitling frame or a Gemstar frame is present. Those five bits, and their values are: (x) xxx0001 1 to detect a valid subtitle box code, and (x) 1 x1 x1 10x to detect a valid Gemstar frame code, where (x) indicates the ninth bit not available, and x indicates a "does not matter" bit. In Figure 4, the bits to the left of the frame code arrive first at the shift register 204, and move outward first. Therefore, the first bit of the frame code travels completely through and out of the shift register 204 before receiving the last bit. Conversely, the last bit of the frame code (bit further to the right) is the most recently moved bit in the shift register 204 and is in the bit position further to the left (bit 0) in the register offset 204 as shown in Figure 4. In Figure 4, if both bits and 4 of the shift register 204, represent the two most right bits K) of the frame code, are logic bits "1", then the output of the first gate "NAND" 302 is a logic signal "0 °, otherwise it is a logic signal" 1". , 12 and 16 of the shift register 204, which represent the next three bits of the frame code, and the output of the first gate "NAND" 302, are all logical signals "0", then the signal at the output terminal of the first gate "NAND" 304, the SUBTITLE TABLE, is a logic signal "1" indicating that a frame code has been detected. subtitling. If the bits 8, 12, 20 and 28 of the shift register 204 0 are all logic signals "1 °, then the output of the second gate" NAND "306 is a logic signal" 0". scroll register 204 and the output of the second gate "NAND" 306 are both logic signals "0", then the signal at the output terminal of the second gate "NAND" 308, FIG. 5 of GE STAR, is a logic signal "1" indicating that a Gemstar frame code has been detected, as the frame code bits are each 1 microsecond in duration and are oversampled by the 4MHz clock (ie, 4 successive samples of each bit of frame code are stored in the shift register s) the GEMSTAR PICTURE signal remains valid for four shift clock cycles The particular subset of five bits selected for use by the frame code detectors of this invention have been selected based on experiments done with the objective of maximizing the detection of valid frame codes under weak signal conditions, which is equivalent to signals that contain white or random noise (the correlated noise can produce other results). By implementing the frame code detectors as illustrated, only a few relatively simple gates are required, while the operation is substantially equivalent to the detectors that process all frame code bits. However, implementing frame code detectors that process all bits of frame code would require a larger shift register (44 bits of 2 shift register to hold the 1 1 bits of frame code of the Gemstar frame code). ) and substantially a more complicated combination logic circuit for processing those eleven bits (eight bits for the subtitling frame code). Figure 5 is a more detailed diagram, partially in 2 block form, and partly in logical form, illustrating a portion of the controller circuit 212 illustrated in Figure 3, which generates the signals of GEMSTAR MODE and MODE OF HIS BTITU LATION in response to the signals of GADSTAR CANDEL and TABLE OF ITS BTITU LATION, respectively. In Figure 5, the 4 MHZ clock signal of the crystal oscillator 40 (of Figure 2) is coupled to an input terminal of the inverter 402. An output terminal of the inverter 402 is coupled to the respective clock input terminals. of a first multi-vibrator D 404 and a second multi-vibrator D 406, and to a first input terminal of a subtitling frame detector circuit (CC) 420.

The TABLE WINDOW signal, generated internally from the composite synchronization signal, as mentioned above, is coupled to a first input terminal of an "AN D" gate 408 and a second input terminal of the subtitle box detector 420 The signal of C UA DRO DE GEMSTA R of the frame code detector 208 (of Figure 3) is coupled to a second input terminal of the "AND" gate 408. An output terminal of the "AND" gate is coupled to an input terminal D of the first multivibrator D 404 and a first input terminal of a first gate "NAND" 410. An output terminal Q of the first multivibrator 404 is coupled to a second input terminal of the first gate "NA ND" 41 0. An output terminal of the first gate "NAN D" is coupled to a first input terminal of a second gate "NAN D" 412. an output terminal of the second "NAN D" gate 412 is coupled to an input terminal D of the second multivibrator 406. An output terminal Q of the second multivibrator 406 generates the GEMSTAR MODE signal that is coupled to the holding circuit 210. The output terminal Q of the second multivibrator 406 is also coupled to an input terminal of a second inverter 414. An output terminal of the second inverter 414 is coupled to a second input terminal of the second gate "NAND" 412. The combination of the gate " AND "408, the first multivibrator D 404, the second multivibrator D 406, the first gate "NAN D" 410, the second gate "NAN D" 412 and the inverter 414 form a Gemstar frame detector (GS). The SUBTITUTE PICTURE signal of the frame code detector 208 (of Figure 3) is coupled to a third input terminal of the subtitle box detector 420. The subtitle box detector 420 is constructed identically to the detector of Gemstar 416, and operates in the same way (described in more detail below). An output terminal of the BATTERY LAYOUT detector produces the BITTING MODE signal, and is coupled to the holding circuit 210. In the operation, at the beginning of each horizontal line, the first and second multivibrators D 404 and FIG. 406 are restarted, by circuits of a known design (not shown) for example by generating a reset signal in response to the horizontal synchronization component in the composite video signal and providing that reset signal to a reset input (not shown) in Figure 5) of each of the multivibrators 404 v y406. Consequently, the signals at the output terminals Q of the first and second multivibrators O 404 and 406 at the start of a horizontal line are both logical signal "0". Therefore, the output signal of GEMSTAR MODE is a logical signal "0". In addition, the input signal of GEMSTAR PICTURE is a logic signal "0" until a Gemstar frame code is detected, ^ lo (as shown in Figure 1). As long as the PACKAGE WINDOW signal remains as a logical "0" signal, the "AND" gate 408 remains deactivated, and produces a logic "0" signal, causing the Q output terminal of the first multivibrator D 404 to continue to produce a logic signal "0" when it is 15 measured in time by the clock signal of 4 MHz. The first gate "NAN D" 410 is deactivated in this way and generates a logic signal "1". The output of the inverter 414 is also a logic signal "1". The output of the second gate "NAN D" 412, therefore, is a logic signal "0" which causes the second multivibrator D 406 to continue to produce a logic signal "0" at its output terminal Q when is measured in time by the inverted clock signal of 4 MHz. The Gemstar 416 frame detector remains in this state as long as a signal pulse of CUA DR ODEG EMSTA R is not received. 25 The Gemstar 416 detector detects receipt of a Gemstar frame code only if that code occurs in two successive cycles of the 4 MHz clock signal. (A frame code signal shall be available for four successive cycles of the 4 MHz clock due to the oversampling of the frame code bits of 1 microsecond by the 4 MHz clock as explained above). This improves the accuracy of the frame code detection process. The "AND" gate 408 is activated when the TABLE WINDOW signal, which defines a time window in which a valid frame code can occur, is activated (as shown in Figure 1). While the TABLE WINDOW signal is active, any pulse in the GEMSTAR PICTURE signal will pass through the "AN D" gate 408. Otherwise, the "AND" gate 408 remains off, produces a logic signal " 0"on your output terminal. If a logic pulse "1" occurs in the PICTURE signal GEMSTA R while the TABLE WINDOW signal is active, a logic "1" is provided to the input terminal D of the first multivibrator 404. The first multivibrator D 404 is measured in time by the inverted clock signal of 4 MHz, that is, a clock signal that is delayed by a half cycle compared to the clock signal of 4 MHz. When the first multivibrator D 404 is measured in time, a logic signal "1" appears in its output terminal Q . This activates the first gate "NA ND" 410. If the GASMAR RATE signal remains as a logic signal "1" in the next cycle of the 4MHz clock signal, the GEMSTAR PICTURE signal conditions the the first "NANO" 410 gate to produce a "0" logic signal. Since the output terminal Q of the second multivibrator 406 is still a logic signal "0", the output terminal of the inverter 414 produces a logic signal "1". However, the logic signal "0" of the first gate "NAN D" 410 conditions the second gate "NAN D" 412 to produce a logic signal "1" at its output terminal. This logic signal "1" is measured in time through the second multivibrator 406 in the next cycle of the inverted clock signal of 4 M Hz. The output terminal Q of the second multivibrator 406, and therefore the MODE signal From GEMSTAR a logic signal "1" is made, as illustrated in Figure 1. The logic signal "1" at the output of the second multivibrator 406 conditions the inverter 414 to generate a logic signal "0" at its output terminal. This deactivates the second gate "NAND" 412, which in turn produces a logic signal "1". This causes the second multivibrator 406 to continue to produce a logic signal "1" of GEMSTAR MODE when measured in time by the inverted 4 MHz clock signal., when a GEMSTAR PICTURE signal is detected in two consecutive cycles of the 4 MHz clock signal, the GEMSTAR MODE signal becomes active, and remains active until the restart at the beginning of the next horizontal line, as It was mentioned earlier. However, if the EMSTAR CUA DRO signal does not remain as a logic signal "1" in the next cycle of the 4 MHz clock signal, the "AND" gate 408 produces a logic "0" signal, that the first multivibrator 404 returns to its static condition, that is, the output terminal Q generates a logical signal "0". Therefore, the first "NAND" gate 410 is deactivated and produces a logic signal "1". This conditions the second gate "NAND" 412 to produce a logical signal "0", which in turn, keeps the second multivibrator 406 in its static condition, that is, the output terminal Q generates a logical signal "0" " Therefore, the GEMSTAR MODE signal remains in logic "0" if the GEMSTAR BOX signal is active for only a 4 MHz clock cycle. As mentioned above, the SUBTITULATION BOX detector 420 is constructed of identical to the detected from GEMSTAR PICTURE 416 and operates in the same manner to generate a logic signal "1" of SUBTITLE MODE when the SUBTITULATION PICTURE signal is present for two consecutive clock cycles of 4 MHZ when the signal of PICTURE WINDOW is active. Then, the SUBTITULATE MODE signal remains as a logical signal "1" until the beginning of the next horizontal line. Figure 6 shows, partially in block form, and partly in logical form, a portion of the controller circuit 212 of Figure 3, which controls the DISPLACEMENT CLOCK signal provided to the shift register 204. In Figure 6, the signal of LINE, generated internally in response to the composite synchronization signal, as described above, is coupled to a first input terminal of a first gate uOR "inverted input 502 and an input terminal of an inverter 504. An output terminal of the inverter 504 is coupled to a first input terminal of a gate "ÑOR" 506 and to the output terminal of the interrupt request signal I RQ, which is coupled to the microprocessor 50 (of Figure 2). 4 MHz of the crystal oscillator 40 (of Figure 2) is coupled to an input terminal of a counter 508, to a clock input terminal of a D 510 multivibrator, and to a er input terminal of a first "NAND" gate 512. A first counter output terminal of the counter 508 generates a Gemstar clock signal (GE STAR CLOCK) that is coupled to a first input terminal of a second gate "NANO "514. A second output terminal of the counter 508 generates a subtitle clock signal (R ELOJ OF ITS BTITU LATION) which is coupled to a first input terminal of a third gate" NAN D "516. An output terminal of the first gate "NA ND" 512 is coupled to a first input terminal of a second gate "O" of inverted input 518; an output terminal of the second gate "NAN D" 514 is coupled to a second input terminal of the second gate "OR" 51 8; and an output terminal of the third gate "NAND" 516 is coupled to a third input terminal of the second gate "OR" 518. An output terminal of the second gate "OR" produces the CLOCKWISE CLOCK signal. , which is coupled to the clock input terminal of the shift register 204 (of Figure 3). In combination, the "OR" gate 506; the first, second and third "NAND" gates 512, 514 and 516; and the second "OR" gate 518 form a multiplexer 560. The GEMSTAR MODE signal of the mode signal control circuits illustrated in FIG. 5 is coupled to a second input terminal of the "ÑOR" gate 506, a a first input terminal of a third gate "OR" 520, and a second input terminal of the second gate "NAND" 514. The signal of MODE OF ITS BTITULATION of the signal control circuits of mode is coupled to a third input terminal of gate "ÑOR" 506, to a second input terminal of the third gate "OR" 520, and to a second input terminal of the third gate "NAN D" 516. A gate output terminal " OR "506, which generates a FAST CLOCK signal, as illustrated in Figure 1, is coupled to a second input terminal of the first gate" NAN D "512. An output terminal of the third gate" OR "520 is coupled to a multivibr input terminal D D 510, and a first input terminal of a fourth gate "NAND" 522. A output terminal Q of the multivibrator D 510 is coupled to an input terminal of a second inverter 524. An output terminal of the second inverter 524 is coupled to a second input terminal of the fourth gate "NAND" 522. In combination, the third gate "OR" 520, the multivibrator D 510, the second inverter 524 and the fourth gate "NANO" 522 form a reset circuit of counter 550. An output terminal of the fourth gate "NAND" 522 is coupled to a second input terminal of the first gate "OR" 502. An output terminal of the first gate "OR" 502 is coupled to a terminal R reset input of counter 508. In operation, shift register 204 (of FIG. 3) is measured in time at one of the three speeds during the active portion of the horizontal line of vertical extinction interval specified by the data in the REG register in the controller circuit 212: at a fast clock rate of 4 MHz before detect a valid frame code, at a Gemstar data rate of 500 KHz after detecting a subtitle box code. The counter 508 receives the 4 MHz clock signal and, in a known manner, for example, using multivibrator divider stages, splits the 4 MHz clock signal to generate a 1 MHz Gemstar clock signal. CLOCK OF GEMSTAR, and a subtitling watch signal of 500 kHz CLOCK OF ITS BTITULACON. The 4 MHz clock signal, the R EOSTA R signal, and the RETURN signal are supplied to the data input terminals of the multiplexer 560. The multiplexer 560 is controlled by the inverted AI line signal, the GEMSTAR MODE signal and the SUBTITLE- TION MODE signal to generate a WIDE SCROLL CLOCK signal at the appropriate frequency. As mentioned above, and as illustrated in Figure 1, the signals of LINE EA. GEMSTAR MODE and SUBTITULATION MODE are logic "0" signals at the beginning of each horizontal line. In response to a logic "0" signal from LINE, the first "OR" gate 502 provides a logic signal "1" to the reset input terminal R of the counter 508, which remains in the reset state. The LINE signal EA is made a logic signal "1" during the active portion of the horizontal line of vertical extinction interval specified by the data in the register REG in the controller circuit 212. In response to a logic signal "1"of LINE, the first" OR "gate 502 provides a logic signal" 0"to the reset input terminal R of the counter 508, which begins to operate normally. The LINE signal EA is inverted by the first inverter 504. Therefore, the inverted AI line signal is a logic signal "0" during the active portion of the horizontal line of the vertical extinction range specified by the data in the register R EG, and a logical signal "1" in another way. Therefore, at the beginning of the active portion of the specified line, all inverted signals of LINE EA, MODE OF G EMSTA R and MODE OF ITS BTITULATION are logical "0". In response to all the inverted signals of LÍ N EA, G MODE EMSTAR and MODE OF ITS BTITU LATION being logical signals "0", the gate "ÑOR" 506 generates a logic signal "1", which activates the first gate "NAND" 512. When activated, the first "NAN D" gate 512 passes the 4MHz clock signal to its output terminal. Simultaneously, in response to the GEMSTAR MODE signal being a "0" logic signal, the second "NAND" gate 514 is deactivated, which blocks the GEMSTAR CLOCK signal from the second "OR" gate 51 8, and in response to the SUBTITLE MODE signal which is a logic signal "0", the third gate "NAN D" 516 is deactivated, which blocks the R signal from the second gate "OR" 518 The second "OR" gate 518 passes the 4 MHz signal to its output terminal, which, in turn, is coupled to the clock input terminal of the shift register 204. Therefore, at the beginning of the portion active of the specified horizontal line, the displacement clock is a 4 MHz signal. If a caption box or Gemstar code on the specified horizontal line is not detected, the displacement clock signal control circuits of the Figure 6 remain in this state until the end of the portion active line. At the end of the active portion of the line, the LINE signal is made a logical signal "0" and the inverted AI line signal is made a logical signal "1". The logic signal "0" of LINE EA puts the counter 508 in the state of restart, as mentioned above. The logic signal "0" of LINE conditions the "OR" gate 506 to produce a logic signal "0" at its output terminal, which deactivates the first "NAND" gate 512, blocking the 4 MHz signal from the second gate "OR" 518 and the clock input terminal of the shift register 204. When a Gemstar frame code is detected, the signal of GEMSTAR MODE becomes a logical signal "1", as described above and illustrated in Figures 4 and 5. In response to a logic signal "1" of GEMSTAR MODE, the "ÑOR" 506 gate generates a logic signal "0" at its output terminal, deactivating the first gate "NAND" 512, and blocking the 4 MHz signal from the second gate "OR" 518. Simultaneously, the signal logic "1" of MODE DE GEMSTAR activates the second gate "NAND" 514, which passes the GEMSTAR CLOCK signal from the counter 508 to the second gate "OR" 518, and to the clock input terminal of the shift register 204. The resulting waveform is illustrated in Figure 1 as the waveform of GEMSTAR SAMPLE CLOCK. If a caption box code is detected, the SUBTITLE MODE signal becomes a logic signal "1". In response to a logic signal "1" of SUBTITLE MODE, the gate "ÑOR" 506 generates a logic signal "0" at its output terminal, deactivating the first gate "NAND" 512, and blocking the signal of 4. MHz of the second gate "OR" 518. Simultaneously, the logic signal "1" of SUBTITLE MODE activates the third gate "NA ND" 516, which passes the SUBTITULATION CLOCK signal of the counter 508 to the second gate " OR "51 8, and to the clock input terminal of the shift register 204. The resulting waveform is illustrated in Figure 1 as the waveform of MU CLOCK ESTRA SUBTITULATION. To adjust the phase of the shift register clock 204 to the center of the data bit periods, the counter 508 is reset when any of the signals GEMSTAR MODE or 0 MODE OF ITS BTITU LATION are converted into a logic signal "1" At the beginning of each horizontal line, the signals GEMSTAR MODE or LATIN BATTERY MODE are logical signals "0". This causes the third "OR" gate 520 to produce a "0" logic signal. This logical signal "0" is applied to the fourth gate "NAND" S 522, deactivating the gate "NAN D" 522, which generates a logic signal "1" of R EI N ICIO COUNTER. At the same time, the logic signal "0" in the output terminal of the third gate "OR" 520 is measured in time through the multivibrator D 510 in each clock cycle of 4 MHz to the output terminal Q. logic signal "0" in the output terminal Q of the multivibrator 510 is inverted by the second inverter 524 which provides a logic signal "1" input to the fourth gate "NAN D" (deactivated) 522. The logic signal "1" of R EI N IC IO OF CONTA DOR of the fourth gate "NAN D" 522 is provided to the first gate "OR" 502. In response to this logic signal "1", the first gate "OR" 502 provides a logic signal "0" to the reset input terminal R to the counter 508. In response to a reset logic "0" signal, the 508 counter operates normally, when any of the signals GEMSTAR MODE or MODE OF YOUR BTITU LATION becomes a logic signal "1", the third gate "OR" 520 produces a logical signal "1" at its output terminal. This signal activates the fourth gate "NANO" 522. The fourth gate "NAND" activated 522 produces a signal of logic "0" at its output terminal as the signal REI N IC IO COUNTER in response to the logic signal " 1"of the second inverter 524. The logic signal" 0"of COUNTER REINSTATEMENT conditions the first" OR "gate 502 to provide a logic signal" 1"to the reset input terminal R of the counter 508, which enter the restart state. In the next clock cycle of 4 MHz, the logic signal "1" of the third gate "OR" 520 is retained via the multivibrator D 51 0, and appears at its output terminal Q. This logic signal "1"is inverted by the second inverter 524, which provides a logic signal" 0"to the fourth gate" NAN D "522, deactivating the fourth gate" NAND "again. Therefore, the fourth gate "NA ND" 522, produces a logic signal "1" of new, conditioning the first gate!, OR "502 to produce a logic signal" 0"and allows the counter 508 to operate normally again, but from a known zero state.

Consequently, the counter will produce the GEMSTAR CLOCK and CLOCKWISE CLOCK signals with sampling times (ie, leading edges) suitably aligned with half of the respective subtitle and Gemstar data bits. Although the illustrated modality is described for data of Gemstar and subtitling, those skilled in the art will understand that the present invention can be used in any data transmission system in which a frame code can be used to identify the format of the following auxiliary digital data.

Claims (10)

1. CLAIMS 1. In a television receiver, an auxiliary digital data extractor comprising:. { a composite video signal source including an auxiliary digital data component comprising one of: a) a first frame code having a predetermined number of auxiliary bits and data in a first format, and b) a second frame code having the predetermined number of auxiliary bits and data in a second format; characterized by a frame code detector, coupled to the source of the composite video signal, and responding to a first suitable sub-frame of the predetermined number of frame code bits for detecting the first frame code and responding to a second suitable subseries of the predetermined number of bits of the frame code to detect the second frame code; an auxiliary data utilization circuit, coupled to the composite video signal source and the frame code detector, for selectively receiving auxiliary data in the first format in response to detection of the first frame code and in the second format in response to the detection of the second frame code. The receiver of claim 1, further characterized by: a separator, coupled to the source of the composite video signal, to generate a digital bitstream representing the composite video signal; a register, coupled to the separator, which responds to a clock signal, and which has an output terminal that generates the predetermined number of bits, to store samples of the digital bitstream of the separator; and a record controller, coupled to the frame code detector, and having an output terminal that produces the clock signal for recording, to condition the record to sample the digital bitstream at a first rate when saving samples of digital bit stream representing a frame code, at a second rate when storing samples representing auxiliary data in the second format, wherein: the frame code detector is coupled to the register, and responds to a first bit subset of the registration output terminal, which corresponds to the first sub-frame of frame code bits to detect the first frame code, and which responds to a second sub-series of bits of the output terminal of the register, which correspond to the sec a subset of frame code bits, to detect the second frame code. 3. The receiver of claim 2, further characterized in that: the controller reg i stro comprises circuits to generate a clock signal of reg i stro for the region at the first speed so that the reg The signal is conditioned to over-sample the composite signal representing the signal of the separator when it stores samples of the digital bit stream representing the frame code; and the frame code detector additionally comprises circuits for detecting one of the first and second frame code s only when the one of the first and second frame code is detected by two consecutive digital bitstream samples. The receiver of claim 2, further characterized in that the frame code detector comprises: or a first combinatorial logic circuit, coupled to the first bit sub-frame of the output terminal of the register, to generate a signal when the signals in the first subseries of the output terminals of the register correspond to the first frame code; and a second combinatorial logic circuit, coupled to the second bit sub-frame of the register output terminal, for generating a signal when the signals in the second sub-series of the output terminals of the register correspond to the second frame code. The receiver of claim 1 further characterized by: a separator, coupled to the source of the composite video signal, to generate a digital bitstream representing the composite video signal; a register, coupled to the separator, which responds to a clock signal, and which has an output terminal that generates less than the predetermined number of bits, to store samples of the digital bitstream of the separator; and a record controller, coupled to the frame code detector, and having an output terminal that produces the clock signal for the record, to condition the record to sample the digital bitstream at a first rate when saving samples of digital bit streams representing a frame code, at a second rate when storing samples representing auxiliary data in the second format, where: 0 the frame code detector is coupled to the register, and responds to a first subseries of bits of the register output terminal, which corresponds to the first sub-series of frame code bits to detect the first frame code, and which corresponds to a second sub-series of bits of the output terminal of the register, which correspond to the second subset of frame code bits, to detect the second frame code. The receiver of claim 5, further characterized in that: the registration controller comprises circuits for generating a record clock signal for recording at the first rate so that the record is conditioned to oversample the composite video signal representative of the signal of the separator when storing samples of the digital bit stream representing the frame code; and the frame code detector additionally comprises circuits for detecting one of the first and second frame code only when the one of the first and second frame code is detected by two consecutive digital bitstream samples. The receiver of claim 5, further characterized in that the frame code detector comprises: a first combinatorial logic circuit, coupled to the first bit sub-frame of the output terminal of the register, for generating a signal when the signals in the first subseries of the output terminals of the register correspond to the first frame code; and a second combinatorial logic circuit, coupled to the second bit sub-frame of the register output terminal, for generating a signal when the signals in the second sub-series of the output terminals of the register correspond to the second frame code. The receiver of claim 1, further characterized in that the first and second suitable sub-series are suitable substrings different from the predetermined number of frame code bits. The receiver of claim 1, further characterized in that the frame code detector operates in a first mode of operation to detect any occurrence of auxiliary information in the composite video signal and, responds to detect any occurrence of auxiliary information during the first mode of operation, operates in a second mode of operation to detect a particular occurrence of auxiliary information in the composite video signal. The receiver of claim 9, further characterized in that the frame code detector during the first mode of operation responds to all of the predetermined number of frame code bits to detect any occurrence of auxiliary information in the composite video signal , and the frame code detector during the second mode of operation responds to the first suitable sub-series or the second adequate sub-series of the predetermined number of frame code bits to detect the particular occurrence of auxiliary information in the composite video signal. RESU MEN An auxiliary digital data extractor in a television receiver includes a source of a composite video signal. The composite video signal includes an auxiliary digital data component that is either a first frame code having a predetermined number of auxiliary bits and data in a first format, or a second frame code having the same number of frames. bits and auxiliary data in a second format. A frame code detector is coupled to the source of the composite video signal. The frame code detector responds to a subset of the frame code bits to detect the first frame code and a different subset of frame code bits to detect the second frame code. An auxiliary data utilization circuit is coupled to the source of the composite video signal and the frame code detector. The auxiliary data utilization circuit receives auxiliary data in either the first format when the first frame code is detected or, in the second format when the second frame code is detected.