JP2829809B2 - Digital audio signal measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio signal measuring device for measuring various characteristics of a digital audio signal.

[0002]

2. Description of the Related Art In recent years, digitalization and broadcasting of audio equipment such as CDs (Compact Discs) and DATs (Digital Audio Tapes) in the consumer market have been conducted.
With the spread of digital audio equipment in studios, standards (digital audio interface standards) for connecting these digital audio equipment have been established. Standards are established by regional or international standards organizations, but in Japan E
Established in July 1987 as CP-340 by the IAJ (Japan Electronic Opportunities Manufacturers Association).

As shown in FIG. 7, the format of a digital audio signal defined by CP-340 is such that one block includes 192 frames, one frame is composed of two subframes, and each subframe has , Bits 0 to 3 for synchronous preamble, bit 4
To bit 27, audio sample data are arranged from bit 28 to bit 30, V, U, and C bits are arranged from bit 28 to bit 30, and a parity bit is arranged to bit 31. Note that bits 4 to 31 are modulated by a biphase mark system in order to provide an interface irrelevant to clock reproduction and connectivity from the suppressed data of the DC component of the transmission line.

A V bit (validity bit) indicates the validity of audio sample data, and a U bit (user bit) is for transmitting information individually defined by a medium (CD, DAT, etc.). The information block length and the meaning of each bit are determined for each medium. The C bit (channel status bit) indicates the nature and source of information in the data portion such as the word length of audio sample data / presence / absence of pre-emphasis / sampling frequency. One information block is composed of 192 bits. Configure. The P bit (parity bit) is a bit for detecting a transmission error or a device failure. The P bit is set so that the number of logical “1” s of bit values from bit 4 to bit 31 is even. Add.

A digital audio signal measuring instrument has an input terminal defined by such a digital audio interface standard.
This device measures various characteristics of audio signals.

FIG. 8 shows the configuration of a conventional digital audio signal measuring device, in which a CPU 801 and a ROM which constitute a general microcomputer basic system.
802, RAM 803, display circuit 804, display device 80
5, input device (keyboard or mouse) 806, storage device 807 for writing / reading measurement conditions and measurement result data, and CPU bus 8 connecting these
18, an input physical audio level conversion circuit 811 for converting an input digital audio signal 817 into a signal level (usually TTL level) inside the device and sending it out as an input channel coding signal 816, and demodulating the input channel coding signal 816 , Various timing signals 815 are generated and supplied to other blocks, and the reception audio sample data 812 and the reception C bit data 81
3 and the reception U-bit data 814, which are supplied to the audio sample analysis circuit 808 and the C-bit and U-bit capture circuit 809, respectively, and the reception audio sample data 812 under the control of the CPU 801. The audio sample analysis circuit 808 for measuring various characteristics and the reception C bit data 813 and the reception U bit data 814
1 and a C-bit and U-bit capturing circuit 809 for capturing the data.

Next, the operation of the above conventional example will be described. In FIG. 8, an input digital audio signal 817 of a predetermined electrical level or optical level input from a digital audio interface is converted into a signal level inside the device by an input physical level conversion circuit 811 and an input channel coding signal is output. 816 is input to the reception separation circuit 810.

[0008] In the receiving / separating circuit 810, audio sample data and V, U, C, and P bits are time-division multiplexed, and the input channel is subjected to biphase mark modulation.
The coding signal 816 is demodulated, and various timing signals 815 necessary for processing of other blocks, for example, as shown in FIG.
Generate bit timing, etc.
The sample data is separated from the C bit and the U bit, and the received audio sample data 8
12, input to the audio sample analysis circuit 808 and the C bit and U bit capture circuit 809 as received C bit data 813 and received U bit data 814.

[0009] The audio sample analysis circuit 808 comprises:
It has a function of measuring various characteristics such as a voltage value / distortion factor / frequency / voltage ratio between channels of the received audio sample data 812 which is a quantized audio signal, and is controlled by the CPU 801 in accordance with an instruction of an operator. Works. The measurement result is processed by the CPU 801 and the display device 80
5 is displayed. At that time, the measurement result can be stored in the storage device 807 according to an instruction of the operator.

C-bit and U-bit fetch circuit 80
The CPU 9 converts the reception C bit data 813 and the reception U bit data 814 separated by the reception separation circuit 810 into CPU
It has a function of recording in a RAM or the like in a format that can be processed by 801. The captured C-bit and U-bit data are processed by the CPU 801 and displayed on the display device 805 in a binary number format. At that time, the measurement result can be stored in the storage device 807 according to an instruction of the operator.

[0011]

However, in the above-mentioned conventional apparatus, the observer of the C bit or the U bit performs the operation by monitoring the result displayed on the display device by the operator (user). Alternatively, it has been difficult to reliably detect an abnormal state in which a specific bit value changes momentarily due to a transmission failure or a software bug. In addition to confirming the condition where a specific bit pattern occurs temporarily, not only abnormalities, even when testing the normality of equipment, if the bit value change rate exceeds the range that can be recognized by humans, it can be reliably captured I couldn't do that. Furthermore, when a specific pattern is detected in a specific field, it is not possible to capture the information of the other fields or the contents of the entire information block, and much time and effort is required to analyze the failure and confirm the operation during development. Was spending.

SUMMARY OF THE INVENTION The present invention solves such a conventional problem, and is an excellent digital signal capable of easily and quickly detecting a specific pattern of C bits or U bits and displaying a corresponding information block at the time of detection. It is an object of the present invention to provide an audio signal measuring device.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention comprises, in a conventional configuration, a C bit and a U bit for comparing a received C bit or a U bit with a specific pattern.
It has a bit comparison circuit.

The present invention further comprises means for synchronizing the C-bit and U-bit capture circuits with the C-bit and U-bit comparison circuits.

[0015]

According to the present invention, the C-bit and U-bit comparing circuits for comparing the received C-bit or U-bit with a specific pattern are provided, so that the specific pattern of the C-bit or U-bit can be reliably detected. .

The present invention also includes a synchronizing means for synchronizing the C-bit and U-bit fetch circuits with the C-bit and U-bit comparison circuits, so that the corresponding information block is detected when a specific C-bit or U-bit pattern is detected. be able to.

Therefore, according to the present invention, it is possible to easily and quickly analyze a failure and check the operation of the apparatus.

[0018]

FIG. 1 shows the configuration of a digital audio signal measuring apparatus according to an embodiment of the present invention. 1, reference numeral 101 denotes a CPU constituting a general microcomputer basic system, 102 denotes a ROM, 103 denotes a RAM, 104 denotes a display circuit, 105 denotes a display device, and 106 denotes a display device.
Is an input device (keyboard or mouse), 107 is a storage device for writing / reading measurement conditions and measurement result data, and these are connected by the CPU bus 121. An audio sample analysis circuit 108 measures various characteristics of the received audio sample data 115 under the control of the CPU 110.
Reference numeral 9 denotes a C which captures the reception C bit data 116 and the reception U bit data 117 so that the CPU 801 can process them.
A bit and U bit fetch circuit. Numeral 110 compares a specific pattern specified by the operator to be detected with the value of the received C-bit data 116 or U-bit data 117, and when a pattern match is detected, a pattern match detection interrupt signal 113 to the CPU 101 and a C bit And the synchronization signal 1 to be input to the U-bit input circuit 109
14 is a C-bit and U-bit comparison circuit. 111 demodulates the input channel coding signal 119, generates and supplies various timing signals 118 to other blocks, and separates the received audio sample data 115 from the received C bit data 116 and the received U bit data 117. , An audio sample analysis circuit 108, a C bit and U bit capture circuit 109, and a C bit and U bit comparison circuit 1 respectively.
10 is a reception separation circuit to be supplied to the receiver 10. Reference numeral 112 denotes an input physical level conversion circuit which converts the input digital audio signal 120 into a signal level (usually TTL level) inside the apparatus and sends it out as an input channel coding signal 119.

Next, the operation of the above embodiment will be described. In FIG. 1, an input digital audio signal 120 having a predetermined electrical level or optical level input from a digital audio interface is converted into a signal level inside the device by an input physical level conversion circuit 112, and an input channel coding signal is input. 119 is input to the reception separation circuit 111.

The receiving / separating circuit 111 demodulates the input channel coding signal 119 on which the audio sample data and V, U, C, P bits are time-division multiplexed and subjected to biphase mark modulation to process other blocks. , Various timing signals 118 (block start timing, frame timing, bit timing, etc.) required for the audio sample data section and the C bit and U bit are separated from each other to obtain the received audio sample data 115, The received C bit data 116 and the received U bit data 117 are output. The received audio sample data 115 is input to the audio sample analysis circuit 108, where the C bit data 116 and the received U
The bit data 117 includes a C-bit and U-bit capture circuit 110 and a C-bit and U-bit comparison circuit 110.
Entered as

The audio sample analysis circuit 108
It has a function of measuring various characteristics such as a voltage value / distortion rate / frequency / voltage ratio between channels in the received audio sample data 115 which is a quantized audio signal. Works. The measurement result is processed by the CPU 101 and the display device 105
Will be displayed. At this time, the measurement result can be stored in the storage device 107 according to an instruction of the operator.

C-bit and U-bit capturing circuit 10
The CPU 9 converts the reception C bit data 116 and the reception U bit data 117 separated by the reception separation circuit 111 into the CPU 1.
It has a function of recording in a RAM or the like in a format that can be processed by the program No. 01. The captured C-bit data 116 and U
The bit data 117 is processed by the CPU 101 and displayed on the display device 105 in a binary or hexadecimal format. At this time, the measurement result is stored in the storage device 107 according to an instruction from the operator.
Can be saved.

C-bit and U-bit comparison circuit 110
Compares the specific pattern to be detected input from the input device by the operator with the bit pattern of the received C-bit data 116 or U-bit data 117, and if a pattern match is detected, a pattern match detection interrupt signal to the CPU 101 113 and a fetch synchronization signal 114 to the C-bit and U-bit fetch circuit 109 are generated.

FIG. 2 shows an example of a display screen used for setting a detection pattern. In this example, the detection target is C
This is an example in which a bit is selected. In the detection target column 201, C
It is set whether a bit is to be subjected to pattern detection or a U bit is to be subjected to pattern detection. In the case of C bits, the same value is basically transmitted to channel 1 and channel 2. However, either one channel or both channels can be selected. The bit position display column 202 displays the bit positions of the pattern data and the bit mask. In the pattern data setting column 203, a bit pattern to be compared is set. In the case of C bits, since one information block is composed of 192 bits (24 bytes), there is a pattern setting column for 24 bytes. In the bit mask setting column 204, whether or not the bit is to be compared is set in bit units. When the value of the bit mask data is logic “0”, the bit is not treated as a comparison target. By doing so, pattern comparison can be performed on a bit-by-bit basis.

FIG. 3 shows the configuration of the C bit and U bit comparison circuit 110 in the above embodiment. In FIG. 3, reference numeral 301 denotes a comparison data storage RAM when a comparison operation is performed.
This is a comparison address generation circuit for generating a comparison address 309 with respect to the block 303.
07, the address is incremented by one address at the address count timing 308. 302 is a comparison data storage RAM address line 31
An address switching circuit for switching whether to connect the CPU address bus 305 or the comparison address line 309 to 0. A comparison data storage RAM 303 stores comparison data. 304 is a comparison data storage RAM
This is a data switching circuit that switches between connecting the data line 311 to the CPU data bus 306 or the comparison data output bus 319. A CPU address bus 305 is connected to the comparison data storage RAM address line 310 when writing comparison data to the comparison data storage RAM 303. 306 is a CPU data bus,
When writing comparison data to the comparison data storage RAM 303, it is connected to the comparison data storage RAM data line 311. 307 is an information block (C bit or U bit)
Block start timing indicating the start timing of
Reference numeral 8 denotes an address count timing for counting up a comparison address, reference numeral 309 denotes a comparison address line indicating an address generated by the comparison address generation circuit, reference numeral 310 denotes a comparison data storage RAM address line, and reference numeral 311 denotes a comparison data storage RAM data line. Reference numeral 312 denotes a mask data line, which is connected to bit 1 of the comparison data output bus 319. A comparison data line 313 is connected to bit 0 of the comparison data output bus 319. 314 is reception C bit data or reception U bit data to be compared. 315 is a bit comparison timing indicating a comparison timing of one bit. 31
Reference numeral 6 denotes a comparison result state signal indicating the state of the comparison result up to that time (whether or not a mismatch has occurred so far). 31
Reference numeral 7 denotes a block comparison result timing indicating the timing for determining the comparison result of one information block. Reference numeral 318 denotes a signal indicating a comparison result of one information block, and is a block comparison result output for outputting a positive logic pulse when they match. Reference numeral 319 denotes a comparison data output bus connected to the comparison data storage RAM data bus when the comparison operation is performed.

Next, the operation of the C-bit and U-bit comparison circuit 110 will be described. When performing the comparison operation, the comparison data storage RAM 303 is stored in advance in FIG.
The pattern data and the bit mask data input by the operator are written on the screen used for setting the detection pattern shown in FIG.

FIG. 4 shows an example of the data arrangement in the comparison data storage RAM 303, which shows a case where C-bit channels 1 and 2 are targeted. Data is arranged so that one subframe corresponds to one address.

After the comparison data and the mask data are written into the comparison data storage RAM 303, the connection is switched to the B side in the address switching circuit 302 and the data switching circuit 304, so that the comparison operation becomes valid.

FIG. 5 shows an example of the operation timing of the C-bit and U-bit comparison circuit 110. The address corresponding to the received sub-frame is output from the comparison address generation circuit 301, and the comparison data 313 and the mask data 312 are output from the comparison data storage RAM 303 accordingly. The received C bit data 314 is compared with the comparison data 313 by the gate 1 (Ex-OR), and if they do not match, the output of the gate 1 goes to the “H” level. Gate 2
The (AND) output is "L" (matched) regardless of the output value of the gate 1 if the value of the mask data corresponding to the bit is "0". If the mask data is "1", the output is the gate. When the output of 1 is "H" (mismatch), a positive logic pulse (indicating that a mismatch has occurred) is generated at the bit comparison timing 315. The FF1 holds that a mismatch has occurred within one information block period, and the comparison result of one information block is output from the gate 3 at the timing of the block comparison result timing 317 after the end of comparison of the last bit of one information block. Output as the block comparison result output 318.

The block comparison result 318 is stored in the CPU of FIG.
A pattern match detection interrupt signal 113 is connected to the interrupt line of the bus 121 to notify the CPU 101 of the occurrence of the pattern match, and the operator is notified of the occurrence of the pattern match by a method such as displaying this information on a screen by processing the software. Notice.

Further, the block comparison result 318 is input to the C-bit and U-bit fetching circuit 109 as a fetch synchronization signal 114 to the C-bit and U-bit fetching circuit 109, and the synchronization signal fetches the C-bit or U-bit. Is stopped, the information block itself that has detected the specific pattern specified by the operator can be reliably captured.

FIG. 6 shows an example of the storage contents of the C-bit and U-bit fetch circuit 109 in the above embodiment. One subframe (1
Bit) C bit or U bit information, a block head status indicating that the subframe is the head subframe of the information block, and a capture end status indicating that the capture operation has been completed in the subframe. . A commercially available RAM is used as the storage buffer, and the address is sequentially counted up, and the data is cyclically stored. The CPU 101 that has recognized that a pattern match has occurred by the pattern match detection interrupt signal 113 has already
In step 4, the C-bit whose capture operation is stopped and the bit of the capture end status of the storage buffer of the U-bit capture circuit 109 are searched to know the capture end address. The C-bit or U-bit information stored at this address is the last bit information of the information block in which the specific pattern has been detected. Next, the bit of the block head status is detected by tracing the address from the capture end address. The C bit or U bit information stored at the address where the block head status is detected for the first time is the head bit information of the information block where the specific pattern is detected. Thus, the information block in which the pattern is detected can be captured.

The C-bit and U-bit comparison circuit 110 of the above-described embodiment uses the reception C-bit data 116
The bit data 117 is configured to be compared in series one bit at a time. Compared with the case of comparing in parallel, the number of components used is small and the circuit is simple. Also, the comparison data storage R
A commercially available inexpensive RAM can be used for the AM 303, and the capacity can be easily increased.

If the block comparison result 318 is output to the outside, it can be used as a trigger signal at the time of pattern detection.

In the above embodiment, the C bit and the U
A signal indicating that a pattern match has been detected is input to the bit capture circuit 109 as the capture synchronization signal 114. Means for detecting parity error, loss of reception synchronization, V bit status, channel status CRC error, etc. By providing the detection result and inputting it as the synchronization signal 114, it is possible to capture C-bit or U-bit information synchronized with the detection of these states.

In the above embodiment, the C bit or U bit
Although a match of a specific pattern of bits is detected, by inverting the logic of the block comparison result timing,
It is also possible to detect a mismatch between the C bit or the U bit and a specific pattern. In this case, an abnormal state temporarily occurring due to a transmission failure on the interface, a failure of the device, a bug, or the like can be easily and reliably grasped.

[0037]

As is apparent from the above embodiment, the present invention includes the C-bit and U-bit comparison circuits, so that the specific pattern of the C-bit or U-bit can be reliably detected.

The present invention also includes a synchronizing means for synchronizing the C-bit and U-bit capture circuits with the C-bit and U-bit comparison circuits, so that the corresponding information block when a specific C-bit or U-bit pattern is detected is captured. be able to.

Therefore, according to the present invention, it is possible to easily and quickly analyze a failure and check the operation of the apparatus.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a digital audio signal measuring device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a screen used for setting a detection pattern in the apparatus.

FIG. 3 is a schematic block diagram showing a configuration of a C-bit and U-bit comparison circuit in the device.

FIG. 4 is a schematic diagram showing a data arrangement column of a comparison data storage RAM in the same device.

FIG. 5 is a timing chart showing the operation of a C-bit and U-bit comparison circuit in the device.

FIG. 6 is a schematic diagram showing an example of storage contents of a C-bit and U-bit fetch RAM in the device.

FIG. 7 is a data structure diagram showing a format of a digital audio signal.

FIG. 8 is a schematic block diagram showing a configuration of a conventional digital audio signal measuring device.

FIG. 9 is a timing chart showing the operation of the reception separation circuit in the device.

[Explanation of symbols]

 101 CPU 102 ROM 103 RAM 104 Display circuit 105 Display device 106 Input device 107 Storage device 108 Audio sample analysis circuit 109 C bit and U bit capture circuit 110 C bit and U bit comparison circuit 112 Input physical level conversion circuit 113 Pattern match detection Interrupt signal 114 Capture synchronization signal 115 Receive audio sample data 116 Receive C bit data 117 Receive U bit data 118 Various timing signals 119 Input channel coding signal 120 Input digital audio signal 121 CPU bus 201 Detection symmetry column 202 Bit position display 203 Pattern data setting field 204 Bit mask setting field 301 Comparison address generation circuit 302 Address switching circuit 303 Comparison Data storage RAM 304 Data switching circuit 305 CPU address bus 306 CPU data bus 307 Block start timing 308 Address count timing 309 Comparison address line 310 Comparison data storage RAM address line 311 Comparison data storage RAN data line 312 Mask data line 313 Comparison data line 314 Received C bit data / received U bit data 315 Bit comparison timing 316 Comparison result status signal 317 Block comparison result timing 318 Block comparison result output 319 Comparison data output bus

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-88175 (JP, A) JP-A-62-6180 (JP, A) JP-A-51-67122 (JP, A) JP-A 59-88 38914 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11B 20/18 G01R 31/00

Claims (2)

(57) [Claims] A receiving / separating circuit for receiving / demodulating / separating an audio input signal; and an audio / separating circuit for analyzing received audio sample data separated by the receiving / separating circuit.
A sample analysis circuit, a C-bit and U-bit capturing circuit for capturing the received C bit and the received U bit separated by the reception separating circuit, and a C bit pattern data or a U bit pattern data set in advance by the receiving separating circuit; Received C bit or received U separated
A digital audio signal measuring device comprising a C-bit and U-bit comparing circuit for sequentially comparing bits to detect a pattern match. 2. A receiving / separating circuit for receiving / demodulating / separating an audio input signal, and an audio / separating circuit for analyzing received audio sample data separated by the receiving / separating circuit.
C-bit and U-bit comparison for detecting a pattern match by sequentially comparing a sample analysis circuit with a predetermined C-bit pattern data or U-bit pattern data with a reception C bit or a reception U bit separated by the reception separation circuit And a C-bit and U-bit capturing circuit for periodically capturing a received C bit and a received U bit separated by the reception separating circuit, and stopping the capturing by a pattern match detection signal from the C bit and U bit comparing circuit A digital audio signal measuring device comprising: