SU1478349A1 - Circuit for measuring confidence of data transmission over discrete communication channel - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of the detection of phase faults. The device contains rg 1 clock pulses, a sensor 2 test signals, a clock synchronization unit 3, sensors 4 and 10 reference signals, a cycle phasing unit 5 and 11, a comparison unit 6, an error counter 7, a display unit 8, a phase error counter 9, analyzer 12 cyclic desynchronization and monitored discrete communication channel 13. The goal is achieved by providing additional analysis in the device, as a result of which only actual events, including during breaks and "fading", phase faults are recorded and the breaks themselves and "fading" are not recorded as phase faults. The apparatus of claim 2, is characterized by the execution of an analyzer 12, consisting of a trigger, a counter, and two coincidence elements. 1 hp f-ly, 1 ill.

Description

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The invention relates to telecommunications and can be used to configure and test digital information transmission equipment, as well as to monitor the state of such equipment and discrete channels during their operation.

The purpose of the invention is to increase the reliability of the detection of phase faults.

The drawing shows a structural electrical circuit of the proposed device.

A device for measuring the reliability of information transmission over a discrete communication channel comprises a clock pulse generator 1, a sensor 2 test signals, a clock synchronization unit 3, a sensor 4 reference signals, a cycle phasing unit 5, a comparison unit 6, an error counter 7, a display unit 8 , phase failure counter 9, additional sensor 10 reference signals, additional cyclic phase 11, analyzer 12 cyclic pa-synchronization, including the first element 12.1 of the match, trigger 12.2, the second element 12.3 of the match and a counter 12.4, a monitored discrete communication channel 13.

The device works as follows.

From sensor 2 to the monitored discrete channel 13 (or the input of the digital equipment of the digital channeling device) receives a sequence of binary pulses, which then goes simultaneously to the second input of the block 3 of the clock synchronization, the second inputs of both blocks 5 and 11 of the cycle phasing and on the first input of block 6 comparison. The clock synchronization unit 3 provides the frequency and phase adjustment of the clock pulses from the clock pulse generator 1, along the leading edges of the binary pulses received from the discrete channel 13 being monitored. After the clock adjustment, the clock pulses go to the first sensor inputs 4 and 10. Sensor 4 produces the same reference sequence of binary pulses as sensor 2. The reference sequence from sensor 4 is fed to the second input of the comparison unit 6, in which it is compared element by element with the sequence Stu pulses received from

monitored discrete channel 13. If the sequence elements do not match, error pulses appear at the output of the comparison block 6, which are recorded by the error counter 7.

Phasing according to the cycle of sensor 4 is carried out according to the control signals received from cycle cycling unit 5. The cyclic phasing unit 5, after correct recording of information from the monitored discrete channel 13 into it, closes it via sensor 4, causes it to work autonomously. The cycle phasing of the additional sensor 10 is effected by the control signals received at its second input from the output of the analyzer 12.

When the second and third inputs of the analyzer 12 (respectively, the first and second inputs of the first element match 12.1) of the No Phase signals are received from the cyclic phasing blocks 11 and 5, the No Phase signal (1) is written to the trigger 12.2. If, in reality, there was no phase failure in the monitored discrete channel 13, but there was, for example, a short break, then after restoring the monitored discrete channel 13 both sensors 4 and 10 will work in phase with sensor 4 "Signal Phase transmitted from the output of the additional 11th cyclic unit phasing to the first input of the analyzer 12 (the first inputs of the trigger 12.2 and the counter 12.4), the signal registered in the trigger 12.2 is erased No phase. If during this interruption the phase failed, then after restoring the monitored discrete channel 13, the sensor 4 is automatically terminated (according to the control signals from the cyclic phasing unit 5), and the No phase signal in the trigger 12.2 will remain. In this case, the second element 12.3 matches signals from the No phase from trigger 12.2, the Phase from the cyclic phasing unit 5, and the clock signals from the 1 clock pulse generator. The clock pulses through the second 12.3 coincidence element are sent to the second input of the counter 12.4, which, after a predetermined time has passed (2-3 times longer than the analysis time in blocks 5 and 11), generates a Phase failure signal on

the second input of the additional sensor 10 and the input of the counter 9 failures. The Phase Failure signal is recorded in the fault counter 9 and provides cyclic phasing of the additional sensor 10. After the cyclic synchronization of both sensors 4 and 10 is established, the No Phase signal in the analyzer 12 is erased.

Thus, as a result of additional analysis, only actual events, including during breaks and fading, phase faults are recorded in the device and the breaks and fades themselves are not recorded as phase faults.

Claims (2)

1. A device for measuring the reliability of information transmission over a discrete communication channel, comprising a sensor of test signals, a counter 0 five 0 The additional sensor of the reference signals, the additional cyclic phasing unit and the cyclic desynchronization analyzer are serially connected, the first input of the additional sensor of the reference signals is connected to the output of the clock synchronization unit, the second input of which is connected to the second input of the additional cyclic phasing unit, the second output of which is connected to the second input analyzer ra cyclic desynchronization, the third, fourth and fifth inputs and output of which are connected respectively with the first and the second outputs of the cyclic phasing unit, with the output of the clock pulse generator and with the input of the phase faults counter connected to the second and inverse inputs of the additional sensor of the reference signals, the second output of the cyclic phasing unit is connected to the third input of the sensor errors, phase failure counter, block from-25 reference signals, and block output Brazher and clock generator, the output of which through the sensor of test signals is connected to the input of the monitored discrete communication channel, the output of which is connected to the first input of the comparison unit, and series-connected clock synchronization unit, the first input of which is connected to the output of the clock generator, the reference sensor signals and a cyclic phasing unit, the first output of which is connected to the second sensor input of the reference signals, the output of which is connected to the second input of the comparator unit, the first input of which is connected thirty 35 40 Comparisons via the error counter are connected to the first input of the display unit, the second input of which is connected to the output of the phase fault counter. 2. The device according to claim 1, characterized in that the frame desynchronization analyzer is configured as a first element of the match, a trigger, a second element of the match, and a counter, the output of which is the output of the cycle desynchronization analyzer, first, second, third, fourth and the fifth inputs, respectively, are the trigger reset input, connected to the counter reset input, the first and second inputs of the first match element, and the second and third inputs of the second match element. with the second inputs of the clock synchronization unit and the cycle phasing unit, characterized in that, in order to increase the reliability of detecting phase faults, 45 reference signals and block output the comparison through the error counter is connected to the first input of the display unit, the second input of which is connected to the output of the phase failure counter. 2. A device according to claim 1, characterized in that the frame desynchronization analyzer is made in the form of serially connected first coincidence element, trigger, second coincidence element and counter, the output of which is the output of the cycle desynchronization analyzer, first, second, third, fourth and n The inputs of which are, respectively, the trigger reset input connected to the counter reset input, the first and second inputs of the first match element, and the second and third inputs of the second match element.