JPH06139159A - Small computer system - Google Patents

Abstract

PURPOSE:To attain rapid operation and to prevent the power OFF of a self- system from exerting bad influence upon the signal transmission/reception of other devices. CONSTITUTION:An output circuit 13 in a small computer device 10 includes an N-channel type 1st transistor(TR) Q1 connecting its source electrode to a ground potential point, connecting its drain electrode to an interface bus 20 and receiving the 1st signal to its gate electrode, a P-channel type 2nd TR Q2 connecting its drain electrode to the bus 20 and receiving the 2nd signal making a pair with the 1st signal to its gate electrode and an N-channel type 3rd TR Q3 connecting its source electrode to the source of the TR Q2 and connecting its drain and gate electrodes to power supply potential point (VDD 2).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a small computer
The present invention relates to a system, and more particularly to a small computer system that transfers data between a plurality of small computer devices via an unbalanced interface bus.

[0002]

2. Description of the Related Art A conventional small computer to which an unbalanced small computer system interface (hereinafter referred to as SCSI), which is a general-purpose input / output interface for small and medium computer systems standardized by American National Standards Institute (ANSI), is applied. A first example of a computer system is shown in FIG.

In this example, the power supply potential point (VDD1 = 5V)
, 220Ω first resistance elements R1 and R3, and 330Ω second resistance elements R2 and R4 connected to the ground potential point, an interface bus 20, an internal circuit 12b, and an interface, respectively. An interface provided with at least one (both in this example) of the input circuit 11 and the output circuit 13b connected to the bus 20.
An output circuit 13b having a plurality of small computer devices 10b for exchanging data via the bus 20.
Is a circuit including a source electrode connected to a ground potential point, a drain electrode connected to the interface bus 20, and a gate electrode including an N-channel type transistor Q1 for receiving the data DT from the internal circuit 12b. The connection of the plurality of small computer devices 10b with the interface bus 20 is controlled by the daisy chain method.

Next, the operation of the output circuit 13b of this example will be described. FIG. 7 is a signal waveform diagram of the interface bus 20 by the output circuit 13b.

By the data DT from the internal circuit 12b,
The interface bus 20 is at a low level when the transistor Q1 is in the ON state, and when the transistor Q1 is changed to the OFF state at the timing of t1, the interface bus 20 is not driven by any small computer device 10b. Therefore, it changes to a high level. However, at this time, due to the influence of the capacitance components parasitic on the resistance elements R1 to R4 and the interface bus 20, it takes ΔT time to reach the voltage (2V) which the small computer system regards as a high level. I was sick.

FIG. 8 shows a second example of a conventional small computer system in which this drawback is improved.

The output circuit 13c of this example has an OR type logic which receives the data DT from the internal circuit 12 at the first input terminal and the inverted signal of the output enable signal E from the internal circuit 12 at the second input terminal. A gate G1, an AND type logic gate G2 that receives the data DT at a first input end and the output enable signal E at a second input end, and an inverter IV1 that forms an inverted signal of the output enable signal E,
The source electrode is connected to the ground potential point, the drain electrode is connected to the interface bus 20, and the gate electrode is the logic gate G.
N-channel type transistor Q for receiving the output data of 2
1 and a P-channel transistor Q2 having a source electrode connected to a power supply potential point (VDD2 = 5V), a drain electrode connected to the interface bus 20, and a gate electrode receiving the output data of the logic gate G1. Has become.

Next, the operation of the output circuit 13c of this example will be described. FIG. 9 is a signal waveform diagram of the interface bus 20 by the output circuit 13c.

When the output enable signal E is at high level,
The data DT passes through the logic gates G1 and G2 and is transmitted to the gate electrodes of the transistors Q1 and Q2.

When data DT is high, transistor Q1 is on, transistor Q2 is off, and interface bus 20 is low. Subsequently, when the data DT becomes high level at the timing of t1 and the transistor Q1 turns off and the transistor Q2 turns on, the interface bus 20 changes to co-level. At this time, the interface bus 20 is charged by the transistor Q2, and the time ΔT from the low level to the high level (2V) reaches the first level.
Is shorter than the example.

When the output enable signal Q is at a low level, both the transistors Q1 and Q2 are turned off, and the output circuit 13 is disconnected from the interface bus 20.

Here, it is assumed that the power supply of its own small computer device 10c is inadvertently cut off while transmitting and receiving data etc. between the other two small computer devices 10c. FIG. 10 shows a voltage waveform diagram of each part at this time. When the power supply of the small computer device 10c of itself is cut off at the timing of t6, the potential of the gate electrode of the transistor Q2 is gradually increased even when the interface bus 20 needs to be kept at a high level (Vb-A). The transistor Q2 is turned on because of the decrease in the voltage, and the interface bus 2
A current path is generated from the high-potential drain electrode side connected to 0 to the source electrode side where the potential drops, and V
There is a risk that the interface bus 20 changes to a low level like bb.

[0013]

In the first example of the conventional small computer system described above, the bus for charging up the interface bus 20 is the element resistance R.
Since there are only 1 and R3, it takes a long time for the interface bus 20 to reach the high level from the low level, and if the timing of the signal change is made fast, the low level pulse of the next progress will be generated before the high level is completely reached. Has arrived,
There is a risk of causing a malfunction and there is a problem that it is not suitable for high speed operation.

In the second example in which the transistor Q2 is added to solve this problem, the time required for the interface bus 20 to reach from the low level to the high level is shortened, which is suitable for high speed operation. , While the other small computer device 10c is executing transmission / reception of data etc.
When the power source of the device 10c is cut off, the transistor Q2 is turned on, which makes it impossible to maintain the high level of the interface bus 20.

An object of the present invention is to provide a small computer system which enables a high speed operation and which does not adversely affect the transmission and reception of signals between other small computer devices even when the power supply of the small computer device is cut off. To provide.

[0016]

In the small computer system of the present invention, first and second resistance elements having predetermined resistance values are connected between a power supply potential point and a ground potential point, respectively. A small computer system having an interface bus and a plurality of small computer devices each including at least one of an input circuit and an output circuit connected to the interface bus and exchanging data via the interface bus. In the output circuit of the small computer device, a source electrode is connected to the ground potential point, a drain electrode is connected to the interface bus, and a gate electrode receives a first signal. , Connecting the drain electrode to the interface bus and connecting the drain electrode to the gate electrode A second transistor of the opposite conductivity type that receives a second signal paired with the first signal; a source electrode connected to the source electrode of the second transistor; and a drain electrode and a gate electrode connected to the power supply potential point. It is configured as a circuit including a third transistor of one conductivity type.

In the output circuit of the small computer device, the drain electrode is connected to the interface bus and the first electrode of one conductivity type for receiving the first signal at the gate electrode and the drain electrode are connected to the interface bus.
A second transistor of opposite conductivity type connected to the bus and having a gate electrode receiving a second signal paired with the first signal; a source electrode connected to the source electrode of the second transistor; A third transistor of one conductivity type that receives a control signal that is connected to a potential point and that receives a control signal that becomes an active level after the power source potential stabilizes when the power source is turned on and becomes an inactive level before the power source potential drops when the power source is turned off, and a source electrode Is connected to a ground potential point, the drain electrode is connected to the source electrode of the first transistor, and the gate electrode is configured as a circuit including a fourth transistor of one conductivity type which receives the control signal.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional small computer system shown in FIG. 8 in that the output circuit of the small computer device includes a transistor Q2.
Between the source electrode and the power supply potential point (VDD2), the source electrode is connected to the source electrode of the transistor Q2, and the drain electrode and the gate electrode are connected to the power supply potential point (VDD
It is a circuit (13) provided with an N-channel type transistor Q3 connected to 2).

Next, the operation of this embodiment will be described.
FIG. 2 is a signal waveform diagram of the interface bus 20 by the output circuit 13.

When the output enable signal E is at a high level and the data DT is at a low level, the transistor Q1 is in the on state,
When the transistor Q2 is off, the interface bus 20 goes low. Transistor Q23
Is in the on state as long as power is supplied to the small computer device 10, the data DT becomes high level at the timing of t1, the transistor Q1 is turned off, and the transistor Q2 is turned on. Change to high level. At this time,
The current paths for charging up the interface bus 20 include transistors Q2 and Q3 in addition to the resistance elements R1 and R3.
Since there are current paths for the interface bus 20
The time ΔT from the low level to the high level (2V) is shortened as compared with the first example of the prior art, and the high speed operation becomes possible.

Here, it is assumed that the power supply of the small computer device 10 of its own is inadvertently cut off while transmitting and receiving data etc. between the other two small computer devices 10. As shown in FIG. 3, even when the power supply of the small computer device 10 is cut off at the timing of t2, the potential of the gate electrode of the transistor Q3 decreases and the transistor Q3 is turned off. Interface bus 20 from the power supply potential point (VDD2)
The current path to is cut off and the problem of illegally driving interface bus 20 to a low level is eliminated.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

The difference between the second embodiment and the first embodiment is that the gate electrode of the transistor Q3 is connected to the power supply potential point (VDD2) in the first embodiment, whereas In the second embodiment, when the power supply of the small computer device 10a is turned on, the power supply potential VDD2 is stabilized and then becomes an active level (high level), and when the power supply is turned off, the power supply potential VDD2 is controlled to be an inactive level (low level) before being lowered. Between the point where the signal CNT is input and the source electrode of the transistor Q1 and the ground potential point, the source electrode is connected to the ground potential point, the drain electrode is connected to the source electrode of the transistor Q1, and the control signal is applied to the gate electrode. The point is that a transistor Q4 for inputting CNT is provided.

Next, the operation of this embodiment will be described.
FIG. 5 is a voltage waveform diagram of each part for explaining the operation of this embodiment.

First, the small computer device 1
A case where a stable power supply is supplied to 0 will be described. In this case, the control signal CNT is at the high level, and the transistors Q3 and Q4 are in the ON state. At this time, when the data DT changes from the low level to the high level, the current path for charging up the interface bus 20 has the transistor Q3 in addition to the resistance elements R1 and R3.
Since the current path of Q2 exists, the time ΔT from reaching the low level to the high level is shortened, and high-speed operation is possible, as in the first embodiment.

Next, the case where the power is not supplied, and when the power is turned on and off is described. When the small computer device 10a is not supplied with power, the control signal CNT is at a low level and the transistors Q3 and Q4 are in an off state, so that the interface bus 20 is not illegally driven to a low level. . Further, after the power is turned on at the timing of t3 shown in FIG. 5 and the power supply potential VDD2 reaches a stable level, the control signal CNT is set to the high level at the timing of t4, and conversely, when the power is turned off, the control is first performed at the timing of t5. By controlling the power supply to be turned off at the timing of t6 after the signal CNT is set to the low level, the power supply potential VDD at the time of turning the power on and off
When it fluctuates, the interface bus 20 causes the power supply potential point (V
Since it is separated from DD2) and the ground potential point, it is possible to prevent an illegal low level from being output to the interface bus 20.

[0029]

As described above, according to the present invention, the third transistor for receiving the power supply potential or the control signal at the gate electrode is provided between the source electrode of the second transistor and the power supply potential point. As a result, at the time of normal data output, the current path by the second and third transistors is added to charge up the interface bus, which enables high-speed operation, and data transmission and reception between other small computer devices. Even if the power supply of its own small computer device is cut off during the operation, the third transistor is turned off and the interface bus is disconnected from its own power supply potential point. This has the effect of not adversely affecting the sending and receiving of.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a voltage waveform diagram of an interface bus by the output circuit of the embodiment shown in FIG.

FIG. 3 is a voltage waveform diagram of each part for explaining the operation and effect of the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a voltage waveform diagram of each part for explaining the operation and effect of the embodiment shown in FIG.

FIG. 6 is a first conventional small computer system.
3 is a circuit diagram showing an example of FIG.

7 is a voltage waveform diagram of an interface bus by an output circuit of the small computer system shown in FIG.

FIG. 8: Second conventional small computer system
3 is a circuit diagram showing an example of FIG.

9 is a voltage waveform diagram of an interface bus by an output circuit of the small computer system shown in FIG.

10 is a voltage waveform diagram of each part for explaining the operation and problems of the small computer system shown in FIG.

[Explanation of symbols]

10, 10a to 10c Small computer device 11 Input circuit 12, 12a, 12b Internal circuit 13, 13a to 13c Output circuit 20 Interface bus G1, G2 Logic gate IV1 Inverter Q1 to Q4 Transistor R1 to R4 Resistance element

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H03K 19/0175

Claims (2)

[Claims] 1. An interface bus to which a first resistance element and a second resistance element having a predetermined resistance value are respectively connected between a power supply potential point and a ground potential point, and each interface bus is connected. A plurality of small computers having at least one of an input circuit and an output circuit for transmitting and receiving data via the interface bus
A small computer system including a device, an output circuit of the small computer device, a source electrode connected to the ground potential point, a drain electrode connected to the interface bus, and a gate electrode receiving a first signal. A first conductivity type transistor, a second conductivity type second transistor having a drain electrode connected to the interface bus and having a gate electrode receiving a second signal paired with the first signal; and a source electrode. The second
Third of one conductivity type connected to the source electrode of the transistor and connecting the drain electrode and the gate electrode to the power supply potential point
A small computer system characterized in that it is a circuit including a transistor. 2. An output circuit of a small computer device, wherein a drain electrode is connected to an interface bus and a first electrode of one conductivity type that receives a first signal at a gate electrode, and a drain electrode is the interface bus. A second transistor of the opposite conductivity type which is connected to the gate electrode and receives a second signal paired with the first signal, a source electrode of which is connected to the source electrode of the second transistor and a drain electrode of which is a power supply potential point When the power supply is connected to the gate electrode, the third conductive type transistor receives the control signal which becomes the active level after the power supply potential is stabilized when the power is turned on and becomes the inactive level before the power supply potential is lowered when the power is turned off, and the source electrode is grounded. The drain electrode is connected to the potential point, the drain electrode is connected to the source electrode of the first transistor, and the gate electrode is connected to the control signal. The small computer system according to claim 1, which is a circuit including a fourth transistor of one conductivity type for receiving.