JPH06138957A - Mos resistance circuit - Google Patents

Abstract

PURPOSE:To provide a MOS resistance circuit which constructs a MOS transistor TR having the resistance value equal to the reference resistance and enables the power-down even when a MOS resistance is connected in series to an R string. CONSTITUTION:The resistance R and Rx are connected in series between the reference power supplies VR (+) and VR (-) with a connection terminal as VA. Meanwhile a TR Q1 and a resistance Ry are connected in series between both supplies VR (+) and VR (-) with a connection terminal as VB respectively. Furthermore these terminals VA and VB are defined as a plus input and a minus input respectively and an operational amplifier Op 1 is connected. The output terminal VG of the Op1 is defined as the gate input of the TR Q1. Then the TR Q1 is made to operate in a non-saturated state when both terminals VB and VA are virtually grounded, and the resistance value of the TR Q1 is controlled at (R/Rx).Ry.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS resistance circuit used for producing a desired resistance value by using a MOS resistance.

[0002]

2. Description of the Related Art FIG. 7 shows an MO manufactured by a conventional technique.
It is a figure which shows the structure of S resistance.

FIG. 1A shows a depletion type PMOS.
The MOS resistance using a transistor is shown, (b) shows the MOS resistance in which the gate voltage of the enhancement type PMOS transistor is VSS, and (c) shows the gate voltage of the enhancement type PMOS transistor as the drain voltage. The same MOS resistance is shown.

[0004]

However, as shown in FIG.
The MOS resistor having the configuration shown in (a) can produce a desired resistance value with relatively high accuracy, but has a problem that the process becomes complicated. Furthermore, FIG.
In the MOS resistors having the configurations shown in (b) and (c), the resistance value varies depending on the process variation, and it is difficult to apply the MOS resistor to a circuit that requires particularly high accuracy.

As described above, in the conventional circuit using the MOS resistance, it is difficult to obtain a desired resistance value due to the process variation and the like, and therefore, it has not been possible to use it in a circuit which requires particularly high accuracy.

Therefore, the mixing property with an analog circuit or the like is poor, and for example, an M for a reference voltage generating circuit of an AD converter or the like is used.
The application of the OS transistor is difficult because the reference voltage varies, and it has been necessary for the AD converter and the like to flow a static current even when another system is powered down.

The present invention has been made in view of the above problems, and an object of the present invention is to construct a MOS transistor having a resistance value equal to that of the reference resistor R and connect the MOS resistor in series to the R string. To enable power down.

[0008]

To achieve the above object, in a MOS resistance circuit of the present invention, a first resistor R and a second resistor connected in series between a first and a second reference power source. Rx, a MOS transistor and a third resistor Ry connected in series between the first and second reference power sources, and a connection end of the first resistor R and the second resistor Rx is a non-inverting input,
The connection terminal between the drain of the MOS transistor and the third resistor Ry is used as the inverting input, and the output terminal is connected to the MOS transistor.
A MOS resistance comprising: an operational amplification means that is a gate input of the transistor; and a control means that controls the resistance of the MOS transistor to (R / Rx) · Ry by operating the MOS transistor in a non-saturated state. circuit.

[0009]

That is, in the MOS resistance circuit of the present invention, the first resistance R and the second resistance Rx are connected in series between the first and second reference power supplies, and the first and second resistances are further connected. A MOS transistor and a third resistor Ry are connected in series between the reference power sources. Further, the first resistor R and the second resistor
Is connected to a non-inverting input at the connection end with the resistor Rx and an inverting input at the connection end between the drain of the MOS transistor and the third resistor Ry, and the output end of the operational amplification means is connected to the above-mentioned output end. It is used as the gate input of a MOS transistor. Then, the control means causes the MOS transistor to operate in a non-saturated state and controls the resistance value of the MOS transistor to (R / Rx) · Ry.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a MOS according to a first embodiment of the present invention.
It is a figure which shows the structure of a resistance circuit.

As shown in the figure, a resistor R and a resistor Rx are connected in series between the reference voltages VR (+) and VR (-),
The connection end is VA. Further, the reference voltage VR (+)
And VR (-), the PMOS transistor Q1 and the resistor Ry are connected in series, and the connection end is VB. Then, an operational amplifier OP1 having the VA (-) input and VB (+) input is connected, and the output terminal VG of the operational amplifier OP1 is used as the gate input of the PMOS transistor Q1.

The output of the operational amplifier OP1 is P
If negative feedback is applied to the gate of the MOS transistor Q1,
The voltage of VB becomes equal to the reference voltage VA, and at this time, PM
PMO so that the OS transistor Q1 operates in non-saturation
If the value of the dimension Rx of the S transistor Q1 is selected, the PMOS transistor Q1 can be treated as a pure resistance having the resistance value R.

If the VG terminal is taken out and input to the PMOS transistor Q2 having the same dimension, P
The resistance value of the MOS transistor Q2 becomes R, and it becomes possible to use a MOS resistor in another circuit. And the resistance R
The resistance values of y and Rx are different, and the dimension is Q.
When 1 = Q2, the resistance value of the PMOS transistor Q2 is (R / Rx) · Ry.

Further, when the output VG of the operational amplifier OP1 is used as the gate input of the PMOS transistor Q2 whose source is connected to VR (+) in this way, the PMOS
By setting the dimension ratio of the transistors Q1 and Q2 to 1: d, the resistance value ratio can be controlled to 1: 1 / d.

The specific operation of the MOS resistance circuit according to the first embodiment will be described below. Now, let it be assumed that the resistance value to be created by using the MOS resistance is R, and Ry = Rx for simplification of the description.

A resistor Rx is connected in series with a desired resistance value R, and the connection terminal VA is input to the (-) terminal of the operational amplifier OP1. Then, the PMOS transistor Q1 and the resistor R
The connection terminal VB with x is input to the (+) terminal of the operational amplifier OP1, and the output of this operational amplifier OP1 is fed back to the gate terminal of the PMOS transistor Q1.

As a result, the operational amplifier OP1 has an NFB
Since (negative feedback) is applied, VA = VB, and the resistance value of the PMOS transistor Q1 becomes equal to R. Where P
In order to handle the MOS transistor Q1 as a resistor, the PMOS transistor Q1 must be operated in a non-saturated state (VDD-VB <VDD-VG).

VG at this time is a PMOS transistor Q2
By applying to the gate of
If the dimensions of 1 and Q2 are the same, PMOS
The transistor Q2 can be regarded as a pure resistance having a resistance value R.

Next, second and third embodiments in which the above-mentioned first embodiment is applied to a circuit which constitutes an R string such as an AD converter will be described.

FIG. 2 is a diagram showing a configuration of a second embodiment in which NMOS transistors Q3 and Q4 for cutting a current path are added to the circuit of the first embodiment.

As shown in the figure, in the second embodiment, NMOS transistors Q3 and Q4 are inserted between resistors Rx and Ry and VR (-), and the gate is controlled by a power down signal PD. In addition, it is a circuit provided with a power down mode for controlling the output of the operational amplifier OP1 so that the PMOS transistor Q1 turns “off”.

FIG. 3 is a diagram showing the configuration of a third embodiment in which an NMOS transistor Q3 is added to the circuit of the first embodiment.

As shown in the figure, in the third embodiment, a power-down NMOS transistor Q3 is added between the resistors Rx and VR (-), and the power-down signal PD causes N
The MOS transistor Q3 is turned off, and the operational amplifier OP
This is a circuit that realizes power down by setting the output of 1 to a voltage at which the PMOS transistor Q1 turns "off".

The MOS resistance circuits according to the first to third embodiments of the present invention have been described above.
To the reference voltages VR (+) and VR in the third embodiment
Replace (-) with the PMOS transistor NMO
The MOS resistance circuits according to the fourth to sixth embodiments in which the NMOS transistor is replaced by the PMOS transistor in the S transistor will be described.

FIG. 4 shows an MO according to the fourth embodiment of the present invention.
It is a figure which shows the structure of an S resistance circuit. As shown in the figure,
A resistor Rx resistor R is connected in series between the reference voltages VR (+) and VR (-), and the connecting end is VA. further,
Between the reference voltages VR (+) and VR (-), resistors Ry and N
The MOS transistor Q5 is connected in series, and its connection end is set to VB. Then, an operational amplifier OP1 having VA (-) input and VB (+) input is connected, and an output terminal VG of the operational amplifier OP1 is used as a gate input of the transistor Q1.

Then, at the output of the operational amplifier, the NMOS
When negative feedback is applied to the gate of the transistor Q5, VB becomes equal to the reference voltage VA. At this time, if the value of the dimension Rx of the NMOS transistor Q5 is selected so that the NMOS transistor Q5 operates in a non-saturated state, the NMOS transistor Q5 becomes It can be treated as a pure resistance having a resistance value R.

Here, if VG is taken out and input to the NMOS transistor Q6 of the same dimension, the NMOS is obtained.
The resistance value of the transistor Q6 becomes R, and the MOS
It becomes possible to use a resistor. And the resistors Ry and R
When x is not equal and the dimension is Q5 = Q6, the resistance value of the NMOS transistor Q6 is (R / R
x) and Ry.

Further, in the circuit in which the output VG of the operational amplifier OP1 is used as the gate input of the NMOS transistor Q6 whose source is connected to VR (+), the NMOS is used.
By setting the dimension ratio of the transistors Q5 and Q6 to 1: d, the resistance ratio can be controlled to 1: 1 / d.

Next, fifth and sixth embodiments in which the above-mentioned fourth embodiment is applied to a circuit which constitutes an R string such as an AD converter will be described.

FIG. 5 is a diagram showing the configuration of the fifth embodiment in which PMOS transistors Q7 and Q8 for cutting the current path are added to the circuit of the fourth embodiment.

As shown in the figure, in the fifth embodiment, PMOS transistors Q7 and Q8 are respectively inserted between resistors Rx and Ry and VR (+), and the gate is controlled by a power down signal PD. In addition, the output VG of the operational amplifier OP1 is turned off by turning off the PMOS transistors Q7 and Q8
It is a circuit with a power-down mode for controlling so.

FIG. 6 is a diagram showing a configuration of a sixth embodiment in which a PMOS transistor Q7 is added to the circuit of the fourth embodiment.

As shown in the figure, in the sixth embodiment, a power-down PMOS transistor Q7 is added between the resistors Rx and VR (+), and the power-down signal PD turns off the PMOS transistor Q7. ", Operational amplifier OP
This circuit realizes power down by setting the output of 1 to a voltage at which the PMOS transistor Q7 turns "off". As described above, according to the present invention, since a MOS transistor having a resistance value equal to that of the reference resistor R is provided, a MOS resistor can be connected in series to the R string, so that, for example, a reference voltage generation circuit of an AD converter or the like. To M
When the OS transistor is applied, it is possible to perform power down because it is not necessary to pass a static current as in the conventional case as the power down of another system.

[0035]

According to the present invention, there is provided a MOS resistance circuit which constitutes a MOS transistor having a resistance value equal to that of the reference resistance R and enables power-down even when a MOS resistance is connected in series to the R string. be able to.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a MOS resistance circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a MOS resistance circuit according to a second embodiment in which the present invention is applied to an AD converter.

FIG. 3 is a diagram showing a configuration of a MOS resistance circuit according to a third embodiment in which the present invention is applied to an AD converter.

FIG. 4 is a diagram showing a configuration of a MOS resistance circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a MOS resistance circuit according to a fifth embodiment in which the present invention is applied to an AD converter.

FIG. 6 is a diagram showing a configuration of a MOS resistance circuit according to a sixth embodiment in which the present invention is applied to an AD converter.

7A to 7C are diagrams showing a configuration of a conventional MOS resistor.

[Explanation of symbols]

R, Rx, Ry ... Resistance, Q1, Q2, Q7, Q8 ... PM
OS transistors, Q3, Q4, Q5, Q6 ... NMOS
Transistor, OP1 ... Operational amplifier.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03M 1/34 9065-5J

Claims (1)

[Claims] 1. A first resistor R and a second resistor Rx connected in series between a first and a second reference power source, and an MO connected in series between the first and second reference power sources.
The connection end of the S transistor and the third resistor Ry and the first resistor R and the second resistor Rx is a non-inverting input, and the connection end of the drain of the MOS transistor and the third resistor Ry is an inverting input. Further, an operational amplifier means having its output end as a gate input of the MOS transistor, and a control means for operating the MOS transistor in a non-saturation operation and controlling the resistance value of the MOS transistor to (R / Rx) · Ry. A MOS resistance circuit comprising.