JPH0613615A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device whose production yield can be increased by protecting a gate insulating film under a gate electrode against the etching destruction by HF etchant to prevent the deterioration of characteristics of elements when a contact window is opened in the layer insulating film on the gate electrode by using the HF etchant. CONSTITUTION:A polysilicon semiconductor layer 12, a gate SiO2 film 14 and Al film 16 are sequentially formed on a transparent substrate 10, and further a TiN protective film 18 having the property of HF resistance and conductivity is formed. The TiN protective film 18 and Al film 16 are patterned to form an Al gate electrode 16a, the upper surface of which is covered with the TiN protective film 18. After a PSG layer insulating film 26 is formed on the whole surface thereof, the PSG layer insulating film 26 on the TiN protective film 18 is selectively etched with the HF etchant to open a contact window 28 on the TiN protective film 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a MIS (Metal Insulator Semiconductor).
Type transistor manufacturing method. LCD (Liquid Crystal Display) as one of MIS type transistors
For active matrix used as drive circuit for
There is an FT (Thin Film Transistor).

In the active matrix type display device, by providing a switch element for each pixel at the matrix intersection, crosstalk at the time of non-selection such as a simple matrix can be completely eliminated, and an excellent display performance can be obtained. It is possible to show. Among them, the TFT-LCD using a TFT as the switch element has a high driving ability as a control element, and is therefore applied to an LCD with a built-in driver and a high image and high definition LCD.

[0003]

2. Description of the Related Art Conventional active matrix TFTs
As shown in FIG. 8, a poly-Si (silicon) semiconductor layer 12 is formed on a transparent substrate 10 made of, for example, a glass substrate. A source region and a drain region are formed opposite to each other in the poly-Si semiconductor layer 12, and an Al (aluminum) gate is formed on the channel region sandwiched between the source region and the drain region via a gate SiO ₂ film 14. An electrode 16a is formed, and an Al wiring layer (not shown) connected to the Al gate electrode 16a through a contact window 28 opened in the PSG (Phospho-Silicate Glass) interlayer insulating film 26 on the Al gate electrode 16a is formed. Has been done.

The Al gate electrode 16a is used here because it cannot be processed at a high temperature because it is formed on the transparent substrate 10 made of, for example, a glass substrate.

[0005]

In a poly-Si-TFT using such a poly-Si semiconductor layer 12, as shown in FIG.
As shown in (a) and (b), when the contact window 28 is opened in the PSG interlayer insulating film 26 on the Al gate electrode 16a, the contact window 28 is relatively large. Since the lower layer may be damaged, wet etching is usually performed. Therefore, the etching process using the HF (hydrofluoric acid) -based etching solution is performed.

However, when the etching process using the HF-based etching solution is performed, PS on the Al gate electrode 16a is increased.
When opening the contact window 28 in the G interlayer insulating film 26,
The gate SiO ₂ film 14 under the Al gate electrode 16a is HF.
The problem that it is etched by the system etching liquid occurred. This is because, as shown in FIG. 8B, in the Al gate electrode 16a, the HF-based etching solution permeates along the grain boundary of Al and reaches the gate SiO ₂ film 14 to reach the gate SiO ₂ film. This is considered to be due to the phenomenon that 14 is etched.

As described above, T for active matrix of LCD
The FT has been described, but at present, not only the TFT for LCD but also the MIS transistor in general, the manufacturing process is being lowered in temperature. As an example thereof, a method of implanting impurity ions while heating the substrate when forming the source region and the drain region has been proposed. According to this method, the heat treatment in the subsequent step, which is required when implanting the impurity ions in a state where the substrate is cooled, that is, the annealing treatment for activating the implanted impurity ions is unnecessary. Therefore, the resistance can be reduced at a lower temperature in the entire process. Therefore, by using this impurity ion implantation method of heating the substrate, a low resistance metal such as Al can be used for the gate electrode.
This means that the solution of the above-mentioned problems regarding the LCD TFT is a major problem for MIS type transistors in general.

Therefore, the present invention protects the gate insulating film below the gate electrode from etching damage by the HF-based etching solution when the contact window is opened in the interlayer insulating film on the gate electrode by using the HF-based etching solution, An object of the present invention is to provide a method for manufacturing a semiconductor device, which prevents deterioration of element characteristics and improves yield.

[0009]

Means for Solving the Problems The problems described above include a semiconductor layer on a semiconductor substrate or an insulating substrate, a source region and a drain region formed by adding impurities to the surface of the semiconductor substrate or the semiconductor layer, and the source. The gate electrode formed on the channel region sandwiched between the region and the drain region via the gate insulating film, the interlayer insulating film formed on the entire surface, and the contact window opened on the interlayer insulating film. In a method of manufacturing a semiconductor device having a wiring layer connected to a gate electrode, a step of forming a first protective film having hydrofluoric acid resistance and conductivity between the gate electrode and the interlayer insulating film, A step of selectively removing the interlayer insulating film by etching using a hydrofluoric acid-based etching solution to open the contact window on the first protective film; and a step of opening the contact window in the contact window. It is achieved by the method for manufacturing a semiconductor device characterized by comprising the step of through the protective film forming the wiring layer connected to the gate electrode.

In the method of manufacturing a semiconductor device described above, after the gate insulating film and the gate electrode film are sequentially deposited on the semiconductor substrate or the semiconductor layer, hydrofluoric acid resistance and conductivity are provided on the gate electrode film. The first step of forming the first protective film having a property, patterning the first protective film and the gate electrode film into a predetermined shape, and covering the upper surface with the first protective film. A second step of forming the gate electrode, and using the first protective film and the gate electrode as a mask, adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer to form the source region and the drain region. And a third step of forming an interlayer insulating film on the entire surface, and then the interlayer insulating film is selectively etched and removed using a hydrofluoric acid-based etching solution to form a film on the first protective film. The method further comprises a fourth step of opening the contact window and a fifth step of forming the wiring layer connected to the gate electrode via the first protective film in the contact window. And a semiconductor device manufacturing method.

In the method of manufacturing a semiconductor device, the gate insulating film and the gate electrode film are sequentially deposited on the semiconductor substrate or the semiconductor layer, and then the gate electrode film is patterned into a predetermined shape. A first step of forming the gate electrode, and a second step of selectively forming the first protective film having hydrofluoric acid resistance and conductivity on the upper surface and the side surface of the gate electrode, A third step of forming the source region and the drain region by adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer using the first protective film and the gate electrode as a mask, and the entire surface, A fourth step of depositing the interlayer insulating film, selectively etching away the interlayer insulating film using a hydrofluoric acid-based etching solution, and opening the contact window on the first protective film. It is achieved by the method for manufacturing a semiconductor device characterized by comprising a fifth step of forming the wiring layer connected to the gate electrode via the first protective film in the contact window.

In the method for manufacturing a semiconductor device described above, the gate insulating film and the gate electrode film are sequentially deposited on the semiconductor substrate or the semiconductor layer, and then the gate electrode film is patterned into a predetermined shape. A first step of forming the gate electrode, and a second step of forming the source region and the drain region by using the gate electrode as a mask and adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer. And a step of selectively forming the first protective film having hydrofluoric acid resistance and conductivity on the upper surface and the side surface of the gate electrode and the upper surface or the upper surface and the side surface of the source region and the drain region. And the step of depositing the interlayer insulating film on the entire surface, and then selectively etching away the interlayer insulating film using a hydrofluoric acid-based etching solution to remove the gate electrode. A fourth step of opening the contact window on the first protective film and opening contact windows on the first protective film on the source region and the drain region, respectively; Forming a wiring layer connected to the gate electrode through the first protective film, and wiring connected to the source region and the drain region through the first protective film in the contact window, respectively. And a fifth step of forming a layer.

Further, the above-mentioned problem is that a semiconductor layer on a semiconductor substrate or an insulating substrate, a source region and a drain region formed by adding impurities to the surface of the semiconductor substrate or the semiconductor layer, the source region and the drain. A gate electrode formed on the channel region sandwiched between the regions via a gate insulating film, an interlayer insulating film formed on the entire surface, and connected to the gate electrode via a contact window opened on the interlayer insulating film A method of manufacturing a semiconductor device having a wiring layer to be formed, the method further comprising the step of forming a first protective film having hydrofluoric acid resistance and conductivity between the gate insulating film and the gate electrode. And a semiconductor device manufacturing method.

In the method of manufacturing a semiconductor device described above, the step of selectively adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer is performed by an ion doping method or an ion shower method. This is a step of implanting unseparated ions, and is achieved by a method of manufacturing a semiconductor device, which is accompanied by an annealing treatment for activating the impurity ions implanted into the surface of the semiconductor substrate or the semiconductor layer.

In the method of manufacturing a semiconductor device described above, the semiconductor layer may be single crystal silicon, polycrystalline silicon,
Or amorphous silicon, the gate electrode is made of aluminum, silicon-added aluminum, or titanium, and the first protective film is molybdenum, tungsten,
It is achieved by a method for manufacturing a semiconductor device, which comprises tantalum, chromium, or titanium nitride.

Further, the above-mentioned problem is that a semiconductor layer on a semiconductor substrate or an insulating substrate, a source region and a drain region formed by adding impurities to the surface of the semiconductor substrate or the semiconductor layer, the source region and the drain. A gate electrode formed on a channel region sandwiched between regions via a gate insulating film, an interlayer insulating film formed on the entire surface, and connected to the gate electrode via a contact window opened on the interlayer insulating film In a method for manufacturing a semiconductor device having a wiring layer for forming, between the gate electrode and the interlayer insulating film,
Forming a first protective film having hydrofluoric acid resistance and conductivity; forming a second protective film on the first protective film; the second protective film, the first protective film; Using the protective film and the gate electrode as a mask, predetermined impurities are added to the surface of the semiconductor substrate or the semiconductor layer to form the source region and the drain region, and the second protective film is used as a barrier against the addition of impurities. And a step of preventing the addition of impurities to the first protective film, and the interlayer insulating film and the second protective film are selectively etched and removed using a hydrofluoric acid-based etching solution to remove the first protective film. A semiconductor comprising: a step of opening the contact window on a protective film; and a step of forming the wiring layer connected to the gate electrode via the first protective film in the contact window. Device manufacturing method Thus it is achieved.

In the method of manufacturing a semiconductor device described above, the step of selectively adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer may be performed by ion implantation with the semiconductor substrate or the insulating substrate being heated. The method is a method of manufacturing a semiconductor device, which is a step of implanting ions in which the predetermined impurities are separated by mass.

In the method of manufacturing a semiconductor device described above, the step of selectively adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer is performed by ion doping with the semiconductor substrate or the insulating substrate being heated. Method or ion shower method, the method is a step of implanting ions of the predetermined impurities whose mass is not separated.

[0019]

In the present invention, HF is formed on the interlayer insulating film on the gate electrode.
Before opening the contact window with a system-based etching solution,
By forming the first protective film having HF resistance and conductivity on the gate electrode, it is possible to prevent the HF-based etching solution for etching the interlayer insulating film from directly contacting the gate electrode or the gate insulating film. Further, since the HF-based etching solution is prevented from penetrating the gate electrode and reaching the gate insulating film, it is possible to prevent the gate insulating film from being broken by the HF-based etching solution.

Further, by simultaneously forming such a first protective film also on the source region and the drain region,
For example, it serves as a barrier at the Al / Si interface of the contact between the source region and the drain region made of poly-Si and the Al wiring layer, and therefore has the effect of preventing contact failure. Moreover, HF resistance is provided between the gate insulating film and the gate electrode.
By sandwiching the first protective film having electrical conductivity and conductivity, it is possible to prevent the gate insulating film from being destroyed by the HF-based etching solution as in the case of forming the first protective film on the gate electrode. .

Further, in the present invention, the semiconductor substrate or the insulating substrate is heated by forming the second protective film as a barrier against the addition of impurities on the first protective film having HF resistance and conductivity. Even if the impurity ions are implanted in the state, whether the impurity ions are not implanted into the first protective film,
Alternatively, even if it is injected into the surface of the first protective film, it is not injected into the entire surface, so that deterioration of the HF resistance of the first protective film is prevented. Therefore, the first protective film can prevent the HF-based etching liquid from penetrating into the gate electrode and prevent the gate insulating film from being destroyed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on illustrated embodiments. FIG. 1 is a process chart for explaining a method for manufacturing a poly-Si-TFT according to the first embodiment of the present invention. The first embodiment is characterized in that the upper surface of the Al gate electrode 16a is covered with a protective film having HF resistance and conductivity.

After a poly-Si semiconductor layer 12 having a thickness of 100 nm, a gate SiO ₂ film 14 having a thickness of 150 nm, and an Al film 16 having a thickness of 800 nm are sequentially formed on the transparent substrate 10,
A TiN (titanium nitride) protective film 18 having a HF resistance and conductivity and having a thickness of 50 nm is formed on the entire surface by sputtering. The formation of the TiN protective film 18 is
Ti target with N ₂ gas flow of 20 SCCM and power of 20
Sputtering was performed under the condition of 0 W (see FIG. 1A).

Then, the TiN protective film 18 and the Al film 16 are formed.
Is patterned into the shape of the gate electrode, and the upper surface is TiN
The Al gate electrode 16a covered with the protective film 18 is formed. Then, using the TiN protective film 18 and the Al gate electrode 16a as a mask, an ion doping method is used in which impurities are ion-implanted while the mass is not separated. For example, P + (phosphorus) ions or As + ( arsenic)
An n-type impurity ion such as an ion or a p-type impurity ion such as a B + (boron) ion is introduced (FIG. 1 (b)).
reference).

Next, the poly-Si semiconductor layer 12 is patterned into the shape of the element region, sandwiched between the source region 20 and the drain region 22 into which the impurity ions are introduced, and the source region 20 and the drain region 22, and the gate Si is formed.
A channel region 24 located below the Al gate electrode 16a is formed via the O ₂ film 14. Then, the entire thickness 60
A 0 nm PSG interlayer insulating film 26 is deposited. And Ti
N protective film 18, source region 20 and drain region 2
The PSG interlayer insulating film 26 on 2 is selectively etched using an HF-based etching solution to open contact windows 28, 30, 32 on the TiN protective film 18 and the source region 20 and the drain region 22, respectively (FIG. 1 (c)).

Further, annealing treatment is performed under the condition of a temperature of 400 ° C. to activate the impurity ions introduced into the source region 20 and the drain region 22. This annealing process is not performed immediately after the introduction of the impurity ions, but the contact windows 28, 3
This annealing treatment is performed after opening 0 and 32.
This is because the HF resistance may be deteriorated due to the deterioration of the film quality of the TiN protective film 18 formed on the upper surface of the Al gate electrode 16a.

That is, the TiN protective film 18 is formed of the HF-based etching solution A when the contact windows 28, 30, 32 are opened.
This is because if the permeation into or penetration of the gate electrode 16a or the gate SiO ₂ film 14 is prevented, it will fulfill its role, and even if the HF resistance is lowered thereafter due to deterioration of the film quality, no problem will occur. Next, although not shown in the drawing, A is provided through the TiN protective film 18 in the contact window 28.
An Al wiring layer connected to the 1-gate electrode 16a and an Al wiring layer connected to the source region 20 and the drain region 22 through the contact windows 30 and 32 are formed.

As described above, according to the first embodiment, the upper surface of the Al gate electrode 16a is made of Ti having HF resistance and conductivity.
By covering with the N protective film 18, the PSG interlayer insulating film 26 on the TiN protective film 18 is selectively etched using the HF-based etching liquid to open the contact window 28, the HF-based etching liquid is removed. It is possible to prevent the Al gate electrode 16a or the gate SiO ₂ film 14 from penetrating and penetrating. Therefore, the gate SiO ₂ film 14 under the Al gate electrode 16a is protected from the etching breakdown by the HF-based etching solution, and the poly-Si-TF
It is possible to prevent the characteristic deterioration of T and improve the manufacturing yield thereof.

Next, poly S according to the second embodiment of the present invention.
A method for manufacturing an i-TFT will be described with reference to the process chart of FIG. The same components as those of the TFT shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the second embodiment, only the upper surface of the Al gate electrode 16a is resistant to H in the first embodiment.
It is characterized in that it is covered with the TiN protective film 18 having F property and conductivity, but not only the upper surface of the Al gate electrode but also its side surface is covered with a protective film having HF resistance and conductivity.

After forming a poly-Si semiconductor layer 12 having a thickness of 150 nm, a gate SiO ₂ film 14 having a thickness of 100 nm and an Al film 16 having a thickness of 600 nm on the transparent substrate 10 in this order,
Only this Al film 16 is patterned into the shape of a gate electrode to form an Al gate electrode 16a (see FIG. 2A). Next, a 30 nm-thickness W (tungsten) protective film 34 having a HF resistance and conductivity is grown on the upper surface and the side surface of the Al gate electrode 16a. At this time, the W protective film 34 has a substrate temperature of 270 ° C. and a WF ₆ flow rate of 10 SCCM.
By flowing the SiH ₄ source gas and the H ₂ carrier gas at a flow rate of 6 SCCM, the SiH ₄ does not grow on the gate SiO ₂ film 14 and selectively grows only around the Al gate electrode 16a (FIG. )reference).

Next, after the gate SiO ₂ film 14 is removed by dry etching using the W protective film 34 and the Al gate electrode 16a as a mask, the W protective film 34 is again formed.
Using the Al gate electrode 16a as a mask and an ion shower method in which ions are implanted while the mass of impurities is not separated, an n-type impurity such as P + or As + is added to the poly-Si semiconductor layer 12.
Type impurity ions or p type impurity ions such as B + are introduced.

Then, similarly to the case of the first embodiment, the poly-Si semiconductor layer 12 is patterned into the shape of the element region to form the source region 20 and the drain region 22 into which the impurity ions are introduced, and these. And a channel region 24 sandwiched between them. Subsequently, after depositing a PSG interlayer insulating film 26 having a total thickness of 600 nm, contact windows 28 and 3 are formed on the W protective film 34 and the source region 20 and the drain region 22, respectively, using an HF-based etching solution.
0 and 32 are opened (see FIG. 2C).

Further, for the same reason as in the case of the first embodiment, after opening the contact windows 28, 30, 32,
Annealing is performed at a temperature of 300 ° C. to activate the impurity ions introduced into the source region 20 and the drain region 22. Next, although not shown, the contact window 2
Then, an Al wiring layer connected to the Al gate electrode 16a via the W protective film 34 in FIG. 8 and an Al wiring layer connected to the source region 20 and the drain region 22 via the contact windows 30 and 32 are formed.

As described above, according to the second embodiment, not only the upper surface of the Al gate electrode 16a but also the side surface thereof is covered with the W protective film 34 having HF resistance and conductivity, so that the W protective film 34 is formed. The upper PSG interlayer insulating film 26 is HF
When the contact window 28 is opened by selective etching using a system-based etching solution, the HF-based etching solution is more effectively prevented from penetrating into the Al gate electrode 16a or the gate SiO ₂ film 14 and penetrating therethrough. be able to. Therefore, it is possible to obtain the same effect as that of the first embodiment or more.

Next, poly S according to the third embodiment of the present invention
A method of manufacturing the i-TFT will be described with reference to the process chart of FIG. The same components as those of the TFT shown in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In the third embodiment, the upper surface and the side surface of the Al gate electrode 16a are covered with the W protective film 34 having HF resistance and conductivity in the second embodiment, but not only the upper surface and the side surface of the Al gate electrode 16a. The feature is that the upper surfaces of the source / drain regions are also covered with a protective film having HF resistance and conductivity.

After forming a poly-Si semiconductor layer 12 having a thickness of 100 nm, a gate SiO ₂ film 14 having a thickness of 100 nm, and an Al film 16 having a thickness of 600 nm on the transparent substrate 10 in this order,
The Al film 16 and the gate SiO ₂ film 14 are patterned into the shape of a gate electrode to form an Al gate electrode 16a (see FIG. 3A). Next, the poly-Si semiconductor layer 12 is patterned into the shape of the element region. And Al
Using the gate electrode 16a as a mask, the ion shower method is used to introduce predetermined impurity ions into the poly-Si semiconductor layer 12 to form the source region 20 and the drain region 22. At the same time, these source region 20 and drain region 2
A channel region 24 sandwiched between the two is formed.

Subsequently, only on the upper surface and the side surface of the Al gate electrode 16a and the upper surface and the side surface of the source region 20 and the drain region 22, there is a thickness 2 having HF resistance and conductivity.
The 0 nm W protective films 36a, 36b, and 36c are selectively grown (see FIG. 3B). Then, after depositing a PSG interlayer insulating film 26 with a thickness of 500 nm on the entire surface,
The W protective films 36a, 36b, 3
Contact windows 28, 30, and 32 are opened on 6c, respectively (see FIG. 3C).

Furthermore, for the same reason as in the case of the first embodiment, after the contact windows 28, 30, 32 are opened,
Annealing is performed at a temperature of 400 ° C. to activate the impurity ions introduced into the source region 20 and the drain region 22. Next, although not shown, the contact window 2
W in the Al wiring layer and the contact windows 30 and 32 connected to the Al gate electrode 16a through the W protective film 36a in 8
The source region 20 is formed through the protective films 36b and 36c.
And an Al wiring layer connected to the drain region 22 is formed.

As described above, according to the third embodiment, the upper surface and the side surface of the Al gate electrode 16a are covered with the W protective film 36a having HF resistance and conductivity, and the source region 2 is formed.
The same W protective films 36b, 3 are formed on the 0 and drain regions 22.
When the PSG interlayer insulating film 26 on the W protective film 36a is selectively etched by using an HF-based etching solution to open the contact window 28 by covering with 6c, the same as in the second embodiment. In addition to the effect, the W protective films 36b and 36c have the contact window 3
Source regions 20 and drain regions 22 and A in 0 and 32
Since it becomes a barrier at the Al / Si interface with the 1 wiring layer, the effect of preventing contact failure is great. Therefore, the manufacturing yield of the poly-Si-TFT can be dramatically improved more than the second embodiment.

Next, poly S according to the fourth embodiment of the present invention
A method for manufacturing an i-TFT will be described with reference to the process chart of FIG.
It The same components as those of the TFT of FIG.
The reference numerals are given and the description is omitted. This fourth embodiment is
In the first to third embodiments, at least the Al gate electrode 16 is used.
a TiN protective film 18 having an HF resistance and conductivity on its upper surface
Alternatively, while being covered with W protective films 34 and 36a, it is resistant to H
A protective film having F property and conductivity is formed on the gate SiO. ₂Membrane and A
It is characterized in that it is formed between the gate electrode and the gate electrode.

On the transparent substrate 10, poly S having a thickness of 80 nm is formed.
i semiconductor layer 12, 100 nm thick gate SiO ₂ film 1
After forming 4 in order, the entire surface is resistant to HF by the sputtering method.
30 nm thick TiN protective film 38 having conductivity and conductivity
To form. The TiN protective film 38 is formed by using a sputtering method with a Ti target at an N ₂ gas flow rate of 10 SC.
The test was performed under the conditions of CM and power of 200 W (see FIG. 4 (a)).

Then, a thickness of 1 μm is formed on the TiN protective film 38.
After forming the Al film 16 m, by patterning the Al film 16, TiN protective film 38 and the gate SiO ₂ film 14 into the shape of the gate electrode, Ti between the gate SiO ₂ film 14
The Al gate electrode 16a sandwiching the N protective film 38 is formed (see FIG. 4B). Next, the poly-Si semiconductor layer 12 is patterned into the shape of the element region. Then, using the Al gate electrode 16a as a mask, an ion shower method is used,
Predetermined impurity ions are introduced into the poly-Si semiconductor layer 12 to form the source region 20 and the drain region 22.
At the same time, a channel region 24 sandwiched between the source region 20 and the drain region 22 is formed.

Subsequently, after depositing a PSG interlayer insulating film 26 having a thickness of 500 nm on the entire surface, contact windows 28 and 30, respectively, are formed on the Al gate electrode 16a and the source region 20 and the drain region 22 by using an HF etching solution.
32 is opened (see FIG. 4 (c)). Further, for the same reason as in the case of the first embodiment, the contact window 28,
After the openings of 30 and 32, annealing treatment is performed under the condition of a temperature of 400 ° C. to activate the impurity ions introduced into the source region 20 and the drain region 22.

Next, although not shown, the contact window 2
W in the Al wiring layer and the contact windows 30 and 32 connected to the Al gate electrode 16a through the W protective film 36a in 8
The source region 20 is formed through the protective films 36b and 36c.
And an Al wiring layer connected to the drain region 22 is formed. Thus, according to the fourth embodiment, the gate SiO ₂
By sandwiching a TiN protective film 38 having HF resistance and conductivity between the film 14 and the Al gate electrode 16a, Al
When the PSG interlayer insulating film 26 on the gate electrode 16a is selectively etched using an HF-based etching solution to open the contact window 28, even if the HF-based etching solution is A
penetrates into the l gate electrode 16a, even after passing through the grain boundary of Al, the TiN protective film 18 on the gate SiO ₂ film 14, HF-based etching solution gate SiO ₂
It is possible to prevent the film 14 from penetrating and penetrating. Therefore, the same effect as that of the first embodiment can be obtained.

Next, poly S according to the fifth embodiment of the present invention
A method of manufacturing the i-TFT will be described with reference to the process chart of FIG. The same components as those of the TFT shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. The fifth embodiment employs a method of implanting impurity ions in a state where a substrate is heated in a step of forming source / drain regions, and has a low resistance without performing an annealing treatment for activating the implanted ions. It was made possible to be converted. However, if this method is immediately applied to the first embodiment, the TiN protective film 1 having the HF resistance and the conductivity formed on the Al gate electrode 16a by the impurity ion implantation in the heated state.
8 is damaged and its HF resistance deteriorates. Therefore, the fifth embodiment is characterized in that the second protective film for protecting the protective film having HF resistance and conductivity from the impurity ion implantation in the heated state is formed.

On the transparent substrate 10, using the sputtering method,
After forming the poly-Si semiconductor layer 12 having a thickness of 80 nm,
Pattern in the shape of the child region. Then, LPCVD
(Low Pressure Chemcal Vapor Deposition) method
80 nm thick gate SiO over the entire surface₂Form the film 14
And this gate SiO₂Sputtering method is used on the film 14.
A 500 nm thick Al film 16 and HF resistance and conductivity.
And a W protective film 40 having a thickness of 50 nm is sequentially formed,
Further, on the W protective film 40, SiO with a thickness of 50 nm is formed. ₂Protective film
42 is formed.

Then, the SiO ₂ protective film 42, the W protective film 40, the Al film 16, and the gate SiO ₂ film 14 are patterned into the shape of a gate electrode, and the stacked W protective film 40 and SiO ₂ protective film 42 are used. A covered on the top
The l gate electrode 16a is formed on the gate SiO ₂ film 14 (see FIG. 5A). Then, the transparent substrate 10 is heated to the temperature 2
In the state of being heated to 00 ° C., B + ions are introduced into the poly-Si semiconductor layer 12 using the SiO ₂ protective film 42 as a mask by using the ion shower method to form the source region 20 and the drain region 22. At the same time, these source regions 2
Channel region 24 sandwiched between 0 and drain region 22
To form.

In this case, the ion shower method is B ₂
Acceleration energy of 20 ke using H ₆ (diborane) gas
The ion implantation was performed under V and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Therefore, due to the range of B + ions, the peak position of the ions injected into the SiO ₂ protective film 42 and the poly-Si semiconductor layer 12 is 15 nm to 25 nm from the surface thereof, so that it is covered with the SiO ₂ protective film 42. B + ions are not implanted into the W protective film 40 (FIG. 5).
(See (b)).

Then, Si ₃ N ₄ having a total thickness of 300 nm is formed.
A (silicon nitride) interlayer insulating film 44 is deposited. And using dry etching, Al gate electrode 16a above the Si ₃ N ₄ layer insulation film 44 and Si on the source region 20 and drain region 22 ₃ N ₄ layer insulation film 44 and the thickness of 2
Selective etching removal up to about 50 nm, and HF
Of the remaining Si ₃ N ₄ interlayer insulating film 44 and the SiO ₂ protective film 4 above the Al gate electrode 16a by using a system etching solution.
And 2 are selectively removed by etching. Thus, the W protective film 40 and the source region 20 on the Al gate electrode 16a are formed.
And contact windows 28 on the drain region 22, respectively.
The openings 30 and 32 are opened (see FIG. 5C).

The annealing treatment performed after the opening of the contact windows 28, 30, 32 in the first to fourth embodiments becomes unnecessary due to the effect of the impurity ion implantation in the heated state. Next, although not shown, the Al gate electrode 16a is formed through the W protective film 40 in the contact window 28.
And an Al wiring layer connected to the source region 20 and the drain region 22 through the contact windows 30 and 32, respectively.

As described above, according to the fifth embodiment, by covering the upper surface of the Al gate electrode 16a with the W protective film 40 and the SiO ₂ protective film 42, the transparent substrate 10 is exposed to the temperature 2 ° C.
When B + ions are introduced into the poly-Si semiconductor layer 12 while being heated to 00 ° C. to form the source region 20 and the drain region 22, the SiO ₂ protective film 42 serves as a barrier and B + to the W protective film 40 is increased. Since the ion implantation is prevented, it is possible to prevent the HF resistance of the W protective film 40 from being deteriorated.

Therefore, as in the case of the first embodiment, when the contact window 28 is opened on the W protective film 40 by the selective etching using the HF-based etching solution,
The HF-based etching solution can be prevented from penetrating into the Al gate electrode 16a or the gate SiO ₂ film 14 and penetrating therethrough. Therefore, the gate SiO ₂ film 14 under the Al gate electrode 16a can be protected from etching damage by the HF-based etching solution, the characteristic deterioration of the poly Si-TFT can be prevented, and the manufacturing yield thereof can be improved.

Further, by introducing the B + ions while the transparent substrate 10 is heated to a temperature of 200 ° C., the annealing process for activating the impurity ions becomes unnecessary, so that the process can be simplified and It is possible to reduce the temperature of the entire process. Next, a method of manufacturing an a-Si (amorphous silicon) -TFT according to a sixth embodiment of the present invention will be described with reference to the process chart of FIG. Incidentally, the T in FIG.
The same components as those of the FT are designated by the same reference numerals and the description thereof will be omitted.

In the sixth embodiment, the poly-Si semiconductor layer 12 is used as the semiconductor layer forming the element region in the fifth embodiment, whereas the a-Si semiconductor layer is used.
The feature is that the Al gate electrode 16a is used as the gate electrode, whereas the gate electrode made of Al-Si (silicon-added aluminum) is used. A 100 nm-thick a film is formed on the transparent substrate 10 by the LPCVD method.
After forming the —Si semiconductor layer 46, patterning is performed in the shape of the element region. Then, a LPCVD method is used to form a 100 nm thick gate SiO ₂ film 14 on the entire surface, and a 400 nm thick Al—Si film 48 and a resist film are formed on the gate SiO ₂ film 14 by sputtering. 20 nm thick Mo (molybdenum) protective film 5 having HF property and conductivity
0 is formed in order, and a thickness of 100 is formed on the Mo protective film 50.
A Si ₃ N ₄ protective film 52 having a thickness of nm is formed.

Then, the Si ₃ N ₄ protective film 52, Mo
The protective film 50, the Al—Si film 48, and the gate SiO ₂ film 14 are patterned into the shape of a gate electrode, and the upper surface of the Al—Si film is covered with the stacked Mo protective film 50 and Si ₃ N ₄ protective film 52. The gate electrode 48a is a gate Si
It is formed on the O ₂ film 14 (see FIG. 6A). Then
With the transparent substrate 10 heated to a temperature of 150 ° C.,
Using an ion doping method, by introducing P + ions in the a-Si semiconductor layer 46 a Si ₃ N ₄ protective film 52 as a mask to form a source region 20 and drain region 22.
At the same time, a channel region 24 sandwiched between the source region 20 and the drain region 22 is formed.

The ion doping method at this time is P
Acceleration energy of 30k using H ₃ (phosphine) gas
It was performed under the ion implantation conditions of eV and a dose amount of 1 × 10 ¹⁶ cm ⁻² . Therefore, the peak position of the ions injected into the Si ₃ N ₄ protective film 52 and the a-Si semiconductor layer 46 is 20 nm to 30 nm from the surface due to the range of the P + ions, so that the Si ₃ N ₄ protection is performed. P + ions are not implanted into the Mo protective film 50 covered with the film 52 (see FIG. 6B).

Then, a SiO ₂ interlayer insulating film 54 having a total thickness of 400 nm is deposited. Then, using an HF-based etching solution, the SiO ₂ interlayer insulating film 54, the Si ₃ N ₄ protective film 52, and the source region 2 above the Al-Si gate electrode 48a.
0 and the SiO ₂ interlayer insulating film 54 on the drain region 22 are selectively removed by etching to remove the Al--Si gate electrode 4
Contact windows 28, 30, 3 on the Mo protective film 50 on 8a and on the source region 20 and the drain region 22, respectively.
2 is opened (see FIG. 6 (c)).

Next, although not shown, the contact window 2
Al-Si gate electrode 4 via Mo protective film 50 in 8
An Al wiring layer connected to 8a is formed, and an Al wiring layer connected to the source region 20 and the drain region 22 through the contact windows 30 and 32 is formed. Thus, according to the sixth embodiment, the Al--Si gate electrode 4
By covering the upper surface of 8a with the Mo protective film 50 and the Si ₃ N ₄ protective film 52, P + ions are introduced into the a-Si semiconductor layer 46 while the transparent substrate 10 is heated to a temperature of 150 ° C. to form the source region. When the 20 and the drain region 22 are formed, the Si ₃ N ₄ protective film 52 serves as a barrier to prevent the implantation of P + ions into the Mo protective film 50, so that the HF resistance of the Mo protective film 50 deteriorates. Can be prevented. Therefore, the same effect as in the case of the fifth embodiment can be obtained.

Next, the MIS according to the seventh embodiment of the present invention.
A method of manufacturing the type transistor will be described with reference to the process chart of FIG. The same components as those of the TFT shown in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In the seventh embodiment, the transparent substrate 10 used in the first to fifth embodiments is used.
In contrast to the FT manufacturing method, M using a semiconductor substrate is used.
It is characterized in that it is a method for manufacturing an IS type transistor.

LPCVD method is used on the Si substrate 56.
Gate SiO of 100 nm thickness₂Forming a film 14,
This gate SiO₂On the film 14, using the sputtering method,
400 nm thick Al-Si film 48 and HF resistance and conductivity
20 nm thick Mo protective film 50 having electrical conductivity is sequentially formed
Further, on the Mo protective film 50, Si with a thickness of 50 nm is formed.₃N
_FourThe protective film 52 is formed.

Then, these Si ₃ N ₄ protective film 52, Mo
The protective film 50, the Al—Si film 48, and the gate SiO ₂ film 14 are patterned into the shape of a gate electrode, and the upper surface of the Al—Si film is covered with the stacked Mo protective film 50 and Si ₃ N ₄ protective film 52. The gate electrode 48a is a gate Si
It is formed on the O ₂ film 14 (see FIG. 7A). Then
With the Si substrate 56 heated to a temperature of 200 ° C.,
Using the ion shower method, P + ions are introduced into the surface of the Si substrate 56 using the Si ₃ N ₄ protective film 52 as a mask to form the source region 58 and the drain region 60. at the same time,
A channel region 62 sandwiched between the source region 58 and the drain region 60 is formed.

The ion doping method at this time is P
Using H ₃ gas, the acceleration energy was 30 keV, and the dose was 1 × 10 ¹⁶ cm ^{-2 under} the conditions of ion implantation. Therefore, as in the case of the sixth embodiment, Si ₃ N _{4 is used.}
P + is added to the Mo protective film 50 covered with the protective film 52.
Ions are not implanted (see FIG. 7B). Then, a Si ₃ N ₄ interlayer insulating film 44 having a total thickness of 300 nm is formed.
Deposit. Then, using an HF-based etching solution, Al
-Si ₃ N ₄ interlayer insulating film 4 above the Si gate electrode 48a
4 and the Si ₃ N ₄ protective film 52 and the Si ₃ N ₄ interlayer insulating film 44 on the source region 58 and the drain region 60 are selectively removed by etching, and the Mo protective film 50 and the source on the Al-Si gate electrode 48a and the source. Contact windows 28, 30, and 32 are opened on the region 58 and the drain region 60, respectively (see FIG. 7C).

Next, although not shown, the contact window 2
Al-Si gate electrode 4 via Mo protective film 50 in 8
An Al wiring layer connected to 8a is formed, and an Al wiring layer connected to the source region 58 and the drain region 60 through the contact windows 30 and 32 is formed. Thus, according to the seventh embodiment, the Al--Si gate electrode 4
8a upper surface, Mo protective film 50 and Si ₃ N ₄ protective film 52
By covering the Si substrate 56 with a temperature of 200 ° C.
Source region 5 by introducing P + ions while being heated to
8 and the drain region 60, the Si ₃ N ₄ protective film 52 serves as a barrier to prevent the implantation of P + ions into the Mo protective film 50, so that the HF resistance of the Mo protective film 50 deteriorates. Can be prevented. Therefore, the same effect as in the case of the sixth embodiment can be obtained.

In the above first to seventh embodiments,
The TiN protective film 18 and the W protective film 3 are used as protective films having HF resistance and conductivity that cover at least the upper surface of the gate electrode.
4, 36a, 40 or the Mo protective film 50 is used, the material is not limited to these materials, and may be, for example, Ta.
You may use (tantalum), Cr (chromium), etc. Further, as the gate electrode, the Al gate electrode 16a or Al
Although the -Si gate electrode 48a is used, the present invention is not limited to these materials and the present invention is applied to a gate electrode using a low resistance metal having no HF resistance such as Ti (titanium). can do.

In addition, in the fourth embodiment, when introducing predetermined impurity ions into the poly-Si semiconductor layer 12,
Although the ion shower method is used in which the transparent substrate 10 is not heated and then the annealing process is performed, the impurity ion implantation method by heating the transparent substrate 10 is used as in the case of the fifth to seventh embodiments. Good. Further, the heating temperature of the transparent substrate 10 or the Si substrate 56 in the fifth to seventh examples is 150 ° C. to 200 ° C.
It may be set in the range of 0 ° C to 300 ° C.

Further, in the above fifth to seventh embodiments, as a method of adding impurities while the substrate is heated, an ion doping method or an ion shower method of implanting ions without mass separation of impurities is used. Although used, it is also possible to use an ion implantation method in which ions with mass separation of impurities are implanted while the substrate is heated.

[0067]

As described above, according to the present invention, the hydrofluoric acid resistance and the conductivity of the gate electrode are improved before the contact window is opened in the interlayer insulating film on the gate electrode by using the hydrofluoric acid type etching solution. By forming the first protective film having the above structure, the hydrofluoric acid resistance of the gate electrode can be strengthened, so that the gate insulating film can be prevented from being destroyed by the hydrofluoric acid-based etching solution. Therefore, it is possible to improve the manufacturing yield of the semiconductor device.

Further, by forming the second protective film as a barrier against the addition of impurities on the first protective film having HF resistance and conductivity, the first protective film can be formed even in the impurity ion implantation step. Since the impurity ions are not implanted and the HF resistance of the first protective film is not deteriorated, it is possible to adopt a method of implanting the impurity ions while the semiconductor substrate or the insulating substrate is heated. Annealing process is unnecessary. Therefore, the first protective film can prevent the HF-based etching solution from penetrating into the gate electrode, prevent the gate insulating film from being destroyed, and contribute to lowering the temperature of the manufacturing process of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a poly-Si-TFT according to a first embodiment of the present invention.
FIG. 6A is a process view for explaining the manufacturing method of.

FIG. 2 is a poly-Si-TFT according to a second embodiment of the present invention.
FIG. 6A is a process view for explaining the manufacturing method of.

FIG. 3 is a poly Si-TFT according to a third embodiment of the present invention.
FIG. 6A is a process view for explaining the manufacturing method of.

FIG. 4 is a poly-Si-TFT according to a fourth embodiment of the present invention.
FIG. 6A is a process view for explaining the manufacturing method of.

FIG. 5 is a poly-Si-TFT according to a fifth embodiment of the present invention.
FIG. 6A is a process view for explaining the manufacturing method of.

FIG. 6 is an a-Si-TFT according to a sixth embodiment of the present invention.
FIG. 6A is a process view for explaining the manufacturing method of.

FIG. 7 is a process drawing for explaining a manufacturing method of a MIS transistor according to a seventh embodiment of the present invention.

FIG. 8 is a process chart for explaining a conventional method for manufacturing a poly-Si-TFT.

[Explanation of symbols]

10 ... Transparent substrate 12 ... Poly Si semiconductor layer 14 ... Gate SiO ₂ film 16 ... Al film 16a ... Al gate electrode 18, 38 ... TiN protective film 20, 58 ... Source region 22, 60 ... Drain region 24, 62 ... Channel region 26 ... PSG interlayer insulating film 28, 30, 32 ... contact window 34,36a, 36b, 36c, 40 ... W protective film 38 ... TiN protective film 42 ... SiO ₂ protective film 44 ... Si ₃ N ₄ insulating interlayer 46 ... a -Si semiconductor layer 48a ... Al-Si gate electrode 50 ... Mo protective film 52 ... Si ₃ N ₄ protective film 54 ... SiO ₂ interlayer insulating film 56 ... Si substrate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Uematsu 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (10)

[Claims] 1. A semiconductor layer on a semiconductor substrate or an insulating substrate, a source region and a drain region formed by adding impurities to the surface of the semiconductor substrate or the semiconductor layer, and a semiconductor layer sandwiched between the source region and the drain region. A gate electrode formed on the formed channel region via a gate insulating film, an interlayer insulating film formed on the entire surface, and a wiring layer connected to the gate electrode via a contact window opened in the interlayer insulating film. A method of manufacturing a semiconductor device having: a step of forming a first protective film having hydrofluoric acid resistance and conductivity between the gate electrode and the interlayer insulating film; A step of selectively etching and removing the contact window with a liquid to open the contact window on the first protective film; and the gate through the first protective film in the contact window. And a step of forming the wiring layer connected to the gate electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film and the gate electrode film are sequentially deposited on the semiconductor substrate or the semiconductor layer, and then the fluorine-resistant film is formed on the gate electrode film. A first step of forming the first protective film having acidity and conductivity; patterning the first protective film and the gate electrode film into a predetermined shape; A second step of forming the covered gate electrode; and using the first protective film and the gate electrode as a mask, adding a predetermined impurity to the semiconductor substrate surface or the semiconductor layer to form the source region and The third step of forming the drain region, and after the interlayer insulating film is deposited on the entire surface, the interlayer insulating film is selectively removed by etching using a hydrofluoric acid-based etching solution to perform the first protection. A fourth step of opening the contact window above; and a fifth step of forming the wiring layer connected to the gate electrode via the first protective film in the contact window. A method for manufacturing a characteristic semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film and the gate electrode film are sequentially deposited on the semiconductor substrate or the semiconductor layer, and then the gate electrode film is formed into a predetermined shape. Patterning to form the gate electrode, and a second step of selectively forming the first protective film having resistance to hydrofluoric acid and conductivity on the upper surface and the side surface of the gate electrode. And a third step of forming the source region and the drain region by adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer using the first protective film and the gate electrode as a mask, After depositing the interlayer insulating film on the entire surface, the interlayer insulating film is selectively removed by etching using a hydrofluoric acid-based etching solution, and the contact window is opened on the first protective film. Process and method of manufacturing a semiconductor device characterized by comprising a fifth step of forming the wiring layer connected to the gate electrode via the first protective film in the contact window. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film and the gate electrode film are sequentially deposited on the semiconductor substrate or the semiconductor layer, and then the gate electrode film is formed into a predetermined shape. Patterning to form the gate electrode, and using the gate electrode as a mask, adding a predetermined impurity to the semiconductor substrate surface or the semiconductor layer to form the source region and the drain region. And a second step of selectively forming the first protective film having resistance to hydrofluoric acid and conductivity on the upper surface and the side surface of the gate electrode and the upper surface or the upper surface and the side surface of the source region and the drain region. And the third step of depositing the interlayer insulating film on the entire surface, and then selectively removing the interlayer insulating film by etching with a hydrofluoric acid-based etching solution. A fourth step of opening the contact window on the first protective film on the electrode and opening contact windows on the first protective film on the source region and the drain region, respectively; Forming the wiring layer connected to the gate electrode via the first protective film in the window, and connecting to the source region and the drain region respectively via the first protective film in the contact window And a fifth step of forming a wiring layer for forming a semiconductor device. 5. A semiconductor layer on a semiconductor substrate or an insulating substrate, a source region and a drain region formed by adding impurities to the surface of the semiconductor substrate or the semiconductor layer, and a semiconductor layer sandwiched between the source region and the drain region. A gate electrode formed on the formed channel region via a gate insulating film, an interlayer insulating film formed on the entire surface, and a wiring layer connected to the gate electrode via a contact window opened in the interlayer insulating film. A method of manufacturing a semiconductor device having: a step of forming a first protective film having hydrofluoric acid resistance and conductivity between the gate insulating film and the gate electrode. Production method. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of selectively adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer is an ion doping method or an ion shower. A step of implanting ions of the predetermined impurity that have not been separated in mass by a method, and is accompanied by an annealing treatment for activating the impurity ions implanted into the semiconductor substrate surface or the semiconductor layer. Method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is made of single crystal silicon, polycrystalline silicon, or amorphous silicon, and the gate electrode is aluminum or silicon. A method of manufacturing a semiconductor device, wherein the first protective film is made of added aluminum or titanium, and the first protective film is made of molybdenum, tungsten, tantalum, chromium, or titanium nitride. 8. A semiconductor layer on a semiconductor substrate or an insulating substrate, a source region and a drain region formed by adding impurities to the surface of the semiconductor substrate or the semiconductor layer, and sandwiched between the source region and the drain region. A gate electrode formed on the formed channel region via a gate insulating film, an interlayer insulating film formed on the entire surface, and a wiring layer connected to the gate electrode via a contact window opened in the interlayer insulating film. A method of manufacturing a semiconductor device having: a step of forming a first protective film having hydrofluoric acid resistance and conductivity between the gate electrode and the interlayer insulating film, and on the first protective film, A step of forming a second protective film, and using the second protective film, the first protective film and the gate electrode as a mask, adding a predetermined impurity to the semiconductor substrate surface or the semiconductor layer Forming the source region and the drain region and using the second protective film as a barrier against impurity addition to prevent impurity addition to the first protective film; and the interlayer insulating film and the second insulating film. Selectively removing the protective film by using a hydrofluoric acid-based etching solution to open the contact window on the first protective film, and through the first protective film in the contact window. And a step of forming the wiring layer connected to the gate electrode. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the step of selectively adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer heats the semiconductor substrate or the insulating substrate. In the state, a step of implanting ions, in which the predetermined impurities are separated by mass, by an ion implantation method is a method for manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 5, wherein the step of selectively adding a predetermined impurity to the surface of the semiconductor substrate or the semiconductor layer heats the semiconductor substrate or the insulating substrate. In the state, a step of implanting ions of the predetermined impurity, which have not been separated in mass, by an ion doping method or an ion shower method.