JPH06132415A - Package for semiconductor-element housing - Google Patents

Package for semiconductor-element housing

Info

Publication number
JPH06132415A
JPH06132415A JP4282733A JP28273392A JPH06132415A JP H06132415 A JPH06132415 A JP H06132415A JP 4282733 A JP4282733 A JP 4282733A JP 28273392 A JP28273392 A JP 28273392A JP H06132415 A JPH06132415 A JP H06132415A
Authority
JP
Japan
Prior art keywords
insulating frame
semiconductor element
package
frame body
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4282733A
Other languages
Japanese (ja)
Other versions
JP2740602B2 (en
Inventor
Naohito Ide
尚人 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4282733A priority Critical patent/JP2740602B2/en
Publication of JPH06132415A publication Critical patent/JPH06132415A/en
Application granted granted Critical
Publication of JP2740602B2 publication Critical patent/JP2740602B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To completely airtightly seal a semiconductor element, to make the propagation loss of a signal extremely small and to operate the semiconductor element normally and stably for a long time by a method wherein an insulating frame body is attached and bonded horizontally and firmly to a heat-conductive base body provided with a protrusion part on the top surface. CONSTITUTION:A package for semiconductor-element housing use is formed by attaching and bonding an insulating frame body 2 to a heat-conductive base body 1 provided with a protrusion 1a, on which a semiconductor element 4 is mounted, on the surface, in such a way that the insulating frame body surrounds the protrusion part 1a. In the package, a cutout part is formed at the inner circumferential corner part on the rear surface of the insulating frame body 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.

【0002】[0002]

【従来の技術】近年、情報処理装置の高性能化、高速化
に伴い、それを構成する半導体素子も高密度、高集積化
が急激に進んでいる。そのため半導体素子は作動時に発
生する単位面積、単位体積あたりの発熱量が増大し、半
導体素子を正常、且つ安定に作動させるためにはその熱
をいかに効率的に除去するかが課題となっている。
2. Description of the Related Art In recent years, as the performance and speed of information processing devices have increased, the density and integration of the semiconductor elements constituting the information processing devices have rapidly increased. Therefore, the amount of heat generated per unit area and unit volume of the semiconductor element increases during operation, and how to efficiently remove the heat is a problem in order to operate the semiconductor element normally and stably. .

【0003】従来、半導体素子の発生する熱の除去方法
としては、図3及び図4に示すように上面中央部に半導
体素子20を載置する突起部21a を有する銅、銅ータング
ステン合金、窒化アルミニウム質焼結体等の熱伝導性材
料から成る基体21上に、前記突起部21a を囲繞するよう
にして絶縁枠体22をロウ付け取着した構造の半導体素子
収納用パッケージを準備し、基体21の突起部21a 上面に
半導体素子20を載置し半導体素子20から発生される熱を
基体21に吸収させるとともに該吸収した熱を大気中に放
出することによって行われている。
Conventionally, as a method of removing heat generated by a semiconductor element, copper, copper-tungsten alloy, nitride having a protrusion 21a for mounting the semiconductor element 20 on the center of the upper surface as shown in FIGS. 3 and 4 has been used. A semiconductor element storage package having a structure in which an insulating frame body 22 is brazed and attached so as to surround the protrusion 21a on a base body 21 made of a heat conductive material such as an aluminum sintered body is prepared. This is performed by mounting the semiconductor element 20 on the upper surface of the protruding portion 21a of 21 and causing the base 21 to absorb the heat generated from the semiconductor element 20 and radiating the absorbed heat into the atmosphere.

【0004】尚、前記突起部21a を有する基体21は、例
えば銅、銅ータングステン合金等から成る平板状基体21
の上面を研削加工し、中央に突起部21a を形成すること
によって製作されている。
The substrate 21 having the projections 21a is a flat substrate 21 made of, for example, copper, copper-tungsten alloy or the like.
It is manufactured by grinding the upper surface of and forming a protrusion 21a at the center.

【0005】また前記絶縁枠体22は上面にタングステ
ン、モリブデン、マンガン等から成るメタライズ配線層
23が形成されており、該メタライズ配線層23を介して内
部に収容する半導体素子20の各電極を外部の電気回路に
電気的に接続し得るように成っている。
The insulating frame 22 has a metallized wiring layer made of tungsten, molybdenum, manganese or the like on the upper surface.
23 is formed, and each electrode of the semiconductor element 20 housed inside can be electrically connected to an external electric circuit via the metallized wiring layer 23.

【0006】更に前記絶縁枠体22は下面に同じくタング
ステン、モリブデン、マンガン等から成るメタライズ金
属層24が形成されており、該メタライズ金属層24を基体
21に銀ロウ等のロウ材25を介しロウ付けすることによっ
て絶縁枠体22は基体21上に取着されている。
Further, a metallized metal layer 24 made of tungsten, molybdenum, manganese or the like is formed on the lower surface of the insulating frame 22, and the metallized metal layer 24 is used as a substrate.
The insulating frame body 22 is attached to the base 21 by brazing it to the 21 via a brazing material 25 such as silver brazing.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、熱伝導性
材料から成る基体21に設けた突起部21a が、該基体21を
研削加工することによって形成されており、突起部21a
の基部と基体21上面との間に円弧状の膨出部Aが形成さ
れてしまう。
However, in this conventional package for accommodating semiconductor elements, the protrusions 21a provided on the base 21 made of a thermally conductive material are formed by grinding the base 21. Cage, protrusion 21a
An arcuate bulge A is formed between the base of the base and the upper surface of the base 21.

【0008】そのためこの突起部21a を有する基体21上
に、該突起部21a を囲繞するようにして絶縁枠体22をロ
ウ付け取着した場合、絶縁枠体22の下面内周角部が前記
基体21の膨出部Aに引っ掛かって斜めとなり、絶縁枠体
22下面と基体21上面との間に間隔のばらつきが発生し、
その結果、基体21と絶縁枠体22とのロウ付け取着が不完
全になるとともに半導体素子収納用パッケージの気密封
止の信頼性が極めて低いものとなる欠点を有していた。
Therefore, when the insulating frame body 22 is brazed and attached on the base body 21 having the protruding portion 21a so as to surround the protruding portion 21a, the inner peripheral corner portion of the lower surface of the insulating frame body 22 is the base body. Insulation frame body
22 A gap between the lower surface and the upper surface of the base 21 occurs,
As a result, there are drawbacks that brazing and attachment of the base body 21 and the insulating frame body 22 becomes incomplete and the reliability of hermetic sealing of the semiconductor element housing package becomes extremely low.

【0009】また前記絶縁枠体22が膨出部Aに起因して
基体21上に斜めに取着されると半導体素子20の各電極を
絶縁枠体22のメタライズ配線層23にボンディングワイヤ
26を介して電気的に接続した際、ボンディングワイヤ26
の長さにばらつきが発生し、半導体素子が高周波帯域で
駆動する場合には、前記ボンディングワイヤ26の長さの
相違に伴う特性インピーダンスの不整合によって信号の
伝搬に大きな損失が発生するという欠点も有していた。
When the insulating frame 22 is obliquely attached to the base 21 due to the bulging portion A, the electrodes of the semiconductor element 20 are bonded to the metallized wiring layer 23 of the insulating frame 22 by bonding wires.
Bonding wire 26 when electrically connected through 26
When the semiconductor element is driven in a high frequency band, there is a drawback that a large loss occurs in signal propagation due to a mismatch in characteristic impedance due to a difference in length of the bonding wire 26. Had.

【0010】[0010]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は上面に突起部を有する熱伝導性基体に絶
縁枠体を水平、且つ強固に取着させることによって半導
体素子の気密封止を完全とするとともに信号の伝搬損失
を極小とし、半導体素子を長期間にわたり正常、且つ安
定に作動させることができる半導体素子収納用パッケー
ジを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object of the invention is to fix a semiconductor device by horizontally and firmly attaching an insulating frame to a heat conductive substrate having a projection on its upper surface. It is an object of the present invention to provide a package for housing a semiconductor element, which is capable of operating the semiconductor element normally and stably for a long period of time while achieving hermetic sealing and minimizing signal transmission loss.

【0011】[0011]

【課題を解決するための手段】本発明は上面に半導体素
子が載置される突起部を有する熱伝導性基体に、前記突
起部を囲繞するようにして絶縁枠体を取着してなる半導
体素子収納用パッケージであって、前記絶縁枠体の下面
内周角部に切欠部を形成したことを特徴とするものであ
る。
SUMMARY OF THE INVENTION The present invention is a semiconductor in which an insulating frame is attached to a heat conductive substrate having a projection on which a semiconductor element is mounted, so as to surround the projection. A package for storing an element, characterized in that a notch is formed at an inner peripheral corner of a lower surface of the insulating frame.

【0012】[0012]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 及び図2 は本発明の半導体素子収納用パッケー
ジの一実施例を示し、1 は基体、2 は絶縁枠体、3 は蓋
体である。
The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a semiconductor element housing package of the present invention, in which 1 is a base, 2 is an insulating frame, and 3 is a lid.

【0013】前記基体1 はその上面中央部に半導体素子
4 が載置される凸状の突起部1aが設けてあり、該突起部
1a上には半導体素子4 が接着剤を介し取着される。
The base 1 has a semiconductor element on the center of its upper surface.
4 is provided with a convex projection 1a on which the projection 4a is placed.
The semiconductor element 4 is attached onto the 1a via an adhesive.

【0014】前記基体1 は良熱伝導性である銅、銅ータ
ングステン合金等の金属から成り、該銅、銅ータングス
テン合金等はその熱伝導率が200W/m・K 以上と高く、熱
を伝導し易いため基体1 の突起部1a上に半導体素子4 を
載置した場合、基体1 は半導体素子4 が発生する熱を吸
収するとともに該吸収した熱を大気中に良好に放出させ
ることができ、その結果、半導体素子4 を常に低温とな
し、半導体素子4 を長期間にわたり正常、且つ安定に作
動させるこができる。
The base 1 is made of a metal having good thermal conductivity such as copper or a copper-tungsten alloy. The copper, the copper-tungsten alloy, etc. have a high thermal conductivity of 200 W / m · K or more, and heat When the semiconductor element 4 is placed on the protruding portion 1a of the base 1 because it is easily conducted, the base 1 can absorb the heat generated by the semiconductor element 4 and can satisfactorily release the absorbed heat to the atmosphere. As a result, the semiconductor element 4 can always be kept at a low temperature, and the semiconductor element 4 can be normally and stably operated for a long period of time.

【0015】尚, 前記基体1 は例えば、銅ータングステ
ン合金から成る場合、タングステンの粉末( 粒径: 約10
μm)を1000Kg/cm 2 の圧力で加圧成形するとともにこれ
を還元雰囲気中、約2300℃の温度で焼成して多孔質のタ
ングステン焼結体を得、次に1100℃の温度で加熱溶融さ
せた銅を前記タングステン焼結体の多孔部分に毛管現象
を利用し含浸させることによって製作される。
When the substrate 1 is made of, for example, a copper-tungsten alloy, tungsten powder (particle size: about 10
(μm) at a pressure of 1000 Kg / cm 2 and is pressed at a temperature of about 2300 ° C. in a reducing atmosphere to obtain a porous tungsten sintered body, which is then heated and melted at a temperature of 1100 ° C. Copper is impregnated into the porous portion of the tungsten sintered body by utilizing the capillarity.

【0016】また前記基体1 の上面中央部に設けられる
突起部1aは、基体1 となる銅、銅ータングステン合金等
から成る板状体の上面に従来周知の研削加工を施すこと
によって基体1 の上面に所定形状に形成される。
The protrusion 1a provided in the central portion of the upper surface of the base 1 is formed by subjecting the upper surface of a plate made of copper, copper-tungsten alloy or the like, which is the base 1, to the conventional grinding process. The upper surface is formed into a predetermined shape.

【0017】前記上面に突起部1aを有する基体1 はまた
その上面に突起部1aを囲繞するようにして絶縁枠体2 が
取着されている。
The base 1 having the projection 1a on the upper surface is also attached with the insulating frame 2 so as to surround the projection 1a on the upper surface.

【0018】前記絶縁枠体2 は後述の半導体素子4 の各
電極を外部電気回路に接続するメタライズ配線層5 を支
持するための支持部材として作用し、酸化アルミニウム
質焼結体等の電気絶縁材料で形成されている。
The insulating frame 2 acts as a supporting member for supporting the metallized wiring layer 5 connecting each electrode of the semiconductor element 4 described later to an external electric circuit, and is made of an electrically insulating material such as an aluminum oxide sintered body. Is formed by.

【0019】尚、前記絶縁枠体2 は酸化アルミニウム質
焼結体から成る場合、例えばアルミナ、シリカ、カルシ
ア、マグネシア等の原料粉末に適当な有機溶剤、溶媒を
添加混合して泥漿状となすとともにこれをドクターブレ
ード法やカレンダーロール法を採用することによってセ
ラミックグリーンシート( セラミック生シート) を形成
し、しかる後、前記セラミックグリーンシートに適当な
打ち抜き加工を施すとともに必要に応じ複数枚積層し、
高温で焼成することによって製作される。
When the insulating frame 2 is made of an aluminum oxide sintered body, for example, alumina, silica, calcia, magnesia, and the like are mixed with a suitable organic solvent and a solvent to form a slurry. A ceramic green sheet (ceramic green sheet) is formed by adopting a doctor blade method or a calendar roll method for this, and thereafter, appropriate punching processing is performed on the ceramic green sheet and a plurality of layers are laminated if necessary,
It is manufactured by firing at high temperature.

【0020】また前記絶縁枠体2 はその下面にタングス
テン、モリブデン、マンガン等の高融点金属粉末から成
るメタライズ金属層6 が被着形成されており、該メタラ
イズ金属層6 を基体1 に銀ロウ等のロウ材7 を介しロウ
付けすることによって絶縁枠体2 は基体1 上に取着され
ることとなる。
On the lower surface of the insulating frame body 2, a metallized metal layer 6 made of a refractory metal powder such as tungsten, molybdenum, manganese, etc. is adhered and formed. The insulating frame body 2 is attached to the base body 1 by brazing with the brazing material 7.

【0021】更に前記絶縁枠体2 は下面内周角部に切欠
部Bが設けてあり、該切欠部Bは基体1 上に絶縁枠体2
を取着する際、絶縁枠体2 の下面内周角部Bが基体1 の
上面と突起部1aの基部との間に形成される膨出部に引っ
掛かって斜めとなるのを有効に防止する作用を為し、こ
れによって絶縁枠体2 は基体1 上に水平に取着されるこ
ととなる。この場合、絶縁枠体2 は、該絶縁枠体2 の下
面内周角部に形成された切欠部Bによって基体1上に水
平に取着されることから基体1上面と絶縁枠体2下面と
は密接し、その結果、基体1と絶縁枠体2との接合強度
が強固になるとともに接合部における気密不良の発生が
皆無となる。
Further, the insulating frame 2 is provided with a cutout portion B at an inner peripheral corner portion of the lower surface, and the cutout portion B is provided on the base body 1 with the insulating frame body 2.
When attaching, it is effectively prevented that the inner peripheral corner portion B of the lower surface of the insulating frame body 2 is caught by the bulging portion formed between the upper surface of the base body 1 and the base portion of the protrusion 1a and becomes oblique. This has the effect that the insulating frame body 2 is horizontally attached to the base body 1. In this case, since the insulating frame body 2 is horizontally attached on the base body 1 by the notch B formed in the inner peripheral corner portion of the lower surface of the insulating frame body 2, the upper surface of the base body 1 and the lower surface of the insulating frame body 2 are Are in close contact with each other, and as a result, the bonding strength between the base body 1 and the insulating frame 2 is strengthened, and the occurrence of airtightness in the bonded portion is eliminated.

【0022】前記絶縁枠体2 に形成する切欠部Bは、例
えば絶縁枠体2となるセラミックグリーンシートの下面
内周角部に位置する部位を予めカッター等で切除してお
くことによって絶縁枠体2 の下面内周角部に形成され
る。
The cutout portion B formed in the insulating frame body 2 is formed, for example, by cutting a portion located at an inner peripheral corner portion of the lower surface of the ceramic green sheet to be the insulating frame body 2 in advance with a cutter or the like. 2 is formed on the inner peripheral corner of the lower surface.

【0023】また前記絶縁枠体2 はその上面に複数個の
メタライズ配線層5 が被着形成されており、該メタライ
ズ配線層5 の一端には半導体素子4 の各電極がボンディ
ングワイヤ8 を介して電気的に接続され、また他端には
外部電気回路に電気的に接続される外部リード端子9 が
ロウ付けされる。
Further, a plurality of metallized wiring layers 5 are adhered and formed on the upper surface of the insulating frame 2, and each electrode of the semiconductor element 4 is bonded to one end of the metallized wiring layer 5 via a bonding wire 8. An external lead terminal 9 electrically connected to the other end and electrically connected to an external electric circuit is brazed.

【0024】尚、前記絶縁枠体2 上面のメタライズ配線
層5 と半導体素子4 の各電極とをボンディングワイヤ8
を介して電気的に接続した場合、絶縁枠体2 は基体1 上
に水平に取着されていることから半導体素子4 の各電極
と各メタライズ配線層5 との間隔が均一となり、その結
果、各ボンディングワイヤ8 の長さを均等としてボンデ
ィングワイヤ8 とメタライズ配線層5 から成る配線の特
性インピーダンスを全て整合させることができ信号の伝
搬に大きな損失を与えるのが皆無となる。
The metallized wiring layer 5 on the upper surface of the insulating frame 2 and each electrode of the semiconductor element 4 are bonded with a bonding wire 8
When electrically connected via, the insulating frame body 2 is horizontally attached to the base body 1, so that the distance between each electrode of the semiconductor element 4 and each metallized wiring layer 5 becomes uniform, and as a result, By making the lengths of the bonding wires 8 uniform, the characteristic impedances of the wirings composed of the bonding wires 8 and the metallized wiring layer 5 can all be matched, and there will be no significant loss in signal propagation.

【0025】また前記メタライズ配線層5 は半導体素子
4 の各電極を外部リード端子9 に接続する作用を為し、
該メタライズ配線層5 はタングステン、モリブデン、マ
ンガン等の高融点金属粉末から成り、タングステン等の
高融点金属粉末に適当な有機溶剤、溶媒を添加混合して
得た金属ペーストを絶縁枠体2 となるセラミックグリー
ンシートに予め従来周知のスクリーン印刷法等を採用し
所定パターンに印刷塗布しておくことによって絶縁枠体
2 の上面に被着形成される。
The metallized wiring layer 5 is a semiconductor device.
It connects each electrode of 4 to the external lead terminal 9,
The metallized wiring layer 5 is made of a refractory metal powder such as tungsten, molybdenum, manganese, etc. The refractory metal powder such as tungsten is mixed with a suitable organic solvent and a solvent to obtain a metal paste, which becomes the insulating frame 2. Insulation frame is formed by applying the well-known screen printing method to the ceramic green sheet in advance and printing and applying it in a predetermined pattern.
It is deposited on the upper surface of 2.

【0026】更に前記メタライズ配線層5 の一端には外
部リード端子9 が銀ロウ等のロウ材を介してロウ付け取
着されており、該外部リード端子9 は内部に収容する半
導体素子4 の各電極を外部電気回路に電気的に接続する
作用を為し、コバール金属(鉄ーニッケルーコバルト合
金) や42アロイ( 鉄ーニッケル合金) 等の金属材料によ
り形成されている。
Further, an external lead terminal 9 is brazed and attached to one end of the metallized wiring layer 5 via a brazing material such as silver brazing, and the external lead terminal 9 is attached to each of the semiconductor elements 4 housed inside. It functions to electrically connect the electrodes to an external electric circuit and is made of a metal material such as Kovar metal (iron-nickel-cobalt alloy) or 42 alloy (iron-nickel alloy).

【0027】前記外部リード端子9 は、例えばコバール
金属等のインゴット( 塊) を従来周知の圧延加工法や打
ち抜き加工法等、従来周知の金属加工法を採用すること
によって所定の板状に形成される。
The external lead terminal 9 is formed in a predetermined plate shape by adopting a conventionally known metal processing method such as a conventionally known rolling processing method or a punching processing method for an ingot (lump) of Kovar metal or the like. It

【0028】尚、前記外部リード端子9 はその露出する
表面にニッケル、金等の耐蝕性に優れ、良導電性でる金
属をメッキ法により1.0 乃至20.0μm の厚みに層着させ
ておくと外部リード端子9 の酸化腐食を有効に防止する
ことができるとともに外部リード端子9 と外部電気回路
との電気的接続を良好となすことができる。従って、前
記外部リード端子9 の露出する表面にはニッケル、金等
を1.0 乃至20.0μm の厚みに層着させておくことが好ま
しい。
The external lead terminals 9 are formed by depositing a metal having good corrosion resistance such as nickel and gold on the exposed surface thereof and having good conductivity and having a thickness of 1.0 to 20.0 μm by a plating method. Oxidation and corrosion of the terminal 9 can be effectively prevented, and good electrical connection between the external lead terminal 9 and the external electric circuit can be achieved. Therefore, it is preferable that nickel, gold or the like is layered on the exposed surface of the external lead terminal 9 in a thickness of 1.0 to 20.0 μm.

【0029】かくして本発明の半導体素子収納用パッケ
ージによれば、基体1 の突起部1a上に半導体素子4 を載
置固定するとともに半導体素子4 の各電極をボンディン
グワイヤ8 を介して絶縁枠体2 のメタライズ配線層5 に
接続し、しかる後、基体1 上の絶縁枠体2 に蓋体3 をガ
ラス、樹脂等から成る封止材を介して接合させ、基体1
、絶縁枠体2 及び蓋体3 から成る容器内部に半導体素
子4 を気密に封止することによって製品としての半導体
装置が完成する。
Thus, according to the package for accommodating semiconductor elements of the present invention, the semiconductor element 4 is mounted and fixed on the protruding portion 1a of the base body 1, and each electrode of the semiconductor element 4 is bonded via the bonding wire 8 to the insulating frame 2 To the metallized wiring layer 5 of the substrate 1. Then, the lid 3 is joined to the insulating frame 2 on the substrate 1 via a sealing material made of glass, resin, etc.
The semiconductor device as a product is completed by hermetically sealing the semiconductor element 4 inside the container including the insulating frame 2 and the lid 3.

【0030】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例では基体1
を銅や銅ータングステン合金等の金属材料で形成した
が、窒化アルミニウム質焼結体等の熱伝導率が150W/m・
K 以上の無機物で形成してもよい。この場合、基体1 と
絶縁枠体2 との取着は、基体1 の上面に予めタングステ
ンやモリブデン等の金属粉末から成るメタライズ金属層
を被着形成させておき、該メタライズ金属層と絶縁枠体
2 下面のメタライズ金属層6 とを銀ロウ等のロウ材7 を
介しロウ付けすることによって行われる。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiments, the base 1
Was formed of a metal material such as copper or a copper-tungsten alloy, but the thermal conductivity of an aluminum nitride sintered body was 150 W / m
It may be formed of an inorganic material of K or more. In this case, the base body 1 and the insulating frame body 2 are attached to each other by depositing a metallized metal layer made of a metal powder such as tungsten or molybdenum on the upper surface of the base body 1 in advance.
2 This is performed by brazing the metallized metal layer 6 on the lower surface with a brazing material 7 such as silver brazing.

【0031】[0031]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、絶縁枠体の下面内周角部に切欠部を形成したこ
とから上面に突起部を有する熱伝導性基体上に、該突起
部を囲繞するようにして絶縁枠体を取着する際、絶縁枠
体の下面内周角部が基体の上面と突起部の基部との間に
形成されている膨出部に引っ掛かって斜めとなることは
なく、その結果、絶縁枠体は熱伝導性基体に水平に密着
し、基体と絶縁枠体との接合強度が極めて強固になると
ともに接合部における気密不良の発生が皆無となる。
According to the package for accommodating semiconductor elements of the present invention, since the notch is formed at the inner peripheral corner of the lower surface of the insulating frame, the projecting portion is formed on the heat conductive substrate having the projecting portion on the upper surface. When the insulating frame is mounted so as to surround the base, the inner peripheral corners of the lower surface of the insulating frame become slanted by being caught by the bulging portion formed between the upper surface of the base and the base of the protrusion. As a result, the insulating frame horizontally adheres to the thermally conductive substrate, the bonding strength between the substrate and the insulating frame becomes extremely strong, and no airtightness occurs at the bonded portion.

【0032】また絶縁枠体が熱伝導性基体上に水平に取
着されることから半導体素子の各電極と絶縁枠体上面に
被着形成した各メタライズ配線層とを電気的に接続する
ボンディングワイヤの長さが全て均等となり、その結
果、ボンディングワイヤとメタライズ配線層から成る配
線の特性インピーダンスを全て整合させることができ、
信号の伝搬に大きな損失を与えるのが皆無となる。
Further, since the insulating frame is horizontally attached on the heat conductive substrate, a bonding wire for electrically connecting each electrode of the semiconductor element and each metallized wiring layer formed on the upper surface of the insulating frame. The lengths of all are equal, and as a result, it is possible to match all the characteristic impedances of the wiring composed of the bonding wire and the metallized wiring layer,
There is no significant loss in signal propagation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【図2】図1に示すパッケージの要部拡大断面図であ
る。
FIG. 2 is an enlarged cross-sectional view of a main part of the package shown in FIG.

【図3】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 3 is a cross-sectional view of a conventional semiconductor element housing package.

【図4】図3 に示すパッケージの要部拡大断面図であ
る。
4 is an enlarged cross-sectional view of a main part of the package shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 1a・・・・突起部 2・・・・・絶縁枠体 3・・・・・蓋体 4・・・・・半導体素子 B・・・・・切欠部 1 ... Insulating substrate 1a ... Protrusions 2 ... Insulating frame 3 ... Lid 4 ... Semiconductor element B ... Notch

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】上面に半導体素子が載置される突起部を有
する熱伝導性基体に、前記突起部を囲繞するようにして
絶縁枠体を取着してなる半導体素子収納用パッケージで
あって、前記絶縁枠体の下面内周角部に切欠部を形成し
たことを特徴とする半導体素子収納用パッケージ。
1. A package for accommodating a semiconductor element, comprising a heat conductive base having a protrusion on which a semiconductor element is mounted, and an insulating frame body attached to the protrusion so as to surround the protrusion. A package for accommodating a semiconductor element, wherein a notch is formed at an inner peripheral corner of the lower surface of the insulating frame.
JP4282733A 1992-10-21 1992-10-21 Package for storing semiconductor elements Expired - Fee Related JP2740602B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4282733A JP2740602B2 (en) 1992-10-21 1992-10-21 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4282733A JP2740602B2 (en) 1992-10-21 1992-10-21 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH06132415A true JPH06132415A (en) 1994-05-13
JP2740602B2 JP2740602B2 (en) 1998-04-15

Family

ID=17656342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4282733A Expired - Fee Related JP2740602B2 (en) 1992-10-21 1992-10-21 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2740602B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629561A (en) * 1994-12-16 1997-05-13 Anam Industrial Co., Ltd. Semiconductor package with integral heat dissipator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629561A (en) * 1994-12-16 1997-05-13 Anam Industrial Co., Ltd. Semiconductor package with integral heat dissipator

Also Published As

Publication number Publication date
JP2740602B2 (en) 1998-04-15

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