JPH06132356A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06132356A
JPH06132356A JP28160892A JP28160892A JPH06132356A JP H06132356 A JPH06132356 A JP H06132356A JP 28160892 A JP28160892 A JP 28160892A JP 28160892 A JP28160892 A JP 28160892A JP H06132356 A JPH06132356 A JP H06132356A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor substrate
substrate
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP28160892A
Other languages
Japanese (ja)
Inventor
Muneo Hatta
宗生 八田
Takashi Kondo
隆 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP28160892A priority Critical patent/JPH06132356A/en
Publication of JPH06132356A publication Critical patent/JPH06132356A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To obtain a semiconductor device which is thin and excellent in heat dissipating properties and mounted with integrated circuits high in density. CONSTITUTION:A semiconductor substrate where an integrated circuit is formed is die-bonded to a heat dissipating fin 7. Input-output pins 5 are formed on one side of a multilayer ceramic board 2, and an anisotropic conductive rubber 8 is arranged between the other side of the ceramic board 2 and the integrated circuit. The anisotropic conductive rubber 8 electrically connects the integrated circuit to an inner wiring 4 provided inside the multilayer ceramic board 2. The inner wiring 4 provided inside the ceramic board 2 is electrically connected to the input-output pins 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置に関し、
特に、集積回路を高密度に実装することが可能となる半
導体装置の構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure of a semiconductor device that enables high density mounting of integrated circuits.

【0002】[0002]

【従来の技術】以下、図9および図10を用いて、従来
の半導体装置について説明する。図9および図10は、
従来の半導体装置を示す断面図である。まず図9を参照
して、多層セラミック基板22の一方の面には、外部と
の信号の入出力を行なう入出力ピン25が複数設けられ
ている。また、多層セラミック基板22の他方の面に
は、集積回路が形成された半導体基板21がダイボンド
されている。
2. Description of the Related Art A conventional semiconductor device will be described below with reference to FIGS. 9 and 10 show
It is sectional drawing which shows the conventional semiconductor device. First, referring to FIG. 9, one surface of multilayer ceramic substrate 22 is provided with a plurality of input / output pins 25 for inputting / outputting signals to / from the outside. The semiconductor substrate 21 having an integrated circuit formed thereon is die-bonded to the other surface of the multilayer ceramic substrate 22.

【0003】半導体基板21における集積回路は、多層
セラミック基板22に形成された内部配線24とワイヤ
23を介して電気的に接続されている。このワイヤ23
は、内部配線24を介して入出力ピン25に電気的に接
続されている。半導体基板21上には、この半導体基板
21を気密封止するための蓋26が多層セラミック基板
22に接合されており、この蓋26には、集積回路が発
生した熱を放散させるための放熱フィン27が接合され
ている。次に、図10を参照して、この図に示される半
導体装置は、複数個の半導体基板21が半導体装置内に
配置されている。そのため、多層基板22の厚みが図9
に示されるものよりもさらに厚くなっている。これ以外
の構造に関しては、上記の図9に示された半導体装置と
同様である。
The integrated circuit on the semiconductor substrate 21 is electrically connected to internal wirings 24 formed on the multilayer ceramic substrate 22 via wires 23. This wire 23
Are electrically connected to the input / output pins 25 via the internal wiring 24. A lid 26 for hermetically sealing the semiconductor substrate 21 is joined to the multilayer ceramic substrate 22 on the semiconductor substrate 21, and the lid 26 has a radiation fin for dissipating heat generated by the integrated circuit. 27 is joined. Next, referring to FIG. 10, in the semiconductor device shown in this figure, a plurality of semiconductor substrates 21 are arranged in the semiconductor device. Therefore, the thickness of the multilayer substrate 22 is as shown in FIG.
It is even thicker than that shown in. The structure other than this is similar to that of the semiconductor device shown in FIG.

【0004】次に、動作について説明する。半導体基板
21に形成された集積回路からの電気信号は、ワイヤ2
3および多層セラミック基板22の内部配線24を経由
して入出力ピン25に伝達される。そして、この入出力
ピン25から外部へ信号の伝達が行なわれることにな
る。一方、集積回路に入力される電気信号は、入出力ピ
ン25から内部配線24に伝達される。そして、この内
部配線24に電気的に接続されているワイヤ23を経て
集積回路に伝達されることになる。
Next, the operation will be described. The electric signal from the integrated circuit formed on the semiconductor substrate 21 is transmitted to the wire 2
3 and the internal wiring 24 of the multilayer ceramic substrate 22 to be transmitted to the input / output pin 25. Then, the signal is transmitted from the input / output pin 25 to the outside. On the other hand, the electric signal input to the integrated circuit is transmitted from the input / output pin 25 to the internal wiring 24. Then, it is transmitted to the integrated circuit through the wire 23 electrically connected to the internal wiring 24.

【0005】一方、蓋26は、多層セラミック基板22
と接合することによって、集積回路が形成された半導体
基板21を気密封止する。このとき、集積回路から発生
する熱は、蓋26に接合されている放熱フィン27によ
って空気中に放散されることになる。
On the other hand, the lid 26 is a multilayer ceramic substrate 22.
The semiconductor substrate 21 on which the integrated circuit is formed is hermetically sealed by being bonded to. At this time, the heat generated from the integrated circuit is dissipated into the air by the radiation fins 27 joined to the lid 26.

【0006】[0006]

【発明が解決しようとする課題】上記の従来の半導体装
置には、次に説明するような問題点があった。まず、図
9および図10に示されるように、従来の半導体装置に
おいては、半導体基板21はワイヤ23を介して多層セ
ラミック基板22に形成された配線層と電気的に接続さ
れていた。すなわち、多層セラミック基板22にワイヤ
ボンドの領域が必要になってくる。そのため、実装密度
を低下させるといった問題点が生じていた。
The conventional semiconductor device described above has the following problems. First, as shown in FIGS. 9 and 10, in the conventional semiconductor device, the semiconductor substrate 21 was electrically connected to the wiring layer formed on the multilayer ceramic substrate 22 via the wire 23. That is, a wire bond region is required in the multilayer ceramic substrate 22. Therefore, there has been a problem that the mounting density is lowered.

【0007】さらに、多層セラミック基板22に形成さ
れる配線層は、スクリーン印刷などによって形成される
ため、その平面的な配線層幅が広いものとなってしま
う。それにより、配線層密度が小さくなることになる。
そのため、多層セラミック基板22自体の厚みを厚くす
ることが必要となってくる。それにより、半導体装置自
体の大きさが大きくなるといった問題点も生じていた。
Further, since the wiring layer formed on the multilayer ceramic substrate 22 is formed by screen printing or the like, the width of the wiring layer in plan view becomes wide. This reduces the wiring layer density.
Therefore, it becomes necessary to increase the thickness of the multilayer ceramic substrate 22 itself. This causes a problem that the size of the semiconductor device itself becomes large.

【0008】さらに、半導体基板21は、多層セラミッ
ク基板22にダイボンドされているため、集積回路で発
生した熱は、放熱フィン27側よりも多層セラミック基
板22側に伝達されやすくなる。そのため、多層セラミ
ック基板22内に熱がこもり、放熱特性を劣化させると
いった問題点が生じていた。この放熱特性に関する問題
点は、多層セラミック基板22の厚みが厚くなった場合
さらに顕著なものとなってくる。
Furthermore, since the semiconductor substrate 21 is die-bonded to the multilayer ceramic substrate 22, heat generated in the integrated circuit is more easily transferred to the multilayer ceramic substrate 22 side than to the heat radiation fins 27 side. Therefore, there is a problem that heat is accumulated in the multilayer ceramic substrate 22 and heat dissipation characteristics are deteriorated. The problem regarding the heat dissipation characteristic becomes more remarkable when the thickness of the multilayer ceramic substrate 22 is increased.

【0009】この発明は、上記のような問題点を解決す
るためになされたものであり、集積回路を高密度で実装
でき、薄型でかつ放熱特性の良好な半導体装置を提供す
ることを目的とする。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device which is capable of mounting an integrated circuit at high density, is thin, and has excellent heat dissipation characteristics. To do.

【0010】[0010]

【課題を解決するための手段】この発明に基づく半導体
装置は、1つの局面では、複数の接続端子を有する集積
回路装置が形成された第1の半導体基板と、集積回路装
置の各接続端子と電気的に接続された複数の配線層が形
成され、第1の半導体基板を保持する第2の半導体基板
と、第2の半導体基板に取付けられ、集積回路装置に発
生する熱を放散させるための放熱フィンと、配線層の各
々と電気的に接続され外部との信号の入出力を行なう複
数個の入出力端子を有する絶縁基板とを備えている。
According to one aspect, a semiconductor device according to the present invention includes a first semiconductor substrate on which an integrated circuit device having a plurality of connection terminals is formed, and each connection terminal of the integrated circuit device. A plurality of electrically connected wiring layers are formed, and a second semiconductor substrate holding the first semiconductor substrate and a second semiconductor substrate are attached to dissipate heat generated in the integrated circuit device. A heat radiation fin and an insulating substrate having a plurality of input / output terminals electrically connected to each of the wiring layers and for inputting / outputting signals to / from the outside are provided.

【0011】この発明に基づく半導体装置は、他の局面
では、一方の面に複数個の第1電極を有する集積回路装
置が形成された半導体基板と、半導体基板の他方の面に
取付けられ、集積回路装置で発生した熱を放散するため
の放熱フィンと、一方の面に外部との信号の入出力を行
なう複数個の入出力端子が設けられ、他方の面に複数個
の第2電極が形成された絶縁基板と、絶縁層と、この絶
縁層を貫通し第1電極と第2電極とを電気的に接続する
複数個の導電層とを有し、集積回路装置と絶縁基板の他
方の面との間に配置された電極接合層とを備えている。
In another aspect of the semiconductor device according to the present invention, a semiconductor substrate having an integrated circuit device having a plurality of first electrodes formed on one surface thereof and an integrated circuit device mounted on the other surface of the semiconductor substrate are integrated. A radiating fin for dissipating heat generated in the circuit device, a plurality of input / output terminals for inputting / outputting signals to / from the outside are provided on one surface, and a plurality of second electrodes are formed on the other surface. An insulating substrate, an insulating layer, and a plurality of conductive layers that penetrate the insulating layer and electrically connect the first electrode and the second electrode, and the other surface of the integrated circuit device and the insulating substrate. And an electrode bonding layer disposed between and.

【0012】[0012]

【作用】この発明に基づく半導体装置は、1つの局面で
は、集積回路装置が形成された第1の半導体基板が第2
の半導体基板に保持され、集積回路装置の各接続端子と
電気的に接続される複数の配線層が第2の半導体基板に
形成されている。それにより、従来のようにセラミック
などからなる絶縁基板上に配線層を形成する場合に比べ
て、配線幅を著しく低減でき、配線層密度を大幅に向上
させることが可能となる。それにより、集積回路装置が
形成された第1の半導体基板の実装密度を向上させるこ
とが可能となる。また、第1の半導体基板は、放熱フィ
ン側に接合されている。それにより、集積回路に発生し
た熱が放熱フィンに伝達されやすくなる。それにより、
従来よりも格段に放熱特性を向上させることが可能とな
る。
According to one aspect of the semiconductor device according to the present invention, the first semiconductor substrate on which the integrated circuit device is formed is the second semiconductor substrate.
A plurality of wiring layers that are held on the semiconductor substrate and are electrically connected to the connection terminals of the integrated circuit device are formed on the second semiconductor substrate. As a result, the wiring width can be remarkably reduced, and the wiring layer density can be significantly improved, as compared with the conventional case where the wiring layer is formed on an insulating substrate made of ceramic or the like. This makes it possible to improve the packaging density of the first semiconductor substrate on which the integrated circuit device is formed. Further, the first semiconductor substrate is joined to the heat radiation fin side. Thereby, the heat generated in the integrated circuit is easily transferred to the heat radiation fins. Thereby,
It is possible to significantly improve the heat dissipation characteristics as compared with the conventional one.

【0013】この発明に基づく半導体装置によれば、他
の局面では、集積回路装置と絶縁基板との電気的な接続
を、電極接合層内に設けられた導電層によって行なって
いる。そのため、従来のようにワイヤの形成領域が必要
でなくなり、集積回路装置が形成された半導体基板の実
装密度を向上させることが可能となる。また、半導体基
板は、放熱フィン側にダイボンドされているため、放熱
フィンに効率よく熱が伝達され、放熱特性を向上させる
ことが可能となる。さらに、電極接合層にも集積回路装
置で発生した熱は伝達されることになる。それにより、
放熱フィンおよび電極接合層の両者によって、集積回路
装置から熱を奪うことが可能となる。それにより、さら
に放熱特性を向上させることが可能となる。
According to another aspect of the semiconductor device of the present invention, the integrated circuit device and the insulating substrate are electrically connected by the conductive layer provided in the electrode bonding layer. Therefore, unlike the conventional case, a wire formation region is not required, and it is possible to improve the packaging density of the semiconductor substrate on which the integrated circuit device is formed. Further, since the semiconductor substrate is die-bonded to the heat radiation fin side, heat is efficiently transferred to the heat radiation fins, and the heat radiation characteristics can be improved. Further, the heat generated in the integrated circuit device is also transferred to the electrode bonding layer. Thereby,
Both the radiation fin and the electrode bonding layer allow heat to be taken from the integrated circuit device. As a result, it becomes possible to further improve the heat dissipation characteristics.

【0014】[0014]

【実施例】以下、この発明に基づく実施例について、図
1〜図8を用いて説明する。図1は、この発明に基づく
第1の実施例における半導体装置を示す断面図である。
図1を参照して、多層セラミック基板2の一方の面に
は、外部との信号の入出力を行なう入出力ピン5が設け
られている。多層セラミック基板2には、内部配線4が
設けられており、この内部配線4は入出力ピン5に電気
的に接続されている。多層セラミック基板2の他方の面
には、電極接合層として機能する異方性導電ゴム8が配
置されている。
Embodiments of the present invention will be described below with reference to FIGS. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
Referring to FIG. 1, an input / output pin 5 for inputting / outputting a signal to / from the outside is provided on one surface of multilayer ceramic substrate 2. Internal wiring 4 is provided on the multilayer ceramic substrate 2, and the internal wiring 4 is electrically connected to the input / output pins 5. An anisotropic conductive rubber 8 that functions as an electrode bonding layer is arranged on the other surface of the multilayer ceramic substrate 2.

【0015】ここで、異方性導電ゴムとは、本明細書に
おいては、絶縁層を貫通する導電層を設けることによっ
て、導電層が設けられた部分のみに導電性を持たせたゴ
ムのことをいうと定義する。本実施例においては、異方
性導電ゴム8は、厚み方向(縦方向)にのみ導電性を有
し、横方向には絶縁性が保持されている。この異方性導
電ゴム8上には、集積回路が形成された半導体基板1が
配置されることになる。この半導体基板1は、放熱フィ
ン7にタイボンドされている。
The term "anisotropic conductive rubber" as used herein means a rubber in which a conductive layer is provided so as to penetrate the insulating layer so that only the portion where the conductive layer is provided has conductivity. Is defined as. In this embodiment, the anisotropic conductive rubber 8 has conductivity only in the thickness direction (longitudinal direction) and maintains the insulating property in the lateral direction. On this anisotropic conductive rubber 8, the semiconductor substrate 1 having an integrated circuit formed thereon is arranged. The semiconductor substrate 1 is tie-bonded to the radiation fin 7.

【0016】ここで、上記の異方性導電ゴム8の構造に
ついて、図4を用いてより詳しく説明する。図4は、半
導体基板1と多層セラミック基板2との接合部を部分拡
大した断面図である。図4を参照して、上記の異方性導
電ゴム8は、シリコーンなどのゴムからなる絶縁層15
と、金属線の細線などからなる導電層14との複合構造
となっている。そして、半導体基板1と多層セラミック
基板2との間に異方性導電ゴム8を挟み込むことによっ
て、半導体基板1に形成された電極12と多層セラミッ
ク基板2上に形成された電極13とを電気的に接続す
る。なお、電極接合層は、絶縁層と導電層との複合構造
であって、絶縁膜を導電層が部分的に貫通したものであ
ればよく、上記の異方性導電ゴム8に限られるものでは
ない。
The structure of the anisotropic conductive rubber 8 will be described in more detail with reference to FIG. FIG. 4 is a partially enlarged cross-sectional view of the joint between the semiconductor substrate 1 and the multilayer ceramic substrate 2. Referring to FIG. 4, the anisotropic conductive rubber 8 is an insulating layer 15 made of rubber such as silicone.
And a conductive layer 14 made of a thin metal wire or the like. Then, by sandwiching the anisotropic conductive rubber 8 between the semiconductor substrate 1 and the multilayer ceramic substrate 2, the electrode 12 formed on the semiconductor substrate 1 and the electrode 13 formed on the multilayer ceramic substrate 2 are electrically connected. Connect to. It should be noted that the electrode bonding layer has a composite structure of an insulating layer and a conductive layer as long as the conductive layer partially penetrates the insulating film, and is not limited to the anisotropic conductive rubber 8 described above. Absent.

【0017】以上のように、半導体基板1は異方性導電
ゴム8を介して多層セラミック基板2に電気的に接続す
ることができ、その際に半導体基板1の平面的な面積と
ほぼ等しい面積を有する異方性導電ゴム8を用いること
が可能となる。それにより、ボンディングワイヤ形成領
域を設ける必要がなくなる。それにより、半導体基板1
の実装密度を向上させることが可能となる。さらに、半
導体基板1は放熱フィン7側にダイボンドされているた
め、放熱フィン7から効率よく集積回路に生じた熱を放
散させることが可能となる。それにより、放熱特性を向
上させることが可能となる。
As described above, the semiconductor substrate 1 can be electrically connected to the multilayer ceramic substrate 2 through the anisotropic conductive rubber 8, and at that time, the area substantially equal to the planar area of the semiconductor substrate 1 is obtained. It is possible to use the anisotropic conductive rubber 8 having As a result, it is not necessary to provide a bonding wire formation region. Thereby, the semiconductor substrate 1
It is possible to improve the mounting density of. Further, since the semiconductor substrate 1 is die-bonded to the heat radiation fin 7 side, it is possible to efficiently dissipate the heat generated in the integrated circuit from the heat radiation fin 7. Thereby, it becomes possible to improve the heat dissipation characteristics.

【0018】上記の構造を有する半導体装置の製造方法
においては、半導体基板1が放熱フィン7側に接合され
るため、放熱フィン7はマーカに対して精度よくダイボ
ンドすることが可能となる。これによっても、実装密度
向上に寄与し得ることとなる。また、このようにして半
導体基板1を放熱フィン7にダイボンドし、多層セラミ
ック基板2のマーカと整合しながら、異方性導電ゴム8
を配置するとともに半導体基板1を気密封止する。
In the method of manufacturing a semiconductor device having the above structure, since the semiconductor substrate 1 is bonded to the radiation fin 7 side, the radiation fin 7 can be die-bonded to the marker with high accuracy. This can also contribute to the improvement of mounting density. In addition, the semiconductor substrate 1 is die-bonded to the radiation fins 7 in this manner, and the anisotropic conductive rubber 8 is aligned with the markers on the multilayer ceramic substrate 2.
And the semiconductor substrate 1 is hermetically sealed.

【0019】次に、上記の構造を有する半導体装置の動
作について説明する。まず、集積回路からの電気信号は
異方性導電ゴム8および多層セラミック基板2の内部配
線4を経由して入出力ピン5に伝達される。それによ
り、外部への信号の伝達が行なわれることになる。一
方、集積回路への電気信号の入力については、上記の経
路と逆の経路の辿って集積回路に外部からの電気信号が
伝達されることになる。
Next, the operation of the semiconductor device having the above structure will be described. First, an electric signal from the integrated circuit is transmitted to the input / output pin 5 via the anisotropic conductive rubber 8 and the internal wiring 4 of the multilayer ceramic substrate 2. As a result, the signal is transmitted to the outside. On the other hand, with respect to the input of the electric signal to the integrated circuit, the electric signal from the outside is transmitted to the integrated circuit by following the route opposite to the above route.

【0020】次に、図2を参照して、この発明に基づく
第2の実施例について説明する。図2は、この発明に基
づく第2の実施例における半導体装置を示す断面図であ
る。図2を参照して、上記の第1の実施例においては、
単体パッケージのものを示した。しかし、この単体パッ
ケージ9を複数個モジュール内に収納してもよい。この
単体パッケージ9は、上記の第1の実施例における半導
体装置の放熱フィン7を除いた構造を有するものである
と考えてよい。
Next, a second embodiment based on the present invention will be described with reference to FIG. FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. Referring to FIG. 2, in the first embodiment described above,
A single package is shown. However, a plurality of this single package 9 may be housed in a module. It can be considered that the single package 9 has a structure excluding the radiation fins 7 of the semiconductor device according to the first embodiment.

【0021】次に、図3を参照して、この発明に基づく
第3の実施例について説明する。図3は、この発明に基
づく第3の実施例における半導体装置を示す断面図であ
る。図3を参照して、本実施例においては、複数個の半
導体基板1が半導体装置内に設けられている。上記の第
2の実施例のように、単体パッケージを複数個モジュー
ル内に収納するのではなく、半導体基板1を半導体装置
内に複数個収納し、モジュールとしてもよい。
Next, a third embodiment according to the present invention will be described with reference to FIG. FIG. 3 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. Referring to FIG. 3, in the present embodiment, a plurality of semiconductor substrates 1 are provided in the semiconductor device. Instead of housing a plurality of single packages in a module as in the second embodiment, a plurality of semiconductor substrates 1 may be housed in a semiconductor device to form a module.

【0022】なお、上記の各実施例において、異方性導
電ゴム8内の金属細線の端部または集積回路の該当する
端子、あるいは多層セラミック基板2の該当する端子に
はんだを形成して相互に接合してもよい。以上のよう
に、上記の各実施例によれば、異方性導電ゴム8を用い
ることによって実装密度を高くすることができ、また、
半導体装置を放熱フィン7側に接合することによって、
集積回路に発生する熱を効果的に放散させることが可能
となる。
In each of the above-described embodiments, solder is formed on the ends of the thin metal wires in the anisotropic conductive rubber 8 or the corresponding terminals of the integrated circuit, or the corresponding terminals of the multilayer ceramic substrate 2 to form mutual solder. You may join. As described above, according to each of the above-described embodiments, the mounting density can be increased by using the anisotropic conductive rubber 8, and
By joining the semiconductor device to the radiation fin 7 side,
The heat generated in the integrated circuit can be effectively dissipated.

【0023】次に、図5を用いて、この発明に基づく第
4の実施例について説明する。図5は、この発明に基づ
く第4の実施例における半導体装置を示す断面図であ
る。図5を参照して、本実施例においては、放熱フィン
7に熱伝導ゴム10を介してシリコン基板9が接合され
ている。このシリコン基板9には、集積回路が形成され
た半導体基板1が接合されている。このシリコン基板9
は、GaAsなどの半導体基板でもよい。
Next, a fourth embodiment based on the present invention will be described with reference to FIG. FIG. 5 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention. Referring to FIG. 5, in this embodiment, the silicon substrate 9 is bonded to the heat radiation fin 7 via the heat conductive rubber 10. The semiconductor substrate 1 having an integrated circuit formed thereon is bonded to the silicon substrate 9. This silicon substrate 9
May be a semiconductor substrate such as GaAs.

【0024】半導体基板1に形成された集積回路の電極
と、シリコン基板9表面に形成された配線層とは、ワイ
ヤ3を介して電気的に接続されている。そして、本実施
例においては、異方性導電ゴム8を介して、シリコン基
板9表面に形成された配線層と、多層セラミック基板2
に形成された配線層とが電気的に接続されることにな
る。多層セラミック基板2の内部配線層4と異方性導電
ゴム8とは電気的に接続され、内部配線層4と入出力ピ
ン5とは電気的に接続される。
The electrodes of the integrated circuit formed on the semiconductor substrate 1 and the wiring layer formed on the surface of the silicon substrate 9 are electrically connected via the wires 3. In this embodiment, the wiring layer formed on the surface of the silicon substrate 9 and the multilayer ceramic substrate 2 with the anisotropic conductive rubber 8 interposed therebetween.
It is electrically connected to the wiring layer formed in. The internal wiring layer 4 of the multilayer ceramic substrate 2 and the anisotropic conductive rubber 8 are electrically connected, and the internal wiring layer 4 and the input / output pin 5 are electrically connected.

【0025】以上のように、シリコン基板9を設けるこ
とによって、集積回路を高密度に実装することが可能と
なる理由について、図8を用いて説明する。図8は、多
層セラミック基板2上に配線層16を形成した場合と、
シリコン基板9上に配線層17を形成した場合とを比較
するための模式図である。
The reason why the integrated circuit can be mounted at a high density by providing the silicon substrate 9 as described above will be described with reference to FIG. FIG. 8 shows the case where the wiring layer 16 is formed on the multilayer ceramic substrate 2,
FIG. 6 is a schematic diagram for comparison with a case where a wiring layer 17 is formed on a silicon substrate 9.

【0026】図8を参照して、従来は、多層セラミック
基板2上に半導体基板1がダイボンドされていた。した
がって、配線層16は、多層セラミック基板2上に形成
されていた。多層セラミック基板2上に配線層を形成し
た場合には、従来例で説明したように、配線幅が大きく
なる。たとえば、アルミナなどの材質からなるセラミッ
ク基板2に、スクリーン印刷を行なうことによって配線
層を形成した場合、形成された配線層の平面的な幅L
は、100μm程度のオーダとなる。
Referring to FIG. 8, conventionally, semiconductor substrate 1 is die-bonded on multilayer ceramic substrate 2. Therefore, the wiring layer 16 was formed on the multilayer ceramic substrate 2. When the wiring layer is formed on the multilayer ceramic substrate 2, the wiring width becomes large as described in the conventional example. For example, when a wiring layer is formed by screen printing on a ceramic substrate 2 made of a material such as alumina, the planar width L of the formed wiring layer is L.
Is on the order of about 100 μm.

【0027】それに対し、本件で用いているシリコン基
板9上に配線層17を形成した場合には、配線層17の
平面的な幅L1は、サブミクロンオーダの配線幅とする
ことが可能となる。それにより、配線層17が形成され
る領域は、配線層16が形成される領域に比べて格段に
小さいものとなる。それにより、配線層の形成領域を格
段に縮小することができ、集積回路の実装密度を向上さ
せることが可能となる。
On the other hand, when the wiring layer 17 is formed on the silicon substrate 9 used in this case, the planar width L1 of the wiring layer 17 can be a wiring width on the order of submicrons. . As a result, the area where the wiring layer 17 is formed is significantly smaller than the area where the wiring layer 16 is formed. As a result, the formation area of the wiring layer can be significantly reduced, and the packaging density of the integrated circuit can be improved.

【0028】ここで再び図5を参照して、本実施例にお
いても、半導体基板1は、放熱フィン7側に接合されて
いるため、上記の各実施例と同様に、放熱特性を向上さ
せることが可能となる。上記の構造を有するこの発明に
基づく第4の実施例における半導体装置の製造方法とし
ては、まず集積回路が形成された半導体基板1をシリコ
ン基板9上に接合し、シリコン基板9を放熱フィン7に
接合する。そして、多層セラミック基板2とシリコン基
板9との間に異方性導電ゴム8を挿入し、放熱フィン7
によって集積回路を気密封止する。
Referring again to FIG. 5, also in this embodiment, since the semiconductor substrate 1 is bonded to the heat radiation fin 7 side, the heat radiation characteristics should be improved as in the above-mentioned respective embodiments. Is possible. In the method of manufacturing the semiconductor device having the above structure according to the fourth embodiment of the present invention, first, the semiconductor substrate 1 on which the integrated circuit is formed is bonded onto the silicon substrate 9, and the silicon substrate 9 is connected to the heat radiation fin 7. To join. Then, the anisotropic conductive rubber 8 is inserted between the multilayer ceramic substrate 2 and the silicon substrate 9 to dissipate the heat radiation fins 7.
To hermetically seal the integrated circuit.

【0029】次に、上記の構造を有するこの発明に基づ
く第4の実施例における半導体装置の動作について説明
する。まず、集積回路からの電気信号が、ワイヤ3、シ
リコン基板9上の相互配線層、異方性導電ゴム8および
多層セラミック基板2の内部配線4を経由して、入出力
ピン5に伝達される。それにより、外部への電気信号の
伝達が行なわれることになる。外部からの電気信号の入
力は、上記の場合と逆の経路を経て集積回路に達するこ
とになる。
Next, the operation of the semiconductor device having the above structure according to the fourth embodiment of the present invention will be described. First, an electric signal from the integrated circuit is transmitted to the input / output pin 5 via the wire 3, the interconnection layer on the silicon substrate 9, the anisotropic conductive rubber 8 and the internal wiring 4 of the multilayer ceramic substrate 2. . As a result, the electric signal is transmitted to the outside. The input of the electric signal from the outside reaches the integrated circuit through the route opposite to the above case.

【0030】次に、図6を参照して、この発明に基づく
第5の実施例について説明する。図6は、この発明に基
づく第5の実施例における半導体装置を示す断面図であ
る。図6を参照して、上記の第5の実施例においては、
シリコン基板9にワイヤボンドしたものを示した。しか
し、図6に示されるように、バンプ11を介してフリッ
プチップボンドしてもよい。それにより、さらに実装密
度を向上させることが可能となる。
Next, a fifth embodiment according to the present invention will be described with reference to FIG. FIG. 6 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention. Referring to FIG. 6, in the above fifth embodiment,
The wire bonded to the silicon substrate 9 is shown. However, as shown in FIG. 6, flip chip bonding may be performed via the bump 11. As a result, the packaging density can be further improved.

【0031】次に、図7を用いて、この発明に基づく第
6の実施例における半導体装置について説明する。図7
は、この発明に基づく第6の実施例における半導体装置
を示す断面図である。図7を参照して、本実施例におい
ては、ウェハスケールの半導体基板1を放熱フィン7側
に熱伝導ゴム10を介して接合し、半導体基板1と多層
セラミック基板2とを異方性導電ゴム8を介して電気的
に接続している。それにより、集積回路を高密度に実装
でき、かつ薄型で放熱特性の高い半導体装置を得ること
が可能となる。
Next, a semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIG. Figure 7
FIG. 11 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention. With reference to FIG. 7, in the present embodiment, the wafer-scale semiconductor substrate 1 is bonded to the radiation fin 7 side via the heat conductive rubber 10, and the semiconductor substrate 1 and the multilayer ceramic substrate 2 are anisotropically conductive rubber. It is electrically connected via 8. As a result, it is possible to mount the integrated circuit at a high density and obtain a thin semiconductor device having high heat dissipation characteristics.

【0032】[0032]

【発明の効果】以上のように、この発明によれば、1つ
の局面では、半導体基板を介して、集積回路が形成され
た半導体基板を放熱フィン側に接合した。半導体基板に
は、セラミックなどからなる絶縁基板上に形成される配
線層の平面的な幅よりも格段に細い幅を有する配線層を
形成することが可能となるため、結果的に集積回路の実
装密度を向上させることが可能となる。また、放熱フィ
ン側に半導体基板が接合されているため、放熱特性を向
上させることが可能となる。
As described above, according to the present invention, in one aspect, the semiconductor substrate on which the integrated circuit is formed is bonded to the radiation fin side via the semiconductor substrate. Since it is possible to form a wiring layer having a width much smaller than the planar width of the wiring layer formed on the insulating substrate made of ceramic or the like on the semiconductor substrate, as a result, the mounting of the integrated circuit can be achieved. It is possible to improve the density. Further, since the semiconductor substrate is bonded to the heat radiation fin side, it becomes possible to improve the heat radiation characteristics.

【0033】他の局面では、電極接合層によって、集積
回路装置と絶縁基板とが電気的に接続されている。この
とき、電極接合層は、集積回路装置と絶縁基板との間に
挟まれるように配置されるため、ボンディングワイヤ形
成領域を省略でき、実装密度を向上させることが可能と
なる。この場合も、半導体基板1は放熱フィン側に接合
されているため、放熱特性は向上する。
In another aspect, the integrated circuit device and the insulating substrate are electrically connected by the electrode bonding layer. At this time, since the electrode bonding layer is arranged so as to be sandwiched between the integrated circuit device and the insulating substrate, the bonding wire formation region can be omitted and the packaging density can be improved. Also in this case, since the semiconductor substrate 1 is bonded to the radiation fin side, the radiation characteristics are improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明に基づく第1の実施例における半導体
装置を示す断面図である。
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図2】この発明に基づく第2の実施例における半導体
装置を示す断面図である。
FIG. 2 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

【図3】この発明に基づく第3の実施例における半導体
装置を示す断面図である。
FIG. 3 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

【図4】半導体基板と多層セラミック基板との間の接続
部分を部分拡大した断面図である。
FIG. 4 is a partially enlarged sectional view of a connecting portion between a semiconductor substrate and a multilayer ceramic substrate.

【図5】この発明に基づく第4の実施例における半導体
装置を示す断面図である。
FIG. 5 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

【図6】この発明に基づく第5の実施例における半導体
装置を示す断面図である。
FIG. 6 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention.

【図7】この発明に基づく第6の実施例における半導体
装置を示す断面図である。
FIG. 7 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention.

【図8】多層セラミック基板上に配線層を形成した場合
と、シリコン基板上に配線層を形成した場合の配線幅の
違いに基づく実装密度の差異を説明するための説明図で
ある。
FIG. 8 is an explanatory diagram for explaining a difference in mounting density based on a difference in wiring width between a case where a wiring layer is formed on a multilayer ceramic substrate and a case where a wiring layer is formed on a silicon substrate.

【図9】従来の半導体装置の一例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device.

【図10】従来の半導体装置の他の例を示す断面図であ
る。
FIG. 10 is a cross-sectional view showing another example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1,21 半導体基板 2,22 多層セラミック基板 3,23 ワイヤ 4,24 内部配線 5,25 入出力ピン 6,26 蓋 7,27 放熱フィン 8 異方性導電ゴム 9 単体パッケージ 10 熱伝導ゴム 11 バンプ 12,13 電極 14 導電層 15 絶縁層 1, 21 Semiconductor substrate 2, 22 Multilayer ceramic substrate 3, 23 Wire 4, 24 Internal wiring 5, 25 Input / output pin 6, 26 Lid 7, 27 Radiating fin 8 Anisotropic conductive rubber 9 Single package 10 Thermal conductive rubber 11 Bump 12, 13 Electrode 14 Conductive layer 15 Insulating layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の接続端子を有する集積回路装置が
形成された第1の半導体基板と、 前記集積回路装置の各接続端子と電気的に接続された複
数の配線層が形成され、前記第1の半導体基板を保持す
る第2の半導体基板と、 前記第2の半導体基板に取付けられ、前記集積回路装置
に発生する熱を放散させるための放熱フィンと、 前記配線層の各々と電気的に接続され外部との信号の入
出力を行なう複数個の入出力端子を有する絶縁基板と、 を備えた半導体装置。
1. A first semiconductor substrate on which an integrated circuit device having a plurality of connection terminals is formed, and a plurality of wiring layers electrically connected to respective connection terminals of the integrated circuit device are formed, A second semiconductor substrate holding the first semiconductor substrate; a heat radiation fin attached to the second semiconductor substrate for dissipating heat generated in the integrated circuit device; A semiconductor device comprising: an insulating substrate having a plurality of input / output terminals that are connected to each other to input / output signals to / from the outside.
【請求項2】 一方の面に複数個の第1電極を有する集
積回路装置が形成された半導体基板と、 前記半導体基板の他方の面に取付けられ、前記集積回路
装置で発生した熱を放散するための放熱フィンと、 一方の面に外部との信号の入出力を行なう複数個の入出
力端子が設けられ、他方の面に複数個の第2電極が形成
された絶縁基板と、 絶縁層と、前記絶縁層を貫通し前記第1電極と前記第2
電極とを電気的に接続する複数個の導電層とを有し、前
記集積回路装置と前記絶縁基板の他方の面との間に配置
された電極接合層と、 を備えた半導体装置。
2. A semiconductor substrate having an integrated circuit device having a plurality of first electrodes formed on one surface, and a semiconductor substrate mounted on the other surface of the semiconductor substrate to dissipate heat generated by the integrated circuit device. For dissipating heat, an insulating substrate on one surface of which a plurality of input / output terminals for inputting / outputting signals to / from the outside are provided and a plurality of second electrodes on the other surface, and an insulating layer. The first electrode and the second electrode penetrating the insulating layer.
A semiconductor device, comprising: a plurality of conductive layers electrically connecting to electrodes; and an electrode bonding layer disposed between the integrated circuit device and the other surface of the insulating substrate.
JP28160892A 1992-10-20 1992-10-20 Semiconductor device Withdrawn JPH06132356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28160892A JPH06132356A (en) 1992-10-20 1992-10-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28160892A JPH06132356A (en) 1992-10-20 1992-10-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06132356A true JPH06132356A (en) 1994-05-13

Family

ID=17641515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28160892A Withdrawn JPH06132356A (en) 1992-10-20 1992-10-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06132356A (en)

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